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Removed 'bools' forwarding in Schematic class

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This commit is contained in:
Vadim Kuznetzov 2016-01-08 15:53:29 +03:00
parent 99dc3fecce
commit 096ae088b6
5 changed files with 35 additions and 30 deletions
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6
qucs/extsimkernels/abstractspicekernel.cpp
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@ -82,11 +82,11 @@ void AbstractSpiceKernel::killThemAll()
* prepared for Xyce simulator. For Ngspice should be false.
* \return Returns true if success, false if netlist preparation fails
*/
bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream, bool xyce)
bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream)
{
QStringList collect;
QPlainTextEdit *err = new QPlainTextEdit;
if (Sch->prepareNetlist(stream,collect,err,true,xyce)==-10) { // Broken netlist
if (Sch->prepareNetlist(stream,collect,err)==-10) { // Broken netlist
output.append(err->toPlainText());
delete err;
return false;
@ -187,7 +187,7 @@ void AbstractSpiceKernel::createSubNetlsit(QTextStream &stream, bool xyce)
header = QString(".SUBCKT %1 ").arg(misc::properName(f));
QList< QPair<int,QString> > ports;
if(!prepareSpiceNetlist(stream,xyce)) {
if(!prepareSpiceNetlist(stream)) {
emit finished();
emit errors(QProcess::FailedToStart);
return;

2
qucs/extsimkernels/abstractspicekernel.h
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@ -51,7 +51,7 @@ protected:
Schematic *Sch;
bool prepareSpiceNetlist(QTextStream &stream, bool xyce = false);
bool prepareSpiceNetlist(QTextStream &stream);
virtual void startNetlist(QTextStream& stream, bool xyce = false);
virtual void createNetlist(QTextStream& stream, int NumPorts,QStringList& simulations,
QStringList& vars, QStringList &outputs);

2
qucs/extsimkernels/xyce.cpp
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@ -70,7 +70,7 @@ void Xyce::createNetlist(QTextStream &stream, int , QStringList &simulations,
QString s;
bool hasParSweep = false;
if(!prepareSpiceNetlist(stream,true)) return; // Unable to perform spice simulation
if(!prepareSpiceNetlist(stream)) return; // Unable to perform spice simulation
startNetlist(stream,true);
// set variable names for named nodes and wires

12
qucs/schematic.h
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@ -276,9 +276,9 @@ private:
public:
static int testFile(const QString &);
bool createLibNetlist(QTextStream*, QPlainTextEdit*, int);
bool createSubNetlist(QTextStream *, int&, QStringList&, QPlainTextEdit*, int, bool spice=false, bool xyce = false);
void createSubNetlistPlain(QTextStream*, QPlainTextEdit*, int, bool spice=false);
int prepareNetlist(QTextStream&, QStringList&, QPlainTextEdit*,bool spice=false, bool xyce = false);
bool createSubNetlist(QTextStream *, int&, QStringList&, QPlainTextEdit*, int);
void createSubNetlistPlain(QTextStream*, QPlainTextEdit*, int);
int prepareNetlist(QTextStream&, QStringList&, QPlainTextEdit*);
QString createNetlist(QTextStream&, int);
bool loadDocument();
void highlightWireLabels (void);
@ -308,12 +308,10 @@ private:
void throughAllNodes(bool, QStringList&, int&);
void propagateNode(QStringList&, int&, Node*);
void collectDigitalSignals(void);
bool giveNodeNames(QTextStream *, int&, QStringList&, QPlainTextEdit*, int,
bool spice = false, bool xyce = false);
bool giveNodeNames(QTextStream *, int&, QStringList&, QPlainTextEdit*, int);
void beginNetlistDigital(QTextStream &);
void endNetlistDigital(QTextStream &);
bool throughAllComps(QTextStream *, int&, QStringList&, QPlainTextEdit *, int,
bool spice = false, bool xyce = false);
bool throughAllComps(QTextStream *, int&, QStringList&, QPlainTextEdit *, int);
DigMap Signals; // collecting node names for VHDL signal declarations
QStringList PortTypes;

43
qucs/schematic_file.cpp
View File

@ -1205,7 +1205,7 @@ void Schematic::propagateNode(QStringList& Collect,
* \return true in case of success (false otherwise)
*/
bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts, bool spice, bool xyce)
QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts)
{
bool r;
QString s;
@ -1283,7 +1283,7 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
d->isVerilog = isVerilog;
d->isAnalog = isAnalog;
d->creatingLib = creatingLib;
r = d->createSubNetlist(stream, countInit, Collect, ErrText, NumPorts,spice,xyce);
r = d->createSubNetlist(stream, countInit, Collect, ErrText, NumPorts);
if (r)
{
i = 0;
@ -1321,8 +1321,10 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
FileList.insert(s, SubFile("LIB", s));
if(isAnalog) {
if (spice) {
if (xyce) r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 16);
if (QucsSettings.DefaultSimulator!=spicecompat::simQucsator) {
if ((QucsSettings.DefaultSimulator==spicecompat::simXyceSer)||
(QucsSettings.DefaultSimulator==spicecompat::simXycePar))
r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 16);
else r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 8);
} else r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 1);
} else {
@ -1357,7 +1359,8 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
FileList.insert(f, SubFile("CIR", f));
SpiceFile *sf = (SpiceFile*)pc;
if (spice) r = sf->createSpiceSubckt(stream);
if (QucsSettings.DefaultSimulator != spicecompat::simQucsator)
r = sf->createSpiceSubckt(stream);
else r = sf->createSubNetlist(stream);
ErrText->appendPlainText(sf->getErrorText());
@ -1408,7 +1411,7 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
// each component. Output into "stream", NodeSets are collected in
// "Collect" and counted with "countInit".
bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts, bool spice, bool xyce)
QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts)
{
// delete the node names
for(Node *pn = DocNodes.first(); pn != 0; pn = DocNodes.next()) {
@ -1432,7 +1435,7 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
}
// go through components
if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts,spice,xyce))
if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts))
return false;
// work on named nodes first in order to preserve the user given names
@ -1489,7 +1492,7 @@ bool Schematic::createLibNetlist(QTextStream *stream, QPlainTextEdit *ErrText,
// ---------------------------------------------------
void Schematic::createSubNetlistPlain(QTextStream *stream, QPlainTextEdit *ErrText,
int NumPorts, bool spice)
int NumPorts)
{
int i, z;
QString s;
@ -1600,7 +1603,7 @@ int NumPorts, bool spice)
if (!spice) {
if (QucsSettings.DefaultSimulator == spicecompat::simQucsator) {
if(isAnalog) {
// ..... analog subcircuit ...................................
@ -1765,13 +1768,12 @@ int NumPorts, bool spice)
// ---------------------------------------------------
// Write the netlist as subcircuit to the text stream 'stream'.
bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts,
bool spice, bool xyce)
QStringList& Collect, QPlainTextEdit *ErrText, int NumPorts)
{
// int Collect_count = Collect.count(); // position for this subcircuit
// TODO: NodeSets have to be put into the subcircuit block.
if(!giveNodeNames(stream, countInit, Collect, ErrText, NumPorts,spice,xyce))
if(!giveNodeNames(stream, countInit, Collect, ErrText, NumPorts))
return false;
/* Example for TODO
@ -1783,8 +1785,8 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
else it++;*/
// Emit subcircuit components
createSubNetlistPlain(stream, ErrText, NumPorts,spice);
if (spice) {
createSubNetlistPlain(stream, ErrText, NumPorts);
if (QucsSettings.DefaultSimulator != spicecompat::simQucsator) {
AbstractSpiceKernel *kern = new AbstractSpiceKernel(this);
QStringList err_lst;
if (!kern->checkSchematic(err_lst)) {
@ -1794,7 +1796,11 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
ErrText->insertPlainText(s);
return false;
}
kern->createSubNetlsit(*stream,xyce);
if ((QucsSettings.DefaultSimulator == spicecompat::simXyceSer)||
(QucsSettings.DefaultSimulator == spicecompat::simXycePar))
kern->createSubNetlsit(*stream,true);
else kern->createSubNetlsit(*stream,false);
delete kern;
}
@ -1806,7 +1812,7 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
// ---------------------------------------------------
// Determines the node names and writes subcircuits into netlist file.
int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
QPlainTextEdit *ErrText,bool spice,bool xyce)
QPlainTextEdit *ErrText)
{
if(showBias > 0) showBias = -1; // do not show DC bias anymore
@ -1867,7 +1873,8 @@ int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
// first line is documentation
if(allTypes & isAnalogComponent) {
if (spice) stream << "*";
if (QucsSettings.DefaultSimulator != spicecompat::simQucsator)
stream << "*";
else stream << '#';
} else if (isVerilog)
stream << "//";
@ -1881,7 +1888,7 @@ int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
}
int countInit = 0; // counts the nodesets to give them unique names
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts,spice,xyce))
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts))
return -10;
if(allTypes & isAnalogComponent)