2007-05-09 Stefan Jahn <stefan@lkcc.org>

* qucs_uk.ts, qtgeneric_uk.ts: Updated Ukrainian translations.
        Thanks to Hse?

        * schematic_file.cpp (giveNodeNames): Allow library component to
        emit analog as well as digital netlist code.

2007-05-09  Stefan Jahn  <stefan@lkcc.org>

        * libcomp.cpp: Enabled library component to emit analog as well as
        digital netlist code.


git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1238 b5b04e8c-4942-46c9-ab4f-83783d557d1c

NEWS

@@ -26,6 +26,7 @@ files.
 Version 0.0.12
 --------------
 
+ * libraries can now contain analog as well as digital subcircuits
  * support for symbolically defined devices
  * new components: exponential voltage and current source
  * added Verilog file component

TODO

@@ -23,6 +23,8 @@ unfixed) have a look at the file BUGS.
 
 (completed tasks are indented one tab)
 
+- handle subcircuits in library components as well as other file
+  references correctly
 - simulation messages are sometimes swallowed by the output parser due
   to the concept how the progress bar is extracted, fix this
 - check if -fno-rtti can be used

qucs/ChangeLog

@@ -1,3 +1,11 @@
+2007-05-09  Stefan Jahn  <stefan@lkcc.org>
+
+	* qucs_uk.ts, qtgeneric_uk.ts: Updated Ukrainian translations.
+	Thanks to Hse?
+
+	* schematic_file.cpp (giveNodeNames): Allow library component to
+	emit analog as well as digital netlist code.
+
 2007-05-08  Stefan Jahn  <stefan@lkcc.org>
 
 	* dialogs/librarydialog.cpp (slotNext): Beside analog models now

qucs/components/ChangeLog

@@ -1,3 +1,8 @@
+2007-05-09  Stefan Jahn  <stefan@lkcc.org>
+
+	* libcomp.cpp: Enabled library component to emit analog as well as
+	digital netlist code.
+
 2007-05-08  Stefan Jahn  <stefan@lkcc.org>
 
 	* verilogfile.cpp, vhdlfile.cpp, spicefile.cpp (createSubNetlist):

qucs/components/libcomp.cpp

@@ -36,6 +36,7 @@ extern QDir QucsWorkDir;
 
 LibComp::LibComp()
 {
+  Type = isComponent;   // both analog and digital
   Description = QObject::tr("Component taken from Qucs library");
 
   Ports.append(new Port(0,  0));  // dummy port because of being device
@@ -200,7 +201,7 @@ int LibComp::loadSymbol()
 }
 
 // -------------------------------------------------------
-bool LibComp::outputSubNetlist(QTextStream *stream)
+bool LibComp::createSubNetlist(QTextStream *stream)
 {
   int r;
   QString FileString;
@@ -210,6 +211,39 @@ bool LibComp::outputSubNetlist(QTextStream *stream)
   return true;
 }
 
+// -------------------------------------------------------
+bool LibComp::createSubNetlist_Verilog(QTextStream *stream)
+{
+  int r;
+  QString FileString;
+  r = loadSection("VerilogModel", FileString);
+  if(r < 0)  return false;
+  (*stream) << "\n" << FileString << "\n";
+  return true;
+}
+
+// -------------------------------------------------------
+bool LibComp::createSubNetlist_VHDL(QTextStream *stream)
+{
+  int r;
+  QString FileString;
+  r = loadSection("VHDLModel", FileString);
+  if(r < 0)  return false;
+  (*stream) << "\n" << FileString << "\n";
+  return true;
+}
+
+// -------------------------------------------------------
+QString LibComp::createType()
+{
+  QString Type = Props.first()->Value;
+  if(!QDir::isRelativePath(Type)) {
+    QFileInfo Info(Type);
+    Type = Info.fileName();
+  }
+  return properName(Type + "_" + Props.next()->Value);
+}
+
 // -------------------------------------------------------
 QString LibComp::netlist()
 {
@@ -220,18 +254,41 @@ QString LibComp::netlist()
     s += " "+p1->Connection->Name;   // node names
 
   // output property
-  QString Type = Props.first()->Value;
-  if(!QDir::isRelativePath(Type)) {
-    QFileInfo Info(Type);
-    Type = Info.fileName();
-  }
-  Type += "_" + Props.next()->Value;
-  Type.replace(QRegExp("\\W"), "_");
-  s += " Type=\""+Type+"\"";   // type for subcircuit
+  s += " Type=\""+createType()+"\"";   // type for subcircuit
 
   // output user defined parameters
-  for(Property *pp = Props.next(); pp != 0; pp = Props.next())
+  for(Property *pp = Props.at(2); pp != 0; pp = Props.next())
     s += " "+pp->Name+"=\""+pp->Value+"\"";
 
   return s + '\n';
 }
+
+// -------------------------------------------------------
+QString LibComp::verilogCode(int)
+{
+  QString s = "  Sub_" + createType() + " " + Name + " (";
+
+  // output all node names
+  Port *pp = Ports.first();
+  if(pp)  s += pp->Connection->Name;
+  for(pp = Ports.next(); pp != 0; pp = Ports.next())
+    s += ", "+pp->Connection->Name;   // node names
+
+  s += ");\n";
+  return s;
+}
+
+// -------------------------------------------------------
+QString LibComp::vhdlCode(int)
+{
+  QString s = "  " + Name + ": entity Sub_" + createType() + " port map (";
+
+  // output all node names
+  Port *pp = Ports.first();
+  if(pp)  s += pp->Connection->Name;
+  for(pp = Ports.next(); pp != 0; pp = Ports.next())
+    s += ", "+pp->Connection->Name;   // node names
+
+  s += ");\n";
+  return s;
+}

qucs/components/libcomp.h

@@ -26,15 +26,21 @@ public:
   LibComp();
  ~LibComp() {};
   Component* newOne();
-  bool outputSubNetlist(QTextStream*);
+
+  bool createSubNetlist(QTextStream*);
+  bool createSubNetlist_Verilog(QTextStream*);
+  bool createSubNetlist_VHDL(QTextStream*);
 
 protected:
   QString netlist();
+  QString vhdlCode(int);
+  QString verilogCode(int);
   void createSymbol();
 
 private:
   int  loadSymbol();
   int  loadSection(const QString&, QString&);
+  QString createType();
 };
 
 #endif

qucs/schematic_file.cpp

@@ -875,11 +875,19 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
         continue;   // insert each subcircuit just one time
 
       StringList.append(s);
-      r = ((LibComp*)pc)->outputSubNetlist(stream);
+      if(NumPorts < 0)
+	r = ((LibComp*)pc)->createSubNetlist(stream);
+      else {
+	if(isVerilog)
+	  r = ((LibComp*)pc)->createSubNetlist_Verilog(stream);
+	else
+	  r = ((LibComp*)pc)->createSubNetlist_VHDL(stream);
+      }
       if(!r) {
-        ErrText->insert(
-        QObject::tr("ERROR: Cannot load library component \"%1\".").arg(pc->Name));
-        return false;
+	ErrText->insert(
+	    QObject::tr("ERROR: Cannot load library component \"%1\".").
+	    arg(pc->Name));
+	return false;
       }
       continue;
     }
@@ -902,9 +910,9 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
       Collect.append(s);
 #else
       SpiceFile *sf = (SpiceFile*)pc;
-      bool ret = sf->createSubNetlist(stream);
+      r = sf->createSubNetlist(stream);
       ErrText->insert(sf->getErrorText());
-      if(!ret) return false;
+      if(!r) return false;
 #endif
       continue;
     }
@@ -946,15 +954,15 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
 #else
       if(pc->Model == "VHDL") {
 	VHDL_File *vf = (VHDL_File*)pc;
-	bool ret = vf->createSubNetlist(stream);
+	r = vf->createSubNetlist(stream);
 	ErrText->insert(vf->getErrorText());
-	if(!ret) return false;
+	if(!r) return false;
       }
       if(pc->Model == "Verilog") {
 	Verilog_File *vf = (Verilog_File*)pc;
-	bool ret = vf->createSubNetlist(stream);
+	r = vf->createSubNetlist(stream);
 	ErrText->insert(vf->getErrorText());
-	if(!ret) return false;
+	if(!r) return false;
       }      
 #endif
       continue;