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Merge branch 'digital' into revised_examples

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This commit is contained in:
Vadim Kuznetsov 2022-10-30 11:58:17 +03:00
commit 0ffc3dbeee
13 changed files with 71 additions and 23 deletions
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30
qucs/components/component.cpp
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@ -1473,22 +1473,24 @@ QString GateComponent::netlist()
return s;
}
QString GateComponent::spice_netlist(bool)
QString GateComponent::spice_netlist(bool isXyce)
{
QString s = Model+Name;
if (isXyce) return QString("");
// output all node names
foreach(Port *pp, Ports)
s += " "+pp->Connection->Name; // node names
// output all properties
Property *p = Props.at(1);
s += " " + p->Name + "=\"" + p->Value + "\"";
p = Props.next();
s += " " + p->Name + "=\"" + p->Value + "\"";
p = Props.next();
s += " " + p->Name + "=\"" + p->Value + "\"\n";
return s;
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString type = "d_" + Model;
type = type.toLower();
QString td = spicecompat::normalize_value(getProperty("t")->Value);
s += " [";
for (int i = Ports.count(); i >= 2; i--) {
s += " " + Ports.at(i-1)->Connection->Name;
}
s += "] " + Ports.at(0)->Connection->Name;
s += " " + tmp_model + "\n";
s += QString(".model %1 %2(rise_delay=%3 fall_delay=%3 input_load=5e-13)\n")
.arg(tmp_model).arg(type).arg(td);
return s;
}
// -------------------------------------------------------

2
qucs/components/component.h
View File

@ -132,7 +132,7 @@ class GateComponent : public MultiViewComponent {
public:
GateComponent();
QString netlist();
QString spice_netlist(bool);
QString spice_netlist(bool isXyce);
QString vhdlCode(int);
QString verilogCode(int);

1
qucs/components/logical_and.cpp
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@ -21,6 +21,7 @@ Logical_AND::Logical_AND()
{
Description = QObject::tr("logical AND");
Model = "AND";
SpiceModel = "A";
createSymbol();
tx = x1+4;

17
qucs/components/logical_buf.cpp
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@ -18,6 +18,7 @@
#include "schematic.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
Logical_Buf::Logical_Buf()
@ -42,6 +43,7 @@ Logical_Buf::Logical_Buf()
ty = y2+4;
Model = "Buf";
Name = "Y";
SpiceModel = "A";
}
// -------------------------------------------------------
@ -133,3 +135,18 @@ Element* Logical_Buf::info(QString& Name, char* &BitmapFile, bool getNewOne)
if(getNewOne) return new Logical_Buf();
return 0;
}
QString Logical_Buf::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("t")->Value);
s += " " + Ports.at(1)->Connection->Name;
s += " " + Ports.at(0)->Connection->Name;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_buffer(rise_delay=%2 fall_delay=%2 input_load=5e-13)\n")
.arg(tmp_model).arg(td);
return s;
}

1
qucs/components/logical_buf.h
View File

@ -31,6 +31,7 @@ public:
protected:
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
void createSymbol();
};

17
qucs/components/logical_inv.cpp
View File

@ -18,6 +18,7 @@
#include "schematic.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
Logical_Inv::Logical_Inv()
@ -42,6 +43,7 @@ Logical_Inv::Logical_Inv()
ty = y2+4;
Model = "Inv";
Name = "Y";
SpiceModel = "A";
}
// -------------------------------------------------------
@ -150,3 +152,18 @@ Element* Logical_Inv::info(QString& Name, char* &BitmapFile, bool getNewOne)
if(getNewOne) return new Logical_Inv();
return 0;
}
QString Logical_Inv::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("t")->Value);
s += " " + Ports.at(1)->Connection->Name;
s += " " + Ports.at(0)->Connection->Name;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_inverter(rise_delay=%2 fall_delay=%2 input_load=5e-13)\n")
.arg(tmp_model).arg(td);
return s;
}

1
qucs/components/logical_inv.h
View File

@ -29,6 +29,7 @@ public:
static Element* info(QString&, char* &, bool getNewOne=false);
protected:
QString spice_netlist(bool isXyce);
QString vhdlCode(int);
QString verilogCode(int);
void createSymbol();

2
qucs/components/logical_nand.cpp
View File

@ -16,11 +16,13 @@
***************************************************************************/
#include "logical_nand.h"
#include "node.h"
Logical_NAND::Logical_NAND()
{
Description = QObject::tr("logical NAND");
Model = "NAND";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_nor.cpp
View File

@ -21,6 +21,7 @@ Logical_NOR::Logical_NOR()
{
Description = QObject::tr("logical NOR");
Model = "NOR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_or.cpp
View File

@ -21,6 +21,7 @@ Logical_OR::Logical_OR()
{
Description = QObject::tr("logical OR");
Model = "OR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_xnor.cpp
View File

@ -21,6 +21,7 @@ Logical_XNOR::Logical_XNOR()
{
Description = QObject::tr("logical XNOR");
Model = "XNOR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_xor.cpp
View File

@ -21,6 +21,7 @@ Logical_XOR::Logical_XOR()
{
Description = QObject::tr("logical XOR");
Model = "XOR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

19
qucs/module.cpp
View File

@ -443,14 +443,6 @@ void Module::registerModules (void) {
// digital components
REGISTER_DIGITAL_1 (Digi_Source);
REGISTER_DIGITAL_1 (Logical_Inv);
REGISTER_DIGITAL_1 (Logical_OR);
REGISTER_DIGITAL_1 (Logical_NOR);
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_NAND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
REGISTER_DIGITAL_1 (Logical_Buf);
REGISTER_DIGITAL_1 (andor4x2);
REGISTER_DIGITAL_1 (andor4x3);
REGISTER_DIGITAL_1 (andor4x4);
@ -488,6 +480,17 @@ void Module::registerModules (void) {
REGISTER_DIGITAL_1 (Digi_Sim);
}
if (QucsSettings.DefaultSimulator == spicecompat::simNgspice ||
QucsSettings.DefaultSimulator == spicecompat::simQucsator) {
REGISTER_DIGITAL_1 (Logical_Buf);
REGISTER_DIGITAL_1 (Logical_Inv);
REGISTER_DIGITAL_1 (Logical_NAND);
REGISTER_DIGITAL_1 (Logical_OR);
REGISTER_DIGITAL_1 (Logical_NOR);
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
}
// file components
REGISTER_FILE_1 (SpiceFile);