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2009-09-12 Stefan Jahn <stefan@lkcc.org>

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* library/Transistors.lib: Added BD139 transistor provided by
        Frans Schreuder.  Thanks!


git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1729 b5b04e8c-4942-46c9-ab4f-83783d557d1c
This commit is contained in:
ela 2009-09-12 15:59:29 +00:00
parent afaff3ddde
commit 1aefc0ad6c
5 changed files with 34 additions and 14 deletions
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5
qucs-lib/ChangeLog
View File

@ -1,3 +1,8 @@
2009-09-12 Stefan Jahn <stefan@lkcc.org>
* library/Transistors.lib: Added BD139 transistor provided by
Frans Schreuder. Thanks!
2009-05-04 Stefan Jahn <stefan@lkcc.org>
* library/Ideal.lib: Fixed symbols of LP1 and VSum.

15
qucs-lib/library/Transistors.lib
View File

@ -1757,6 +1757,21 @@
</Model>
</Component>
<Component BD139>
<Description>
BD139 NPN EPITAXIAL SILICON TRANSISTOR
MEDIUM POWER LINEAR AND SWITCHING APPLICATIONS
BVcbo: 80V
BVceo: 80V
BVebo: 5V
Complement to BD140
added by Frans Schreuder <f.p.schreuder@rug.nl>
</Description>
<Model>
<_BJT BD139_ 1 0 0 8 -26 0 0 "npn" 0 "1e-9" 0 "0.85" 0 "1.33751" 0 "0.166126" 0 "1.66126" 0 "36.4079" 0 "142.931" 0 "5.03418e-09" 0 "1.45313 " 0 "5.02557e-09" 0 "3.10227" 0 "222.664" 0 "1.35467" 0 "0.1" 0 "0.1" 0 "1.04109" 0 "0.000472454" 0 "26.9143" 0 "1e-11" 0 "0.75" 0 "0.33" 0 "1e-11" 0 "0.75" 0 "0.33" 0 "0.9" 0 "0" 0 "0.75" 0 "0.5" 0 "0.5" 0 "1e-09" 0 "1" 0 "10" 0 "0.01" 0 "1e-07" 0 "26.85" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "0.727762" 0 "1.04311" 0 "1.05" 0 "26.85" 0 "1" 0>
</Model>
</Component>
<Component BF720>
<Description>
Si npn 1.5W 300V 100mA 60MHz pkg:SOT-223 2,1,3

2
qucs/node.cpp
View File

@ -25,7 +25,7 @@ Node::Node(int _x, int _y)
Label = 0;
Type = isNode;
State = 0;
Type = "";
DType = "";
cx = _x;
cy = _y;

6
qucs/node.h
View File

@ -37,9 +37,9 @@ public:
void setName(const QString&, const QString&, int x_=0, int y_=0);
QPtrList<Element> Connections;
QString Name; // node name used by creation of netlist
QString Type; // type of node (used by digital files)
int State; // remember some things during some operations
QString Name; // node name used by creation of netlist
QString DType; // type of node (used by digital files)
int State; // remember some things during some operations
};
#endif

20
qucs/schematic_file.cpp
View File

@ -338,11 +338,11 @@ void Schematic::simpleInsertComponent(Component *c)
// check if new node lies upon existing node
for(pn = DocNodes.first(); pn != 0; pn = DocNodes.next())
if(pn->cx == x) if(pn->cy == y) {
if (!pn->Type.isEmpty()) {
pp->Type = pn->Type;
if (!pn->DType.isEmpty()) {
pp->Type = pn->DType;
}
if (!pp->Type.isEmpty()) {
pn->Type = pp->Type;
pn->DType = pp->Type;
}
break;
}
@ -353,7 +353,7 @@ void Schematic::simpleInsertComponent(Component *c)
}
pn->Connections.append(c); // connect schematic node to component node
if (!pp->Type.isEmpty()) {
pn->Type = pp->Type;
pn->DType = pp->Type;
}
pp->Connection = pn; // connect component node to schematic node
@ -787,9 +787,9 @@ void Schematic::collectDigitalSignals(void)
for(pn = DocNodes.first(); pn != 0; pn = DocNodes.next()) {
DigMap::Iterator it = Signals.find(pn->Name);
if(it == Signals.end()) { // avoid redeclaration of signal
Signals.insert(pn->Name, DigSignal(pn->Name, pn->Type));
} else if (!pn->Type.isEmpty()) {
it.data().Type = pn->Type;
Signals.insert(pn->Name, DigSignal(pn->Name, pn->DType));
} else if (!pn->DType.isEmpty()) {
it.data().Type = pn->DType;
}
}
}
@ -882,7 +882,7 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
// apply in/out signal types of subcircuit
for(Port *pp = pc->Ports.first(); pp; pp = pc->Ports.next(), i++) {
pp->Type = it.data().PortTypes[i];
pp->Connection->Type = pp->Type;
pp->Connection->DType = pp->Type;
}
}
continue; // insert each subcircuit just one time
@ -908,7 +908,7 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
// save in/out signal types of subcircuit
for(Port *pp = pc->Ports.first(); pp; pp = pc->Ports.next(), i++) {
pp->Type = d->PortTypes[i];
pp->Connection->Type = pp->Type;
pp->Connection->DType = pp->Type;
}
sub.PortTypes = d->PortTypes;
FileList.replace(f, sub);
@ -1142,7 +1142,7 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
DigMap::Iterator it = Signals.find(*it_name);
(*it_type) = it.data().Type;
// propagate type to port symbol
pc->Ports.getFirst()->Connection->Type = *it_type;
pc->Ports.getFirst()->Connection->DType = *it_type;
if(!isAnalog) {
if (isVerilog) {