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Quick fix for .FOUR simulation with Xyce; old circuits are operational

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This commit is contained in:
Vadim Kuznetsov 2022-02-18 22:05:43 +01:00
parent c9ffce91a7
commit 35b5cbc285
2 changed files with 4 additions and 2 deletions
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4
qucs/extsimkernels/abstractspicekernel.cpp
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@ -1008,6 +1008,7 @@ void AbstractSpiceKernel::convertToQucsData(const QString &qucs_dataset)
bool hasParSweep = false;
bool hasDblParSweep = false;
QRegExp four_rx(".*\\.four[0-9]+$");
QString full_outfile = workdir+QDir::separator()+ngspice_output_filename;
if (ngspice_output_filename.endsWith("HB.FD.prn")) {
parseHBOutput(full_outfile,sim_points,var_list,hasParSweep);
@ -1017,7 +1018,8 @@ void AbstractSpiceKernel::convertToQucsData(const QString &qucs_dataset)
+ "spice4qucs.hb.cir.res");
parseResFile(res_file,swp_var,swp_var_val);
}
} else if (ngspice_output_filename.endsWith(".four")) {
} else if (ngspice_output_filename.endsWith(".four") ||
four_rx.exactMatch(ngspice_output_filename)) {
isComplex=false;
parseFourierOutput(full_outfile,sim_points,var_list);
} else if (ngspice_output_filename.endsWith(".ngspice.sens.dc.prn")) {

2
qucs/extsimkernels/xyce.cpp
View File

@ -166,7 +166,7 @@ void Xyce::createNetlist(QTextStream &stream, int , QStringList &simulations,
if (pc1->Model==".FOURIER") {
if (pc1->Props.at(0)->Value==pc->Name) {
QString s1 = pc1->getSpiceNetlist(true);
outputs.append("spice4qucs.tran.cir.four");
outputs.append("spice4qucs.tran.cir.four0");
stream<<s1;
}
}