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Move spice entry for logical gates to component.cpp

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This commit is contained in:
Vadim Kuznetsov 2022-10-06 17:42:15 +03:00
parent d347585a38
commit 443efab7a6
10 changed files with 32 additions and 43 deletions
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30
qucs/components/component.cpp
View File

@ -1473,22 +1473,24 @@ QString GateComponent::netlist()
return s;
}
QString GateComponent::spice_netlist(bool)
QString GateComponent::spice_netlist(bool isXyce)
{
QString s = Model+Name;
if (isXyce) return QString("");
// output all node names
foreach(Port *pp, Ports)
s += " "+pp->Connection->Name; // node names
// output all properties
Property *p = Props.at(1);
s += " " + p->Name + "=\"" + p->Value + "\"";
p = Props.next();
s += " " + p->Name + "=\"" + p->Value + "\"";
p = Props.next();
s += " " + p->Name + "=\"" + p->Value + "\"\n";
return s;
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString type = "d_" + Model;
type = type.toLower();
QString td = spicecompat::normalize_value(getProperty("t")->Value);
s += " [";
for (int i = Ports.count(); i >= 2; i--) {
s += " " + Ports.at(i-1)->Connection->Name;
}
s += "] " + Ports.at(0)->Connection->Name;
s += " " + tmp_model + "\n";
s += QString(".model %1 %2(rise_delay=%3 fall_delay=%3 input_load=5e-13)\n")
.arg(tmp_model).arg(type).arg(td);
return s;
}
// -------------------------------------------------------

2
qucs/components/component.h
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@ -132,7 +132,7 @@ class GateComponent : public MultiViewComponent {
public:
GateComponent();
QString netlist();
QString spice_netlist(bool);
QString spice_netlist(bool isXyce);
QString vhdlCode(int);
QString verilogCode(int);

1
qucs/components/logical_and.cpp
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@ -21,6 +21,7 @@ Logical_AND::Logical_AND()
{
Description = QObject::tr("logical AND");
Model = "AND";
SpiceModel = "A";
createSymbol();
tx = x1+4;

19
qucs/components/logical_nand.cpp
View File

@ -17,7 +17,6 @@
#include "logical_nand.h"
#include "node.h"
#include "extsimkernels/spicecompat.h"
Logical_NAND::Logical_NAND()
{
@ -51,21 +50,3 @@ Element* Logical_NAND::info(QString& Name, char* &BitmapFile, bool getNewOne)
if(getNewOne) return new Logical_NAND();
return 0;
}
QString Logical_NAND::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("t")->Value);
s += " [";
for (int i = Ports.count(); i >= 2; i--) {
s += " " + Ports.at(i-1)->Connection->Name;
}
s += "] " + Ports.at(0)->Connection->Name;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_nand(rise_delay=%2 fall_delay=%2 input_load=5e-13)\n")
.arg(tmp_model).arg(td);
return s;
}

2
qucs/components/logical_nand.h
View File

@ -27,8 +27,6 @@ public:
~Logical_NAND();
Component* newOne();
static Element* info(QString&, char* &, bool getNewOne=false);
protected:
QString spice_netlist(bool isXyce);
};
#endif

1
qucs/components/logical_nor.cpp
View File

@ -21,6 +21,7 @@ Logical_NOR::Logical_NOR()
{
Description = QObject::tr("logical NOR");
Model = "NOR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_or.cpp
View File

@ -21,6 +21,7 @@ Logical_OR::Logical_OR()
{
Description = QObject::tr("logical OR");
Model = "OR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_xnor.cpp
View File

@ -21,6 +21,7 @@ Logical_XNOR::Logical_XNOR()
{
Description = QObject::tr("logical XNOR");
Model = "XNOR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

1
qucs/components/logical_xor.cpp
View File

@ -21,6 +21,7 @@ Logical_XOR::Logical_XOR()
{
Description = QObject::tr("logical XOR");
Model = "XOR";
SpiceModel = "A";
createSymbol();
tx = x1+4;

17
qucs/module.cpp
View File

@ -443,11 +443,6 @@ void Module::registerModules (void) {
// digital components
REGISTER_DIGITAL_1 (Digi_Source);
REGISTER_DIGITAL_1 (Logical_OR);
REGISTER_DIGITAL_1 (Logical_NOR);
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
REGISTER_DIGITAL_1 (Logical_Buf);
REGISTER_DIGITAL_1 (andor4x2);
REGISTER_DIGITAL_1 (andor4x3);
@ -486,8 +481,16 @@ void Module::registerModules (void) {
REGISTER_DIGITAL_1 (Digi_Sim);
}
REGISTER_DIGITAL_1 (Logical_Inv);
REGISTER_DIGITAL_1 (Logical_NAND);
if (QucsSettings.DefaultSimulator == spicecompat::simNgspice ||
QucsSettings.DefaultSimulator == spicecompat::simQucsator) {
REGISTER_DIGITAL_1 (Logical_Inv);
REGISTER_DIGITAL_1 (Logical_NAND);
REGISTER_DIGITAL_1 (Logical_OR);
REGISTER_DIGITAL_1 (Logical_NOR);
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
}
// file components
REGISTER_FILE_1 (SpiceFile);