2009-11-08 Stefan Jahn <stefan@lkcc.org>

* qucs.cpp (slotSetCompView, fillComboBox, slotSelectComponent):
        Using new module/category interface for filling the component view
        and instantiating components for use on the schematic.

        * module.cpp: New components are now registered in
        registerModules() function for static linking.  This is now the
        only location where to tell the application about such a
        component.

        * module.h (class Module): Implemented new module and category
        classes for use as dynamic lists for available components seen in
        the component tab.

2009-11-08  Stefan Jahn  <stefan@lkcc.org>

        * component.cpp (getComponentFromName): Using new module interface
        for instantiating components currently loaded.
This commit is contained in:
ela 2009-11-08 16:33:19 +00:00
parent e52415564f
commit 4a57e7a062
26 changed files with 1547 additions and 601 deletions

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@ -1,3 +1,18 @@
2009-11-08 Stefan Jahn <stefan@lkcc.org>
* qucs.cpp (slotSetCompView, fillComboBox, slotSelectComponent):
Using new module/category interface for filling the component view
and instantiating components for use on the schematic.
* module.cpp: New components are now registered in
registerModules() function for static linking. This is now the
only location where to tell the application about such a
component.
* module.h (class Module): Implemented new module and category
classes for use as dynamic lists for available components seen in
the component tab.
2009-10-27 Stefan Jahn <stefan@lkcc.org>
* paintings/rectangle.cpp, paintings/portsymbol.cpp,

View File

@ -38,7 +38,7 @@ MOCFILES = $(MOCHEADERS:.h=.moc.cpp)
qucs_SOURCES = node.cpp element.cpp qucsdoc.cpp wire.cpp mouseactions.cpp \
qucs.cpp main.cpp wirelabel.cpp qucs_init.cpp qucs_actions.cpp \
viewpainter.cpp mnemo.cpp schematic.cpp schematic_element.cpp textdoc.cpp \
schematic_file.cpp syntax.cpp
schematic_file.cpp syntax.cpp module.cpp
nodist_qucs_SOURCES = $(MOCFILES)
@ -48,8 +48,8 @@ qucs_LDADD = components/libcomponents.a diagrams/libdiagrams.a \
paintings/libpaintings.a dialogs/libdialogs.a \
$(X11_LIBS) $(QT_LIBS)
noinst_HEADERS = $(MOCHEADERS) main.h wire.h qucsdoc.h element.h \
node.h wirelabel.h viewpainter.h mnemo.h mouseactions.h syntax.h
noinst_HEADERS = $(MOCHEADERS) main.h wire.h qucsdoc.h element.h node.h \
wirelabel.h viewpainter.h mnemo.h mouseactions.h syntax.h module.h
# rules for translations
TRANSLATIONS = qucs_de.ts qucs_pl.ts qucs_fr.ts qucs_it.ts qucs_ro.ts \

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@ -1,3 +1,8 @@
2009-11-08 Stefan Jahn <stefan@lkcc.org>
* component.cpp (getComponentFromName): Using new module interface
for instantiating components currently loaded.
2009-10-27 Stefan Jahn <stefan@lkcc.org>
* vafile.cpp (VerilogA_File_Info): Added new class parsing ports

View File

@ -17,13 +17,6 @@
#include <stdlib.h>
#include "components.h"
#include "node.h"
#include "main.h"
#include "qucs.h"
#include "schematic.h"
#include "viewpainter.h"
#include <qdir.h>
#include <qpen.h>
#include <qpoint.h>
@ -32,6 +25,15 @@
#include <qtabwidget.h>
#include <qmessagebox.h>
#include <qdom.h>
#include <qdict.h>
#include "components.h"
#include "node.h"
#include "main.h"
#include "qucs.h"
#include "schematic.h"
#include "viewpainter.h"
#include "module.h"
// ***********************************************************************
// ********** **********
@ -1495,207 +1497,18 @@ Component* getComponentFromName(QString& Line)
return 0;
}
QString cstr = Line.section(' ',0,0); // component type
char first = Line.at(1).latin1(); // first letter of component name
cstr.remove(0,2); // remove leading "<" and first letter
QString cstr = Line.section (' ',0,0); // component type
cstr.remove (0,1); // remove leading "<"
if (cstr == "Lib") c = new LibComp ();
else if (cstr == "Eqn") c = new Equation ();
else if (cstr == "Rus") c = new Resistor (false); // backward compatible
else if (cstr.left (6) == "SPfile" && cstr != "SPfile") {
// backward compatible
c = new SParamFile ();
c->Props.getLast()->Value = cstr.mid (6); }
else
c = Module::getComponent (cstr);
// to speed up the string comparision, they are ordered by the first
// letter of their name
switch(first) {
case 'R' : if(cstr.isEmpty()) c = new Resistor();
else if(cstr == "ECTLINE") c = new RectLine();
else if(cstr == "us") c = new Resistor(false); // backward capatible
else if(cstr == "SFF") c = new RS_FlipFlop();
else if(cstr == "elais") c = new Relais();
else if(cstr == "FEDD") c = new RFedd();
else if(cstr == "FEDD2P") c = new RFedd2P();
else if(cstr == "LCG") c = new RLCG();
break;
case 'C' : if(cstr.isEmpty()) c = new Capacitor();
else if(cstr == "CCS") c = new CCCS();
else if(cstr == "CVS") c = new CCVS();
else if(cstr == "irculator") c = new Circulator();
else if(cstr == "oupler") c = new Coupler();
else if(cstr == "LIN") c = new Coplanar();
else if(cstr == "OPEN") c = new CPWopen();
else if(cstr == "SHORT") c = new CPWshort();
else if(cstr == "GAP") c = new CPWgap();
else if(cstr == "STEP") c = new CPWstep();
else if(cstr == "OAX") c = new CoaxialLine();
break;
case 'L' : if(cstr.isEmpty()) c = new Inductor();
else if(cstr == "ib") c = new LibComp();
break;
case 'G' : if(cstr == "ND") c = new Ground();
else if(cstr == "yrator") c = new Gyrator();
break;
case 'I' : if(cstr == "Probe") c = new iProbe();
else if(cstr == "dc") c = new Ampere_dc();
else if(cstr == "ac") c = new Ampere_ac();
else if(cstr == "noise") c = new Ampere_noise();
else if(cstr == "solator") c = new Isolator();
else if(cstr == "pulse") c = new iPulse();
else if(cstr == "rect") c = new iRect();
else if(cstr == "Inoise") c = new Noise_ii();
else if(cstr == "Vnoise") c = new Noise_iv();
else if(cstr == "nv") c = new Logical_Inv();
else if(cstr == "exp") c = new iExp();
else if(cstr == "file") c = new iFile();
break;
case 'J' : if(cstr == "FET") c = new JFET();
else if(cstr == "KFF") c = new JK_FlipFlop();
break;
case 'V' : if(cstr == "dc") c = new Volt_dc();
else if(cstr == "ac") c = new Volt_ac();
else if(cstr == "CCS") c = new VCCS();
else if(cstr == "CVS") c = new VCVS();
else if(cstr == "Probe") c = new vProbe();
else if(cstr == "noise") c = new Volt_noise();
else if(cstr == "pulse") c = new vPulse();
else if(cstr == "rect") c = new vRect();
else if(cstr == "Vnoise") c = new Noise_vv();
else if(cstr == "HDL") c = new VHDL_File();
else if(cstr == "erilog") c = new Verilog_File();
else if(cstr == "exp") c = new vExp();
else if(cstr == "file") c = new vFile();
break;
case 'T' : if(cstr == "r") c = new Transformer();
else if(cstr == "LIN") c = new TLine();
else if(cstr == "LIN4P") c = new TLine_4Port();
else if(cstr == "WIST") c = new TwistedPair();
else if(cstr == "riac") c = new Triac();
break;
case 's' : if(cstr == "Tr") c = new symTrafo();
break;
case 'P' : if(cstr == "ac") c = new Source_ac();
else if(cstr == "ort") c = new SubCirPort();
else if(cstr == "Shift") c = new Phaseshifter();
else if(cstr == "M_Mod") c = new PM_Modulator();
break;
case 'S' : if(cstr == "Pfile") c = new SParamFile();
else if(cstr.left(5) == "Pfile") { // backward compatible
c = new SParamFile();
c->Props.getLast()->Value = cstr.mid(5); }
else if(cstr == "ub") c = new Subcircuit();
else if(cstr == "UBST") c = new Substrate();
else if(cstr == "PICE") c = new SpiceFile();
else if(cstr == "witch") c = new Switch();
else if(cstr == "CR") c = new Thyristor();
break;
case 'D' : if(cstr == "CBlock") c = new dcBlock();
else if(cstr == "CFeed") c = new dcFeed();
else if(cstr == "iode") c = new Diode();
else if(cstr == "igiSource") c = new Digi_Source();
else if(cstr == "FF") c = new D_FlipFlop();
else if(cstr == "iac") c = new Diac();
else if(cstr == "LS_nto1") c = new DLS_nto1();
else if(cstr == "LS_1ton") c = new DLS_1ton();
break;
case 'B' : if(cstr == "iasT") c = new BiasT();
else if(cstr == "JT") c = new BJTsub();
else if(cstr == "OND") c = new BondWire();
else if(cstr == "uf") c = new Logical_Buf();
break;
case 'A' : if(cstr == "ttenuator") c = new Attenuator();
else if(cstr == "mp") c = new Amplifier();
else if(cstr == "ND") c = new Logical_AND();
else if(cstr == "M_Mod") c = new AM_Modulator();
break;
case 'M' : if(cstr == "UT") c = new Mutual();
else if(cstr == "UT2") c = new Mutual2();
else if(cstr == "LIN") c = new MSline();
else if(cstr == "OSFET") c = new MOSFET_sub();
else if(cstr == "STEP") c = new MSstep();
else if(cstr == "CORN") c = new MScorner();
else if(cstr == "TEE") c = new MStee();
else if(cstr == "CROSS") c = new MScross();
else if(cstr == "MBEND") c = new MSmbend();
else if(cstr == "OPEN") c = new MSopen();
else if(cstr == "GAP") c = new MSgap();
else if(cstr == "COUPLED") c = new MScoupled();
else if(cstr == "VIA") c = new MSvia();
else if(cstr == "RSTUB") c = new MSrstub();
else if(cstr == "ESFET") c = new MESFET();
break;
case 'E' : if(cstr == "qn") c = new Equation();
else if(cstr == "DD") c = new EqnDefined();
else if(cstr == "KV26MOS") c = new EKV26MOS();
break;
case 'O' : if(cstr == "pAmp") c = new OpAmp();
else if(cstr == "R") c = new Logical_OR();
break;
case 'N' : if(cstr == "OR") c = new Logical_NOR();
else if(cstr == "AND") c = new Logical_NAND();
break;
case 'n' : if(cstr == "igbt") c = new nigbt();
break;
case '.' : if(cstr == "DC") c = new DC_Sim();
else if(cstr == "AC") c = new AC_Sim();
else if(cstr == "TR") c = new TR_Sim();
else if(cstr == "SP") c = new SP_Sim();
else if(cstr == "HB") c = new HB_Sim();
else if(cstr == "SW") c = new Param_Sweep();
else if(cstr == "Digi") c = new Digi_Sim();
else if(cstr == "Opt") c = new Optimize_Sim();
break;
case '_' : if(cstr == "BJT") c = new BJT();
else if(cstr == "MOSFET") c = new MOSFET();
break;
case 'X' : if(cstr == "OR") c = new Logical_XOR();
else if(cstr == "NOR") c = new Logical_XNOR();
break;
case 'h' : if(cstr == "icumL2V2p1") c = new hicumL2V2p1();
else if(cstr == "ic2_full") c = new hic2_full();
else if(cstr == "ic0_full") c = new hic0_full();
else if(cstr == "icumL0V1p2") c = new hicumL0V1p2();
else if(cstr == "icumL2V2p23") c = new hicumL2V2p23();
else if(cstr == "a1b") c = new ha1b();
else if(cstr == "pribin4bit") c = new hpribin4bit();
break;
case 'H' : if(cstr == "BT_X") c = new HBT_X();
break;
case 'm' : if(cstr == "od_amp") c = new mod_amp();
else if(cstr == "ux2to1") c = new mux2to1();
else if(cstr == "ux4to1") c = new mux4to1();
else if(cstr == "ux8to1") c = new mux8to1();
break;
case 'l' : if(cstr == "og_amp") c = new log_amp();
else if(cstr == "ogic_0") c = new logic_0();
else if(cstr == "ogic_1") c = new logic_1();
break;
case 'p' : if(cstr == "otentiometer") c = new potentiometer();
else if(cstr == "hotodiode") c = new photodiode();
else if(cstr == "hototransistor") c = new phototransistor();
else if(cstr == "ad2bit") c = new pad2bit();
else if(cstr == "ad3bit") c = new pad3bit();
else if(cstr == "ad4bit") c = new pad4bit();
break;
case 'd' : if(cstr == "ff_SR") c = new dff_SR();
else if(cstr == "mux2to4") c = new dmux2to4();
else if(cstr == "mux3to8") c = new dmux3to8();
else if(cstr == "mux4to16") c = new dmux4to16();
break;
case 'j' : if(cstr == "kff_SR") c = new jkff_SR();
break;
case 't' : if(cstr == "ff_SR") c = new tff_SR();
break;
case 'g' : if(cstr == "atedDlatch") c = new gatedDlatch();
else if(cstr == "reytobinary4bit") c = new greytobinary4bit();
break;
case 'a' : if(cstr == "ndor4x2") c = new andor4x2();
else if(cstr == "ndor4x3") c = new andor4x3();
else if(cstr == "ndor4x4") c = new andor4x4();
break;
case 'f' : if(cstr == "a1b") c = new fa1b();
else if(cstr == "a2b") c = new fa2b();
break;
case 'b' : if(cstr == "inarytogrey4bit") c = new binarytogrey4bit();
break;
case 'c' : if(cstr == "omp_1bit") c = new comp_1bit();
else if(cstr == "omp_2bit") c = new comp_2bit();
else if(cstr == "omp_4bit") c = new comp_4bit();
break;
}
if(!c) {
QMessageBox::critical(0, QObject::tr("Error"),
QObject::tr("Format Error:\nUnknown component!"));

421
qucs/module.cpp Normal file
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@ -0,0 +1,421 @@
/***************************************************************************
module.cpp
------------
begin : Thu Nov 5 2009
copyright : (C) 2009 by Stefan Jahn
email : stefan@lkcc.org
***************************************************************************/
/***************************************************************************
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
***************************************************************************/
#include <qdict.h>
#include <qstring.h>
#include <qstringlist.h>
#include "element.h"
#include "components/component.h"
#include "components/components.h"
#include "paintings/paintings.h"
#include "diagrams/diagrams.h"
#include "module.h"
// Global category and component lists.
QDict<Module> Module::Modules;
QPtrList<Category> Category::Categories;
// Constructor creates instance of module object.
Module::Module () {
info = 0;
category = "#special";
}
// Destructor removes instance of module object from memory.
Module::~Module () {
}
// Module registration using a category name and the appropriate
// function returning a modules instance object.
void Module::registerModule (QString category, pInfoFunc info) {
Module * m = new Module ();
m->info = info;
m->category = category;
intoCategory (m);
}
// Component registration using a category name and the appropriate
// function returning a components instance object.
void Module::registerComponent (QString category, pInfoFunc info) {
Module * m = new Module ();
m->info = info;
m->category = category;
// instantiation of the component once in order to obtain "Model"
// property of the component
QString Name, Model;
char * File;
Component * c = (Component *) info (Name, File, true);
Model = c->Model;
delete c;
// put into category and the component hash
intoCategory (m);
if (!Modules.find (Model))
Modules.insert (Model, m);
}
// Returns instantiated component based on the given "Model" name. If
// there is no such component registers the function returns NULL.
Component * Module::getComponent (QString Model) {
Module * m = Modules.find (Model);
if (m) {
QString Name;
char * File;
return (Component *) m->info (Name, File, true);
}
return 0;
}
// The function appends the given module to the appropriate category.
// If there is no such category yet, then the category gets created.
void Module::intoCategory (Module * m) {
// look through existing categories
Category * cat = Category::Categories.first ();
for (; cat; cat = Category::Categories.next ()) {
if (cat->Name == m->category) {
cat->Content.append (m);
break;
}
}
// if there is no such category, then create it
if (!cat) {
cat = new Category (m->category);
Category::Categories.append (cat);
cat->Content.append (m);
}
}
// Helper macros for module registration.
#define REGISTER_MOD_1(cat,val) \
registerModule (cat, &val::info)
#define REGISTER_MOD_2(cat,val,inf1,inf2) \
registerModule (cat, &val::inf1); \
registerModule (cat, &val::inf2)
#define REGISTER_MOD_3(cat,val,inf1,inf2,inf3) \
registerModule (cat, &val::inf1); \
registerModule (cat, &val::inf2); \
registerModule (cat, &val::inf3)
#define REGISTER_COMP_1(cat,val) \
registerComponent (cat, &val::info)
#define REGISTER_COMP_2(cat,val,inf1,inf2) \
registerComponent (cat, &val::inf1); \
registerComponent (cat, &val::inf2)
#define REGISTER_COMP_3(cat,val,inf1,inf2,inf3) \
registerComponent (cat, &val::inf1); \
registerComponent (cat, &val::inf2); \
registerComponent (cat, &val::inf3)
#define REGISTER_LUMPED_1(val) \
REGISTER_COMP_1 (QObject::tr("lumped components"),val)
#define REGISTER_LUMPED_2(val,inf1,inf2) \
REGISTER_COMP_2 (QObject::tr("lumped components"),val,inf1,inf2)
#define REGISTER_SOURCE_1(val) \
REGISTER_COMP_1 (QObject::tr("sources"),val)
#define REGISTER_PROBE_1(val) \
REGISTER_COMP_1 (QObject::tr("probes"),val)
#define REGISTER_TRANS_1(val) \
REGISTER_COMP_1 (QObject::tr("transmission lines"),val)
#define REGISTER_NONLINEAR_1(val) \
REGISTER_COMP_1 (QObject::tr("nonlinear components"),val)
#define REGISTER_NONLINEAR_2(val,inf1,inf2) \
REGISTER_COMP_2 (QObject::tr("nonlinear components"),val,inf1,inf2)
#define REGISTER_NONLINEAR_3(val,inf1,inf2,inf3) \
REGISTER_COMP_3 (QObject::tr("nonlinear components"),val,inf1,inf2,inf3)
#define REGISTER_VERILOGA_1(val) \
REGISTER_COMP_1 (QObject::tr("verilog-a devices"),val)
#define REGISTER_VERILOGA_2(val,inf1,inf2) \
REGISTER_COMP_2 (QObject::tr("verilog-a devices"),val,inf1,inf2)
#define REGISTER_DIGITAL_1(val) \
REGISTER_COMP_1 (QObject::tr("digital components"),val)
#define REGISTER_FILE_1(val) \
REGISTER_COMP_1 (QObject::tr("file components"),val)
#define REGISTER_FILE_3(val,inf1,inf2,inf3) \
REGISTER_COMP_3 (QObject::tr("file components"),val,inf1,inf2,inf3)
#define REGISTER_SIMULATION_1(val) \
REGISTER_COMP_1 (QObject::tr("simulations"),val)
#define REGISTER_DIAGRAM_1(val) \
REGISTER_MOD_1 (QObject::tr("diagrams"),val)
#define REGISTER_DIAGRAM_2(val,inf1,inf2) \
REGISTER_MOD_2 (QObject::tr("diagrams"),val,inf1,inf2)
#define REGISTER_PAINT_1(val) \
REGISTER_MOD_1 (QObject::tr("paintings"),val)
#define REGISTER_PAINT_2(val,inf1,inf2) \
REGISTER_MOD_2 (QObject::tr("paintings"),val,inf1,inf2)
// This function has to be called once at application startup. It
// registers every component available in the application. Put here
// any new component.
void Module::registerModules (void) {
// lumped components
REGISTER_LUMPED_2 (Resistor, info, info_us);
REGISTER_LUMPED_1 (Capacitor);
REGISTER_LUMPED_1 (Inductor);
REGISTER_LUMPED_1 (Ground);
REGISTER_LUMPED_1 (SubCirPort);
REGISTER_LUMPED_1 (Transformer);
REGISTER_LUMPED_1 (symTrafo);
REGISTER_LUMPED_1 (dcBlock);
REGISTER_LUMPED_1 (dcFeed);
REGISTER_LUMPED_1 (BiasT);
REGISTER_LUMPED_1 (Attenuator);
REGISTER_LUMPED_1 (Amplifier);
REGISTER_LUMPED_1 (Isolator);
REGISTER_LUMPED_1 (Circulator);
REGISTER_LUMPED_1 (Gyrator);
REGISTER_LUMPED_1 (Phaseshifter);
REGISTER_LUMPED_1 (Coupler);
REGISTER_LUMPED_1 (iProbe);
REGISTER_LUMPED_1 (vProbe);
REGISTER_LUMPED_1 (Mutual);
REGISTER_LUMPED_1 (Mutual2);
REGISTER_LUMPED_1 (Switch);
REGISTER_LUMPED_1 (Relais);
REGISTER_LUMPED_1 (RFedd);
REGISTER_LUMPED_1 (RFedd2P);
// sources
REGISTER_SOURCE_1 (Volt_dc);
REGISTER_SOURCE_1 (Ampere_dc);
REGISTER_SOURCE_1 (Volt_ac);
REGISTER_SOURCE_1 (Ampere_ac);
REGISTER_SOURCE_1 (Source_ac);
REGISTER_SOURCE_1 (Volt_noise);
REGISTER_SOURCE_1 (Ampere_noise);
REGISTER_SOURCE_1 (VCCS);
REGISTER_SOURCE_1 (CCCS);
REGISTER_SOURCE_1 (VCVS);
REGISTER_SOURCE_1 (CCVS);
REGISTER_SOURCE_1 (vPulse);
REGISTER_SOURCE_1 (iPulse);
REGISTER_SOURCE_1 (vRect);
REGISTER_SOURCE_1 (iRect);
REGISTER_SOURCE_1 (Noise_ii);
REGISTER_SOURCE_1 (Noise_vv);
REGISTER_SOURCE_1 (Noise_iv);
REGISTER_SOURCE_1 (AM_Modulator);
REGISTER_SOURCE_1 (PM_Modulator);
REGISTER_SOURCE_1 (iExp);
REGISTER_SOURCE_1 (vExp);
REGISTER_SOURCE_1 (vFile);
REGISTER_SOURCE_1 (iFile);
// probes
REGISTER_PROBE_1 (iProbe);
REGISTER_PROBE_1 (vProbe);
// transmission lines
REGISTER_TRANS_1 (TLine);
REGISTER_TRANS_1 (TLine_4Port);
REGISTER_TRANS_1 (TwistedPair);
REGISTER_TRANS_1 (CoaxialLine);
REGISTER_TRANS_1 (RectLine);
REGISTER_TRANS_1 (RLCG);
REGISTER_TRANS_1 (Substrate);
REGISTER_TRANS_1 (MSline);
REGISTER_TRANS_1 (MScoupled);
REGISTER_TRANS_1 (MScorner);
REGISTER_TRANS_1 (MSmbend);
REGISTER_TRANS_1 (MSstep);
REGISTER_TRANS_1 (MStee);
REGISTER_TRANS_1 (MScross);
REGISTER_TRANS_1 (MSopen);
REGISTER_TRANS_1 (MSgap);
REGISTER_TRANS_1 (MSvia);
REGISTER_TRANS_1 (MSrstub);
REGISTER_TRANS_1 (Coplanar);
REGISTER_TRANS_1 (CPWopen);
REGISTER_TRANS_1 (CPWshort);
REGISTER_TRANS_1 (CPWgap);
REGISTER_TRANS_1 (CPWstep);
REGISTER_TRANS_1 (BondWire);
// nonlinear components
REGISTER_NONLINEAR_1 (Diode);
REGISTER_NONLINEAR_2 (BJT, info, info_pnp);
REGISTER_NONLINEAR_2 (BJTsub, info, info_pnp);
REGISTER_NONLINEAR_2 (JFET, info, info_p);
REGISTER_NONLINEAR_3 (MOSFET, info, info_p, info_depl);
REGISTER_NONLINEAR_3 (MOSFET_sub, info, info_p, info_depl);
REGISTER_NONLINEAR_1 (OpAmp);
REGISTER_NONLINEAR_1 (EqnDefined);
REGISTER_NONLINEAR_1 (Diac);
REGISTER_NONLINEAR_1 (Triac);
REGISTER_NONLINEAR_1 (Thyristor);
// verilog-a devices
REGISTER_VERILOGA_1 (hicumL2V2p1);
REGISTER_VERILOGA_1 (HBT_X);
REGISTER_VERILOGA_1 (mod_amp);
REGISTER_VERILOGA_1 (hic2_full);
REGISTER_VERILOGA_1 (log_amp);
REGISTER_VERILOGA_2 (hic0_full, info, info_pnp);
REGISTER_VERILOGA_1 (potentiometer);
REGISTER_VERILOGA_1 (MESFET);
REGISTER_VERILOGA_2 (EKV26MOS, info, info_pmos);
REGISTER_VERILOGA_2 (hicumL0V1p2, info, info_pnp);
REGISTER_VERILOGA_1 (hicumL2V2p23);
REGISTER_VERILOGA_1 (photodiode);
REGISTER_VERILOGA_1 (phototransistor);
REGISTER_VERILOGA_1 (nigbt);
// digital components
REGISTER_DIGITAL_1 (Digi_Source);
REGISTER_DIGITAL_1 (Logical_Inv);
REGISTER_DIGITAL_1 (Logical_OR);
REGISTER_DIGITAL_1 (Logical_NOR);
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_NAND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
REGISTER_DIGITAL_1 (Logical_Buf);
REGISTER_DIGITAL_1 (andor4x2);
REGISTER_DIGITAL_1 (andor4x3);
REGISTER_DIGITAL_1 (andor4x4);
REGISTER_DIGITAL_1 (mux2to1);
REGISTER_DIGITAL_1 (mux4to1);
REGISTER_DIGITAL_1 (mux8to1);
REGISTER_DIGITAL_1 (dmux2to4);
REGISTER_DIGITAL_1 (dmux3to8);
REGISTER_DIGITAL_1 (dmux4to16);
REGISTER_DIGITAL_1 (ha1b);
REGISTER_DIGITAL_1 (fa1b);
REGISTER_DIGITAL_1 (fa2b);
REGISTER_DIGITAL_1 (RS_FlipFlop);
REGISTER_DIGITAL_1 (D_FlipFlop);
REGISTER_DIGITAL_1 (dff_SR);
REGISTER_DIGITAL_1 (JK_FlipFlop);
REGISTER_DIGITAL_1 (jkff_SR);
REGISTER_DIGITAL_1 (tff_SR);
REGISTER_DIGITAL_1 (gatedDlatch);
REGISTER_DIGITAL_1 (logic_0);
REGISTER_DIGITAL_1 (logic_1);
REGISTER_DIGITAL_1 (pad2bit);
REGISTER_DIGITAL_1 (pad3bit);
REGISTER_DIGITAL_1 (pad4bit);
REGISTER_DIGITAL_1 (DLS_nto1);
REGISTER_DIGITAL_1 (DLS_1ton);
REGISTER_DIGITAL_1 (binarytogrey4bit);
REGISTER_DIGITAL_1 (greytobinary4bit);
REGISTER_DIGITAL_1 (comp_1bit);
REGISTER_DIGITAL_1 (comp_2bit);
REGISTER_DIGITAL_1 (comp_4bit);
REGISTER_DIGITAL_1 (hpribin4bit);
REGISTER_DIGITAL_1 (VHDL_File);
REGISTER_DIGITAL_1 (Verilog_File);
REGISTER_DIGITAL_1 (Digi_Sim);
// file components
REGISTER_FILE_1 (SpiceFile);
REGISTER_FILE_3 (SParamFile, info1, info2, info);
REGISTER_FILE_1 (Subcircuit);
// simulations
REGISTER_SIMULATION_1 (DC_Sim);
REGISTER_SIMULATION_1 (TR_Sim);
REGISTER_SIMULATION_1 (AC_Sim);
REGISTER_SIMULATION_1 (SP_Sim);
REGISTER_SIMULATION_1 (HB_Sim);
REGISTER_SIMULATION_1 (Param_Sweep);
REGISTER_SIMULATION_1 (Digi_Sim);
REGISTER_SIMULATION_1 (Optimize_Sim);
// diagrams
REGISTER_DIAGRAM_1 (RectDiagram);
REGISTER_DIAGRAM_1 (PolarDiagram);
REGISTER_DIAGRAM_1 (TabDiagram);
REGISTER_DIAGRAM_2 (SmithDiagram, info, info_y);
REGISTER_DIAGRAM_2 (PSDiagram, info, info_sp);
REGISTER_DIAGRAM_1 (Rect3DDiagram);
REGISTER_DIAGRAM_1 (CurveDiagram);
REGISTER_DIAGRAM_1 (TimingDiagram);
REGISTER_DIAGRAM_1 (TruthDiagram);
// paintings
REGISTER_PAINT_1 (GraphicLine);
REGISTER_PAINT_1 (Arrow);
REGISTER_PAINT_1 (GraphicText);
REGISTER_PAINT_2 (Ellipse, info, info_filled);
REGISTER_PAINT_2 (Rectangle, info, info_filled);
REGISTER_PAINT_1 (EllipseArc);
}
// This function has to be called once at application end. It removes
// all categories and registered modules from memory.
void Module::unregisterModules (void) {
Category::Categories.setAutoDelete (true);
Category::Categories.clear ();
Modules.clear ();
}
// Constructor creates instance of module object.
Category::Category () {
Name = "#special";
Content.clear ();
}
// Constructor creates named instance of module object.
Category::Category (const QString name) {
Name = name;
Content.clear ();
}
// Destructor removes instance of module object from memory.
Category::~Category () {
Content.setAutoDelete (true);
Content.clear ();
}
// Returns the available category names in a list of strings.
QStringList Category::getCategories (void) {
QStringList res;
Category * cat = Categories.first ();
for (; cat; cat = Categories.next ()) {
res.append (cat->Name);
}
return res;
}
// The function returns the registered modules in the given category
// as a pointer list. The pointer list is empty if there is no such
// category available.
QPtrList<Module> Category::getModules (QString category) {
QPtrList<Module> res;
Category * cat = Categories.first ();
for (; cat; cat = Categories.next ()) {
if (category == cat->Name)
res = cat->Content;
}
return res;
}
// Returns the index number into the category list for the given
// category name. The function returns zero if there is no such
// category.
int Category::getModulesNr (QString category) {
Category * cat = Categories.first ();
for (int i = 0; cat; cat = Categories.next (), i++) {
if (category == cat->Name)
return i;
}
return 0;
}

67
qucs/module.h Normal file
View File

@ -0,0 +1,67 @@
/***************************************************************************
module.h
----------
begin : Thu Nov 5 2009
copyright : (C) 2009 by Stefan Jahn
email : stefan@lkcc.org
***************************************************************************/
/***************************************************************************
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
***************************************************************************/
#ifndef MODULE_H
#define MODULE_H
// function typedefs for circuits and analyses
typedef Element * (* pInfoFunc) (QString&, char * &, bool);
typedef Component * (* pCreatorFunc) ();
class Module
{
public:
Module ();
~Module ();
static void registerModule (QString, pInfoFunc);
static void registerComponent (QString, pInfoFunc);
static void intoCategory (Module *);
static Component * getComponent (QString);
public:
static QDict<Module> Modules;
public:
static void registerModules (void);
static void unregisterModules (void);
public:
pInfoFunc info;
QString category;
};
class Category
{
public:
Category ();
Category (const QString);
~Category ();
public:
static QPtrList<Category> Categories;
public:
static QStringList getCategories (void);
static QPtrList<Module> getModules (QString);
static int getModulesNr (QString);
public:
QString Name;
QPtrList<Module> Content;
};
#endif /* __MODULE_H__ */

View File

@ -27,7 +27,7 @@ NAME = qucs
SOURCES = node.cpp element.cpp qucsdoc.cpp wire.cpp mouseactions.cpp \
qucs.cpp main.cpp wirelabel.cpp qucs_init.cpp qucs_actions.cpp \
viewpainter.cpp mnemo.cpp schematic.cpp schematic_element.cpp textdoc.cpp \
schematic_file.cpp syntax.cpp
schematic_file.cpp syntax.cpp module.cpp
# List of special Qt files.
MOCHEADERS = qucs.h schematic.h textdoc.h

View File

@ -66,6 +66,7 @@
#include "schematic.h"
#include "mouseactions.h"
#include "wire.h"
#include "module.h"
#include "components/components.h"
#include "paintings/paintings.h"
#include "diagrams/diagrams.h"
@ -145,6 +146,7 @@ QucsApp::QucsApp()
viewBrowseDock->setOn(true);
initCursorMenu();
HierarchyHistory.setAutoDelete(true);
Module::registerModules ();
// default settings of the printer
Printer = new QPrinter(QPrinter::HighResolution);
@ -178,6 +180,7 @@ QucsApp::QucsApp()
QucsApp::~QucsApp()
{
Module::unregisterModules ();
delete Printer;
}
@ -325,144 +328,48 @@ QucsDoc * QucsApp::findDoc (QString File, int * Pos)
return 0;
}
// ####################################################################
// ##### The following arrays contains the elements that appear #####
// ##### in the component listview. #####
// ####################################################################
typedef Element* (*pInfoFunc) (QString&, char* &, bool);
pInfoFunc lumpedComponents[] =
{&Resistor::info, &Resistor::info_us, &Capacitor::info, &Inductor::info,
&Ground::info, &SubCirPort::info, &Transformer::info, &symTrafo::info,
&dcBlock::info, &dcFeed::info, &BiasT::info, &Attenuator::info,
&Amplifier::info, &Isolator::info, &Circulator::info,
&Gyrator::info, &Phaseshifter::info, &Coupler::info, &iProbe::info,
&vProbe::info, &Mutual::info, &Mutual2::info, &Switch::info,
&Relais::info, &RFedd::info, &RFedd2P::info, 0};
pInfoFunc Sources[] =
{&Volt_dc::info, &Ampere_dc::info, &Volt_ac::info, &Ampere_ac::info,
&Source_ac::info, &Volt_noise::info, &Ampere_noise::info, &VCCS::info,
&CCCS::info, &VCVS::info, &CCVS::info, &vPulse::info, &iPulse::info,
&vRect::info, &iRect::info, &Noise_ii::info, &Noise_vv::info,
&Noise_iv::info, &AM_Modulator::info, &PM_Modulator::info, &iExp::info,
&vExp::info, &vFile::info, &iFile::info, 0};
pInfoFunc Probes[] =
{&iProbe::info, &vProbe::info, 0};
pInfoFunc TransmissionLines[] =
{&TLine::info, &TLine_4Port::info, &TwistedPair::info, &CoaxialLine::info,
&RectLine::info, &RLCG::info,
&Substrate::info, &MSline::info, &MScoupled::info, &MScorner::info,
&MSmbend::info, &MSstep::info, &MStee::info, &MScross::info, &MSopen::info,
&MSgap::info, &MSvia::info, &MSrstub::info, &Coplanar::info, &CPWopen::info,
&CPWshort::info, &CPWgap::info, &CPWstep::info, &BondWire::info, 0};
pInfoFunc nonlinearComps[] =
{&Diode::info, &BJT::info, &BJT::info_pnp, &BJTsub::info,
&BJTsub::info_pnp, &JFET::info, &JFET::info_p,
&MOSFET::info, &MOSFET::info_p, &MOSFET::info_depl,
&MOSFET_sub::info, &MOSFET_sub::info_p, &MOSFET_sub::info_depl,
&OpAmp::info, &EqnDefined::info, &Diac::info, &Triac::info,
&Thyristor::info,
0};
pInfoFunc VerilogAComps[] =
{&hicumL2V2p1::info, &HBT_X::info, &mod_amp::info, &hic2_full::info,
&log_amp::info, &hic0_full::info, &hic0_full::info_pnp,
&potentiometer::info, &MESFET::info, &EKV26MOS::info, &EKV26MOS::info_pmos,
&hicumL0V1p2::info, &hicumL0V1p2::info_pnp, &hicumL2V2p23::info,
&photodiode::info, &phototransistor::info, &nigbt::info, 0};
pInfoFunc digitalComps[] =
{&Digi_Source::info, &Logical_Inv::info, &Logical_OR::info,
&Logical_NOR::info, &Logical_AND::info, &Logical_NAND::info,
&Logical_XOR::info, &Logical_XNOR::info, &Logical_Buf::info,
&andor4x2::info, &andor4x3::info, &andor4x4::info,
&mux2to1::info, &mux4to1::info, &mux8to1::info,
&dmux2to4::info, &dmux3to8::info, &dmux4to16::info,
&ha1b::info, &fa1b::info, &fa2b::info,
&RS_FlipFlop::info, &D_FlipFlop::info, &dff_SR::info,
&JK_FlipFlop::info, &jkff_SR::info, &tff_SR::info,
&gatedDlatch::info,
&logic_0::info, &logic_1::info,
&pad2bit::info, &pad3bit::info, &pad4bit::info,
&DLS_nto1::info, &DLS_1ton::info,
&binarytogrey4bit::info, &greytobinary4bit::info,
&comp_1bit::info, &comp_2bit::info, &comp_4bit::info,
&hpribin4bit::info,
&VHDL_File::info, &Verilog_File::info,
&Digi_Sim::info, 0};
pInfoFunc Simulations[] =
{&DC_Sim::info, &TR_Sim::info, &AC_Sim::info, &SP_Sim::info,
&HB_Sim::info, &Param_Sweep::info, &Digi_Sim::info, &Optimize_Sim::info,
0};
pInfoFunc FileComponents[] =
{&SpiceFile::info, &SParamFile::info1, &SParamFile::info2,
&SParamFile::info, &Subcircuit::info, 0};
pInfoFunc Diagrams[] =
{&RectDiagram::info, &PolarDiagram::info, &TabDiagram::info,
&SmithDiagram::info, &SmithDiagram::info_y, &PSDiagram::info,
&PSDiagram::info_sp, &Rect3DDiagram::info, &CurveDiagram::info,
&TimingDiagram::info, &TruthDiagram::info, 0};
pInfoFunc Paintings[] =
{&GraphicLine::info, &Arrow::info, &GraphicText::info,
&Ellipse::info, &Rectangle::info, &Ellipse::info_filled,
&Rectangle::info_filled, &EllipseArc::info, 0};
// Order of the component groups in the ComboBox
pInfoFunc *ComponentGroups[] =
{lumpedComponents, Sources, Probes, TransmissionLines, nonlinearComps,
VerilogAComps, digitalComps, FileComponents, Simulations, Diagrams, 0};
// ---------------------------------------------------------------
// Put the component groups into the ComboBox. It is possible to
// only put the paintings in it, because of "symbol painting mode".
void QucsApp::fillComboBox(bool setAll)
void QucsApp::fillComboBox (bool setAll)
{
CompChoose->setSizeLimit(11); //Increase this if you add items below.
CompChoose->clear();
if(setAll) {
CompChoose->insertItem(tr("lumped components"));
CompChoose->insertItem(tr("sources"));
CompChoose->insertItem(tr("probes"));
CompChoose->insertItem(tr("transmission lines"));
CompChoose->insertItem(tr("nonlinear components"));
CompChoose->insertItem(tr("verilog-a devices"));
CompChoose->insertItem(tr("digital components"));
CompChoose->insertItem(tr("file components"));
CompChoose->insertItem(tr("simulations"));
CompChoose->insertItem(tr("diagrams"));
CompChoose->setSizeLimit (11); // Increase this if you add items below.
CompChoose->clear ();
QStringList cats = Category::getCategories ();
for (QStringList::Iterator it = cats.begin (); it != cats.end (); ++it) {
if (*it != QObject::tr("paintings")) {
if (setAll) CompChoose->insertItem (*it);
}
else CompChoose->insertItem (*it);
}
CompChoose->insertItem(tr("paintings"));
}
// ----------------------------------------------------------
// Whenever the Component Library ComboBox is changed, this slot fills the
// Component IconView with the appropriat components.
void QucsApp::slotSetCompView(int index)
void QucsApp::slotSetCompView (int index)
{
editText->setHidden(true); // disable text edit of component property
editText->setHidden (true); // disable text edit of component property
char *File;
QString Name;
pInfoFunc *Infos = 0;
CompComps->clear(); // clear the IconView
if((index+1) >= CompChoose->count()) // because of symbol edit mode
Infos = &Paintings[0];
QPtrList<Module> Comps;
CompComps->clear (); // clear the IconView
if (CompChoose->count () <= 0) return;
QString item = CompChoose->text (index);
if ((index + 1) >= CompChoose->count ()) // because of symbol edit mode
Comps = Category::getModules (QObject::tr("paintings"));
else
Infos = ComponentGroups[index];
Comps = Category::getModules (item);
while(*Infos != 0) {
(**Infos) (Name, File, false);
new QIconViewItem(CompComps, Name,
QImage(QucsSettings.BitmapDir+QString(File)+".png"));
Infos++;
char * File;
QString Name;
Module * Mod;
for (Mod = Comps.first(); Mod; Mod = Comps.next ()) {
if (Mod->info) {
*(Mod->info) (Name, File, false);
new QIconViewItem (CompComps, Name,
QImage (QucsSettings.BitmapDir + QString (File) + ".png"));
}
}
}
@ -493,22 +400,24 @@ void QucsApp::slotSelectComponent(QIconViewItem *item)
}
activeAction = 0;
MouseMoveAction = &MouseActions::MMoveElement;
MousePressAction = &MouseActions::MPressElement;
MouseReleaseAction = 0;
MouseDoubleClickAction = 0;
pInfoFunc Infos = 0;
int i = CompComps->index(item);
int i = CompComps->index (item);
QPtrList<Module> Comps;
if((CompChoose->currentItem()+1) >= CompChoose->count())
Infos = Paintings[i]; // the only one in "symbol-painting" mode
// the only one in "symbol-painting" mode
Comps = Category::getModules (QObject::tr("paintings"));
else
Infos = *(ComponentGroups[CompChoose->currentItem()] + i);
Comps = Category::getModules (CompChoose->currentText ());
Infos = Comps.at(i)->info;
char *Dummy2;
char * Dummy2;
QString Dummy1;
if(Infos)
if (Infos)
view->selElem = (*Infos) (Dummy1, Dummy2, true);
}
@ -1871,11 +1780,11 @@ void QucsApp::slotChangePage(QString& DocName, QString& DataDisplay)
if(!isTextDocument (w))
((Schematic*)w)->reloadGraphs(); // ... changes, reload here !
TabView->setCurrentPage(2); // switch to "Component"-Tab
if(Name.right(4) == ".dpl") {
int i = sizeof(ComponentGroups)/sizeof(pInfoFunc) - 2;
CompChoose->setCurrentItem(i); // switch to diagrams
slotSetCompView(i);
TabView->setCurrentPage (2); // switch to "Component"-Tab
if (Name.right(4) == ".dpl") {
int i = Category::getModulesNr (QObject::tr("diagrams"));
CompChoose->setCurrentItem (i); // switch to diagrams
slotSetCompView (i);
}
}

View File

@ -6864,6 +6864,50 @@ qucsedit [-r] file :إستعمال
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">صنف العناصر</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">المصادر</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">تحقيقات</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">انتقال الخط</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">العناصر غير الخطية</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">أجهزة فيريلوج</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">عناصر الرقمية</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">عناصر الملفات</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">المحاكاة </translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">رسوم بيانية</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">لوحات</translation>
</message>
</context>
<context>
<name>QucsApp</name>
@ -7075,47 +7119,47 @@ Overwrite ?</source>
</message>
<message>
<source>lumped components</source>
<translation>صنف العناصر</translation>
<translation type="obsolete">صنف العناصر</translation>
</message>
<message>
<source>sources</source>
<translation>المصادر</translation>
<translation type="obsolete">المصادر</translation>
</message>
<message>
<source>probes</source>
<translation>تحقيقات</translation>
<translation type="obsolete">تحقيقات</translation>
</message>
<message>
<source>transmission lines</source>
<translation>انتقال الخط</translation>
<translation type="obsolete">انتقال الخط</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>العناصر غير الخطية</translation>
<translation type="obsolete">العناصر غير الخطية</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>أجهزة فيريلوج</translation>
<translation type="obsolete">أجهزة فيريلوج</translation>
</message>
<message>
<source>digital components</source>
<translation>عناصر الرقمية</translation>
<translation type="obsolete">عناصر الرقمية</translation>
</message>
<message>
<source>file components</source>
<translation>عناصر الملفات</translation>
<translation type="obsolete">عناصر الملفات</translation>
</message>
<message>
<source>simulations</source>
<translation>المحاكاة </translation>
<translation type="obsolete">المحاكاة </translation>
</message>
<message>
<source>diagrams</source>
<translation>رسوم بيانية</translation>
<translation type="obsolete">رسوم بيانية</translation>
</message>
<message>
<source>paintings</source>
<translation>لوحات</translation>
<translation type="obsolete">لوحات</translation>
</message>
<message>
<source>Rename</source>

View File

@ -7108,6 +7108,50 @@ Use: qucsedit [-r] fitxer
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">componentes sueltos</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">fuentes</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">línees de transmisión</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">componentes no líneales</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">componentes digitales</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">componentes del fitxer</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simulaciones</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">diagramas</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">pinturas</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7220,19 +7264,19 @@ Use: qucsedit [-r] fitxer
</message>
<message>
<source>lumped components</source>
<translation>componentes sueltos</translation>
<translation type="obsolete">componentes sueltos</translation>
</message>
<message>
<source>sources</source>
<translation>fuentes</translation>
<translation type="obsolete">fuentes</translation>
</message>
<message>
<source>transmission lines</source>
<translation>línees de transmisión</translation>
<translation type="obsolete">línees de transmisión</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>componentes no líneales</translation>
<translation type="obsolete">componentes no líneales</translation>
</message>
<message>
<source>file data</source>
@ -7240,15 +7284,15 @@ Use: qucsedit [-r] fitxer
</message>
<message>
<source>simulations</source>
<translation>simulaciones</translation>
<translation type="obsolete">simulaciones</translation>
</message>
<message>
<source>diagrams</source>
<translation>diagramas</translation>
<translation type="obsolete">diagramas</translation>
</message>
<message>
<source>paintings</source>
<translation>pinturas</translation>
<translation type="obsolete">pinturas</translation>
</message>
<message>
<source>Rename</source>
@ -7743,11 +7787,11 @@ Edita el esquema</translation>
</message>
<message>
<source>file components</source>
<translation>componentes del fitxer</translation>
<translation type="obsolete">componentes del fitxer</translation>
</message>
<message>
<source>digital components</source>
<translation>componentes digitales</translation>
<translation type="obsolete">componentes digitales</translation>
</message>
<message>
<source>Others</source>
@ -9591,14 +9635,6 @@ Center vertically selected elements</source>
<source>Verilog</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>
<translation type="unfinished"></translation>

View File

@ -7330,6 +7330,50 @@ Použití: qucsedit [-r] soubor
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">diskrétní komponenty</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">zdroje</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">sondy</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">nelineární komponenty</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">verilog-a zařízení</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">digitální komponenty</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7868,7 +7912,7 @@ Zkopíruje vybranou oblast do schránky</translation>
</message>
<message>
<source>digital components</source>
<translation>digitální komponenty</translation>
<translation type="obsolete">digitální komponenty</translation>
</message>
<message>
<source>Schematic</source>
@ -7940,35 +7984,35 @@ Zkopíruje vybranou oblast do schránky</translation>
</message>
<message>
<source>lumped components</source>
<translation>diskrétní komponenty</translation>
<translation type="obsolete">diskrétní komponenty</translation>
</message>
<message>
<source>sources</source>
<translation>zdroje</translation>
<translation type="obsolete">zdroje</translation>
</message>
<message>
<source>transmission lines</source>
<translation>přenosová vedení</translation>
<translation type="obsolete">přenosová vedení</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>nelineární komponenty</translation>
<translation type="obsolete">nelineární komponenty</translation>
</message>
<message>
<source>file components</source>
<translation>datové komponenty</translation>
<translation type="obsolete">datové komponenty</translation>
</message>
<message>
<source>simulations</source>
<translation>simulace</translation>
<translation type="obsolete">simulace</translation>
</message>
<message>
<source>diagrams</source>
<translation>diagramy</translation>
<translation type="obsolete">diagramy</translation>
</message>
<message>
<source>paintings</source>
<translation>grafika</translation>
<translation type="obsolete">grafika</translation>
</message>
<message>
<source>Rename</source>
@ -9996,11 +10040,11 @@ Vyrovnat svisle vybrané prvky</translation>
</message>
<message>
<source>probes</source>
<translation>sondy</translation>
<translation type="obsolete">sondy</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>verilog-a zařízení</translation>
<translation type="obsolete">verilog-a zařízení</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -7386,6 +7386,50 @@ Verwendung: qucsedit [-r] Datei
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">diskrete Komponenten</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">Quellen</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">Messgeräte</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">Übertragungsstrecken</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">nichtlineare Komponenten</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">Verilog-A Komponenten</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">digitale Komponenten</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">Dateikomponenten</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">Simulationen</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">Diagramme</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">Zeichnungen</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7924,7 +7968,7 @@ Kopiert den ausgewählten Bereich in die Zwischenablage</translation>
</message>
<message>
<source>digital components</source>
<translation>digitale Komponenten</translation>
<translation type="obsolete">digitale Komponenten</translation>
</message>
<message>
<source>Schematic</source>
@ -7996,35 +8040,35 @@ Kopiert den ausgewählten Bereich in die Zwischenablage</translation>
</message>
<message>
<source>lumped components</source>
<translation>diskrete Komponenten</translation>
<translation type="obsolete">diskrete Komponenten</translation>
</message>
<message>
<source>sources</source>
<translation>Quellen</translation>
<translation type="obsolete">Quellen</translation>
</message>
<message>
<source>transmission lines</source>
<translation>Übertragungsstrecken</translation>
<translation type="obsolete">Übertragungsstrecken</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>nichtlineare Komponenten</translation>
<translation type="obsolete">nichtlineare Komponenten</translation>
</message>
<message>
<source>file components</source>
<translation>Dateikomponenten</translation>
<translation type="obsolete">Dateikomponenten</translation>
</message>
<message>
<source>simulations</source>
<translation>Simulationen</translation>
<translation type="obsolete">Simulationen</translation>
</message>
<message>
<source>diagrams</source>
<translation>Diagramme</translation>
<translation type="obsolete">Diagramme</translation>
</message>
<message>
<source>paintings</source>
<translation>Zeichnungen</translation>
<translation type="obsolete">Zeichnungen</translation>
</message>
<message>
<source>Rename</source>
@ -10056,11 +10100,11 @@ Zentriert ausgewählte Elemente vertikal</translation>
</message>
<message>
<source>probes</source>
<translation>Messgeräte</translation>
<translation type="obsolete">Messgeräte</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>Verilog-A Komponenten</translation>
<translation type="obsolete">Verilog-A Komponenten</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -7132,6 +7132,50 @@ Use: qucsedit [-r] archivo
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">componentes sueltos</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">fuentes</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">sondas</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">líneas de transmisión</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">componentes no líneales</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">Componentes verilog</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">componentes digitales</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">componentes del archivo</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simulaciones</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">diagramas</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">pinturas</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7244,19 +7288,19 @@ Use: qucsedit [-r] archivo
</message>
<message>
<source>lumped components</source>
<translation>componentes sueltos</translation>
<translation type="obsolete">componentes sueltos</translation>
</message>
<message>
<source>sources</source>
<translation>fuentes</translation>
<translation type="obsolete">fuentes</translation>
</message>
<message>
<source>transmission lines</source>
<translation>líneas de transmisión</translation>
<translation type="obsolete">líneas de transmisión</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>componentes no líneales</translation>
<translation type="obsolete">componentes no líneales</translation>
</message>
<message>
<source>file data</source>
@ -7264,15 +7308,15 @@ Use: qucsedit [-r] archivo
</message>
<message>
<source>simulations</source>
<translation>simulaciones</translation>
<translation type="obsolete">simulaciones</translation>
</message>
<message>
<source>diagrams</source>
<translation>diagramas</translation>
<translation type="obsolete">diagramas</translation>
</message>
<message>
<source>paintings</source>
<translation>pinturas</translation>
<translation type="obsolete">pinturas</translation>
</message>
<message>
<source>Rename</source>
@ -7767,11 +7811,11 @@ Edita el esquema</translation>
</message>
<message>
<source>file components</source>
<translation>componentes del archivo</translation>
<translation type="obsolete">componentes del archivo</translation>
</message>
<message>
<source>digital components</source>
<translation>componentes digitales</translation>
<translation type="obsolete">componentes digitales</translation>
</message>
<message>
<source>Others</source>
@ -9625,11 +9669,11 @@ Centra verticalmente los elementos seleccionados</translation>
</message>
<message>
<source>probes</source>
<translation>sondas</translation>
<translation type="obsolete">sondas</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>Componentes verilog</translation>
<translation type="obsolete">Componentes verilog</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -7136,6 +7136,50 @@ Invocation : qucsedit [-r] fichier
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">composants discrets</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">sources</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">sondes</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">composants distribués</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">composants non-linéaires</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">Macrocomposants numériques</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">Fichier de composants</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simulations</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">graphiques</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">décor</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7282,19 +7326,19 @@ Le remplacer ?</translation>
</message>
<message>
<source>lumped components</source>
<translation>composants discrets</translation>
<translation type="obsolete">composants discrets</translation>
</message>
<message>
<source>sources</source>
<translation>sources</translation>
<translation type="obsolete">sources</translation>
</message>
<message>
<source>transmission lines</source>
<translation>composants distribués</translation>
<translation type="obsolete">composants distribués</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>composants non-linéaires</translation>
<translation type="obsolete">composants non-linéaires</translation>
</message>
<message>
<source>file data</source>
@ -7302,15 +7346,15 @@ Le remplacer ?</translation>
</message>
<message>
<source>simulations</source>
<translation>simulations</translation>
<translation type="obsolete">simulations</translation>
</message>
<message>
<source>paintings</source>
<translation>décor</translation>
<translation type="obsolete">décor</translation>
</message>
<message>
<source>diagrams</source>
<translation>graphiques</translation>
<translation type="obsolete">graphiques</translation>
</message>
<message>
<source>Warning</source>
@ -7809,11 +7853,11 @@ Modifie ce schéma</translation>
</message>
<message>
<source>file components</source>
<translation>Fichier de composants</translation>
<translation type="obsolete">Fichier de composants</translation>
</message>
<message>
<source>digital components</source>
<translation>Macrocomposants numériques</translation>
<translation type="obsolete">Macrocomposants numériques</translation>
</message>
<message>
<source>Others</source>
@ -9689,11 +9733,7 @@ Centre verticalement les éléments sélectionnés</translation>
</message>
<message>
<source>probes</source>
<translation>sondes</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
<translation type="obsolete">sondes</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -6963,6 +6963,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">רכיבים מאוחדים</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">מקורות</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">קוי תמסורת</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">רכיבים לא לינאריים</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">סימולציות</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">דיאגרמות</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">ציורים</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7071,19 +7115,19 @@ Usage: qucsedit [-r] file
</message>
<message>
<source>lumped components</source>
<translation>רכיבים מאוחדים</translation>
<translation type="obsolete">רכיבים מאוחדים</translation>
</message>
<message>
<source>sources</source>
<translation>מקורות</translation>
<translation type="obsolete">מקורות</translation>
</message>
<message>
<source>transmission lines</source>
<translation>קוי תמסורת</translation>
<translation type="obsolete">קוי תמסורת</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>רכיבים לא לינאריים</translation>
<translation type="obsolete">רכיבים לא לינאריים</translation>
</message>
<message>
<source>file data</source>
@ -7091,15 +7135,15 @@ Usage: qucsedit [-r] file
</message>
<message>
<source>simulations</source>
<translation>סימולציות</translation>
<translation type="obsolete">סימולציות</translation>
</message>
<message>
<source>diagrams</source>
<translation>דיאגרמות</translation>
<translation type="obsolete">דיאגרמות</translation>
</message>
<message>
<source>paintings</source>
<translation>ציורים</translation>
<translation type="obsolete">ציורים</translation>
</message>
<message>
<source>Rename</source>
@ -7567,14 +7611,6 @@ Edits the symbol for this schematic</source>
Edits the schematic</source>
<translation type="obsolete">ערוך סכימה עורך את הסכימה</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Others</source>
<translation type="unfinished"></translation>
@ -9320,14 +9356,6 @@ Center vertically selected elements</source>
<source>Verilog</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>
<translation type="unfinished"></translation>

View File

@ -7106,6 +7106,50 @@ Digitális szimuláció</translation>
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">Álltalános alkatrészek</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">Áram és feszültségforrások</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">próbák</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">Tápvonalak</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">Nemlineáris, aktív alkatrészek</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">digitális alkatrészek</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">fájl alkatrészek</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">Szimulációk</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">Diagramok</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">Feliratok, rajzelemek</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7267,19 +7311,19 @@ Felülírjam?</translation>
</message>
<message>
<source>lumped components</source>
<translation>Álltalános alkatrészek</translation>
<translation type="obsolete">Álltalános alkatrészek</translation>
</message>
<message>
<source>sources</source>
<translation>Áram és feszültségforrások</translation>
<translation type="obsolete">Áram és feszültségforrások</translation>
</message>
<message>
<source>transmission lines</source>
<translation>Tápvonalak</translation>
<translation type="obsolete">Tápvonalak</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>Nemlineáris, aktív alkatrészek</translation>
<translation type="obsolete">Nemlineáris, aktív alkatrészek</translation>
</message>
<message>
<source>file data</source>
@ -7287,15 +7331,15 @@ Felülírjam?</translation>
</message>
<message>
<source>simulations</source>
<translation>Szimulációk</translation>
<translation type="obsolete">Szimulációk</translation>
</message>
<message>
<source>diagrams</source>
<translation>Diagramok</translation>
<translation type="obsolete">Diagramok</translation>
</message>
<message>
<source>paintings</source>
<translation>Feliratok, rajzelemek</translation>
<translation type="obsolete">Feliratok, rajzelemek</translation>
</message>
<message>
<source>Rename</source>
@ -7803,11 +7847,11 @@ Nem indítható a tápvonal tervező program!
</message>
<message>
<source>file components</source>
<translation>fájl alkatrészek</translation>
<translation type="obsolete">fájl alkatrészek</translation>
</message>
<message>
<source>digital components</source>
<translation>digitális alkatrészek</translation>
<translation type="obsolete">digitális alkatrészek</translation>
</message>
<message>
<source>Others</source>
@ -9679,11 +9723,7 @@ A kiválasztott elemeket vízszintesen egyvonalba mozgatja</translation>
</message>
<message>
<source>probes</source>
<translation>próbák</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
<translation type="obsolete">próbák</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -7281,6 +7281,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">componenti discreti</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">generatori</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">linee di trasmissione</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">componenti non lineari</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">dispositivi verilog-a</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">componenti digitali</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">componenti file</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simulazioni</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">diagrammi</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">disegni</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -8127,19 +8171,19 @@ Breve introduzione a Qucs</translation>
</message>
<message>
<source>lumped components</source>
<translation>componenti discreti</translation>
<translation type="obsolete">componenti discreti</translation>
</message>
<message>
<source>sources</source>
<translation>generatori</translation>
<translation type="obsolete">generatori</translation>
</message>
<message>
<source>transmission lines</source>
<translation>linee di trasmissione</translation>
<translation type="obsolete">linee di trasmissione</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>componenti non lineari</translation>
<translation type="obsolete">componenti non lineari</translation>
</message>
<message>
<source>file data</source>
@ -8147,15 +8191,15 @@ Breve introduzione a Qucs</translation>
</message>
<message>
<source>simulations</source>
<translation>simulazioni</translation>
<translation type="obsolete">simulazioni</translation>
</message>
<message>
<source>paintings</source>
<translation>disegni</translation>
<translation type="obsolete">disegni</translation>
</message>
<message>
<source>diagrams</source>
<translation>diagrammi</translation>
<translation type="obsolete">diagrammi</translation>
</message>
<message>
<source>Rename</source>
@ -8835,11 +8879,11 @@ Modifica lo schema</translation>
</message>
<message>
<source>file components</source>
<translation>componenti file</translation>
<translation type="obsolete">componenti file</translation>
</message>
<message>
<source>digital components</source>
<translation>componenti digitali</translation>
<translation type="obsolete">componenti digitali</translation>
</message>
<message>
<source>Others</source>
@ -10045,13 +10089,9 @@ Centra verticalmente gli elementi selezionati</translation>
<source>Cannot delete Verilog source: </source>
<translation type="obsolete">Impossibile cancellare sorgente Verilog: </translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>dispositivi verilog-a</translation>
<translation type="obsolete">dispositivi verilog-a</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -7062,6 +7062,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">Verilog-a </translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7174,19 +7218,19 @@ Usage: qucsedit [-r] file
</message>
<message>
<source>lumped components</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>sources</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>transmission lines</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>nonlinear components</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>file data</source>
@ -7194,15 +7238,15 @@ Usage: qucsedit [-r] file
</message>
<message>
<source>simulations</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>diagrams</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>paintings</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>Rename</source>
@ -7656,11 +7700,11 @@ Edits the schematic</source>
</message>
<message>
<source>file components</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>digital components</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>Others</source>
@ -9526,11 +9570,11 @@ Center vertically selected elements</source>
</message>
<message>
<source>probes</source>
<translation></translation>
<translation type="obsolete"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>Verilog-a </translation>
<translation type="obsolete">Verilog-a </translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -6814,6 +6814,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">дискреттік компоненттер</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">қорек көздері</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">тестілеу</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">мәліметтерді беру арнасы</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">сызықтық емес компоненттер</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">verilog құрылғылары</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">цифрлық компоненттер</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">файл компоненттері</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">Моделдеу түрлері</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">диаграммалар</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">суреттер</translation>
</message>
</context>
<context>
<name>QucsApp</name>
@ -7024,47 +7068,47 @@ Overwrite ?</source>
</message>
<message>
<source>lumped components</source>
<translation>дискреттік компоненттер</translation>
<translation type="obsolete">дискреттік компоненттер</translation>
</message>
<message>
<source>sources</source>
<translation>қорек көздері</translation>
<translation type="obsolete">қорек көздері</translation>
</message>
<message>
<source>probes</source>
<translation>тестілеу</translation>
<translation type="obsolete">тестілеу</translation>
</message>
<message>
<source>transmission lines</source>
<translation>мәліметтерді беру арнасы</translation>
<translation type="obsolete">мәліметтерді беру арнасы</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>сызықтық емес компоненттер</translation>
<translation type="obsolete">сызықтық емес компоненттер</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>verilog құрылғылары</translation>
<translation type="obsolete">verilog құрылғылары</translation>
</message>
<message>
<source>digital components</source>
<translation>цифрлық компоненттер</translation>
<translation type="obsolete">цифрлық компоненттер</translation>
</message>
<message>
<source>file components</source>
<translation>файл компоненттері</translation>
<translation type="obsolete">файл компоненттері</translation>
</message>
<message>
<source>simulations</source>
<translation>Моделдеу түрлері</translation>
<translation type="obsolete">Моделдеу түрлері</translation>
</message>
<message>
<source>diagrams</source>
<translation>диаграммалар</translation>
<translation type="obsolete">диаграммалар</translation>
</message>
<message>
<source>paintings</source>
<translation>суреттер</translation>
<translation type="obsolete">суреттер</translation>
</message>
<message>
<source>Rename</source>

View File

@ -7168,6 +7168,50 @@ Stosowanie: qucsedit [-r] plik
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">elementy skupione</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">źródła</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">linie transmisyjne</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">elementy nieliniowe</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">elementy cyfrowe</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">komponenty pliku</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">symulacje</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">wykresy</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">wzory graficzne</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7276,19 +7320,19 @@ Stosowanie: qucsedit [-r] plik
</message>
<message>
<source>lumped components</source>
<translation>elementy skupione</translation>
<translation type="obsolete">elementy skupione</translation>
</message>
<message>
<source>sources</source>
<translation>źródła</translation>
<translation type="obsolete">źródła</translation>
</message>
<message>
<source>transmission lines</source>
<translation>linie transmisyjne</translation>
<translation type="obsolete">linie transmisyjne</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>elementy nieliniowe</translation>
<translation type="obsolete">elementy nieliniowe</translation>
</message>
<message>
<source>file data</source>
@ -7296,15 +7340,15 @@ Stosowanie: qucsedit [-r] plik
</message>
<message>
<source>simulations</source>
<translation>symulacje</translation>
<translation type="obsolete">symulacje</translation>
</message>
<message>
<source>paintings</source>
<translation>wzory graficzne</translation>
<translation type="obsolete">wzory graficzne</translation>
</message>
<message>
<source>diagrams</source>
<translation>wykresy</translation>
<translation type="obsolete">wykresy</translation>
</message>
<message>
<source>Warning</source>
@ -7804,11 +7848,11 @@ Edytuj schemat</translation>
</message>
<message>
<source>file components</source>
<translation>komponenty pliku</translation>
<translation type="obsolete">komponenty pliku</translation>
</message>
<message>
<source>digital components</source>
<translation>elementy cyfrowe</translation>
<translation type="obsolete">elementy cyfrowe</translation>
</message>
<message>
<source>Others</source>
@ -9674,14 +9718,6 @@ wyśrodkowuje w pionie wybrane elementy</translation>
<source>Cannot delete Verilog source: </source>
<translation type="obsolete">Nie mogę usunąć źródła Verilog: </translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>
<translation type="unfinished"></translation>

View File

@ -6974,6 +6974,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">componentes soltos</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">fontes</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">ponteiras</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">linhas de transmissão</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">componentes não-lineares</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">componentes digitais</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">componentes em arquivo</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simulações</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">diagramas</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">desenho</translation>
</message>
</context>
<context>
<name>QucsApp</name>
@ -7176,39 +7220,39 @@ Overwrite ?</source>
</message>
<message>
<source>lumped components</source>
<translation>componentes soltos</translation>
<translation type="obsolete">componentes soltos</translation>
</message>
<message>
<source>sources</source>
<translation>fontes</translation>
<translation type="obsolete">fontes</translation>
</message>
<message>
<source>transmission lines</source>
<translation>linhas de transmissão</translation>
<translation type="obsolete">linhas de transmissão</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>componentes não-lineares</translation>
<translation type="obsolete">componentes não-lineares</translation>
</message>
<message>
<source>digital components</source>
<translation>componentes digitais</translation>
<translation type="obsolete">componentes digitais</translation>
</message>
<message>
<source>file components</source>
<translation>componentes em arquivo</translation>
<translation type="obsolete">componentes em arquivo</translation>
</message>
<message>
<source>simulations</source>
<translation>simulações</translation>
<translation type="obsolete">simulações</translation>
</message>
<message>
<source>diagrams</source>
<translation>diagramas</translation>
<translation type="obsolete">diagramas</translation>
</message>
<message>
<source>paintings</source>
<translation>desenho</translation>
<translation type="obsolete">desenho</translation>
</message>
<message>
<source>Rename</source>
@ -8540,11 +8584,7 @@ Sobre Qt da Trolltech</translation>
</message>
<message>
<source>probes</source>
<translation>ponteiras</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
<translation type="obsolete">ponteiras</translation>
</message>
<message>
<source>New Text</source>

View File

@ -7047,6 +7047,50 @@ Folosire: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">componente discrete</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">surse</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">linii de transmisie</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">componente neliniare</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simulări</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">diagrame</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">desene</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7135,19 +7179,19 @@ Folosire: qucsedit [-r] file
</message>
<message>
<source>lumped components</source>
<translation>componente discrete</translation>
<translation type="obsolete">componente discrete</translation>
</message>
<message>
<source>sources</source>
<translation>surse</translation>
<translation type="obsolete">surse</translation>
</message>
<message>
<source>transmission lines</source>
<translation>linii de transmisie</translation>
<translation type="obsolete">linii de transmisie</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>componente neliniare</translation>
<translation type="obsolete">componente neliniare</translation>
</message>
<message>
<source>file data</source>
@ -7155,15 +7199,15 @@ Folosire: qucsedit [-r] file
</message>
<message>
<source>simulations</source>
<translation>simulări</translation>
<translation type="obsolete">simulări</translation>
</message>
<message>
<source>paintings</source>
<translation>desene</translation>
<translation type="obsolete">desene</translation>
</message>
<message>
<source>diagrams</source>
<translation>diagrame</translation>
<translation type="obsolete">diagrame</translation>
</message>
<message>
<source>Rename</source>
@ -7653,14 +7697,6 @@ Editează această schemă</translation>
<source>permanently! Continue ?</source>
<translation type="obsolete">definitiv! Continuaţi?</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Others</source>
<translation type="unfinished"></translation>
@ -9410,14 +9446,6 @@ Center vertically selected elements</source>
<source>Verilog</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>
<translation type="unfinished"></translation>

View File

@ -7377,6 +7377,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">дискретные компоненты</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">источники</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">измерители</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">нелинейные компоненты</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">устройства verilog-a</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">цифровые компоненты</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">файловые компоненты</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">виды моделирования</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">диаграммы</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">рисунки</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7915,7 +7959,7 @@ Copies the selected section to the clipboard</source>
</message>
<message>
<source>digital components</source>
<translation>цифровые компоненты</translation>
<translation type="obsolete">цифровые компоненты</translation>
</message>
<message>
<source>Schematic</source>
@ -7987,35 +8031,35 @@ Copies the selected section to the clipboard</source>
</message>
<message>
<source>lumped components</source>
<translation>дискретные компоненты</translation>
<translation type="obsolete">дискретные компоненты</translation>
</message>
<message>
<source>sources</source>
<translation>источники</translation>
<translation type="obsolete">источники</translation>
</message>
<message>
<source>transmission lines</source>
<translation>линии передачи данных</translation>
<translation type="obsolete">линии передачи данных</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>нелинейные компоненты</translation>
<translation type="obsolete">нелинейные компоненты</translation>
</message>
<message>
<source>file components</source>
<translation>файловые компоненты</translation>
<translation type="obsolete">файловые компоненты</translation>
</message>
<message>
<source>simulations</source>
<translation>виды моделирования</translation>
<translation type="obsolete">виды моделирования</translation>
</message>
<message>
<source>diagrams</source>
<translation>диаграммы</translation>
<translation type="obsolete">диаграммы</translation>
</message>
<message>
<source>paintings</source>
<translation>рисунки</translation>
<translation type="obsolete">рисунки</translation>
</message>
<message>
<source>Rename</source>
@ -10037,11 +10081,11 @@ Center vertically selected elements</source>
</message>
<message>
<source>probes</source>
<translation>измерители</translation>
<translation type="obsolete">измерители</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>устройства verilog-a</translation>
<translation type="obsolete">устройства verilog-a</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -6928,6 +6928,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">diskreta komponeter</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">källor</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">transmissionslinjer</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">icke-linjära komponenter</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">digitala komponenter</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">filkomponenter</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">simuleringar</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">kurvor</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">färgläggningar</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7082,19 +7126,19 @@ Skriva över?</translation>
</message>
<message>
<source>lumped components</source>
<translation>diskreta komponeter</translation>
<translation type="obsolete">diskreta komponeter</translation>
</message>
<message>
<source>sources</source>
<translation>källor</translation>
<translation type="obsolete">källor</translation>
</message>
<message>
<source>transmission lines</source>
<translation>transmissionslinjer</translation>
<translation type="obsolete">transmissionslinjer</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>icke-linjära komponenter</translation>
<translation type="obsolete">icke-linjära komponenter</translation>
</message>
<message>
<source>file data</source>
@ -7102,15 +7146,15 @@ Skriva över?</translation>
</message>
<message>
<source>simulations</source>
<translation>simuleringar</translation>
<translation type="obsolete">simuleringar</translation>
</message>
<message>
<source>diagrams</source>
<translation>kurvor</translation>
<translation type="obsolete">kurvor</translation>
</message>
<message>
<source>paintings</source>
<translation>färgläggningar</translation>
<translation type="obsolete">färgläggningar</translation>
</message>
<message>
<source>Rename</source>
@ -7448,11 +7492,11 @@ Redigerar schemat</translation>
</message>
<message>
<source>digital components</source>
<translation>digitala komponenter</translation>
<translation type="obsolete">digitala komponenter</translation>
</message>
<message>
<source>file components</source>
<translation>filkomponenter</translation>
<translation type="obsolete">filkomponenter</translation>
</message>
<message>
<source>Others</source>
@ -9290,14 +9334,6 @@ Center vertically selected elements</source>
<source>Verilog</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>
<translation type="unfinished"></translation>

View File

@ -6971,6 +6971,50 @@ Kullanım: qucsedit [-r] kütük
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">sınıflandırılmamış bileşenler</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">kaynaklar</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">ölçüm uçları</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">iletim hatları</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">doğrusal olmayan bileşenler</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished">verilog-a devre elemanları</translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">dijital bileşenler</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">kütük bileşenleri</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">benzetimler</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">çizgeler</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">boyamalar</translation>
</message>
</context>
<context>
<name>QucsActions</name>
@ -7129,39 +7173,39 @@ Overwrite ?</source>
</message>
<message>
<source>lumped components</source>
<translation>sınıflandırılmamış bileşenler</translation>
<translation type="obsolete">sınıflandırılmamış bileşenler</translation>
</message>
<message>
<source>sources</source>
<translation>kaynaklar</translation>
<translation type="obsolete">kaynaklar</translation>
</message>
<message>
<source>transmission lines</source>
<translation>iletim hatları</translation>
<translation type="obsolete">iletim hatları</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>doğrusal olmayan bileşenler</translation>
<translation type="obsolete">doğrusal olmayan bileşenler</translation>
</message>
<message>
<source>digital components</source>
<translation>dijital bileşenler</translation>
<translation type="obsolete">dijital bileşenler</translation>
</message>
<message>
<source>file components</source>
<translation>kütük bileşenleri</translation>
<translation type="obsolete">kütük bileşenleri</translation>
</message>
<message>
<source>simulations</source>
<translation>benzetimler</translation>
<translation type="obsolete">benzetimler</translation>
</message>
<message>
<source>diagrams</source>
<translation>çizgeler</translation>
<translation type="obsolete">çizgeler</translation>
</message>
<message>
<source>paintings</source>
<translation>boyamalar</translation>
<translation type="obsolete">boyamalar</translation>
</message>
<message>
<source>Rename</source>
@ -9378,11 +9422,11 @@ Seçili bileşenleri dikey olarak ortala</translation>
</message>
<message>
<source>probes</source>
<translation>ölçüm uçları</translation>
<translation type="obsolete">ölçüm uçları</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation>verilog-a devre elemanları</translation>
<translation type="obsolete">verilog-a devre elemanları</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>

View File

@ -6966,6 +6966,50 @@ Usage: qucsedit [-r] file
<source>Cannot save C++ file &quot;%1&quot;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>lumped components</source>
<translation type="unfinished">дискретні компоненти</translation>
</message>
<message>
<source>sources</source>
<translation type="unfinished">джерела</translation>
</message>
<message>
<source>probes</source>
<translation type="unfinished">проби</translation>
</message>
<message>
<source>transmission lines</source>
<translation type="unfinished">лінії передачі</translation>
</message>
<message>
<source>nonlinear components</source>
<translation type="unfinished">нелінійні компоненти</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>digital components</source>
<translation type="unfinished">цифрові компоненти</translation>
</message>
<message>
<source>file components</source>
<translation type="unfinished">файлові компоненти</translation>
</message>
<message>
<source>simulations</source>
<translation type="unfinished">види моделювання</translation>
</message>
<message>
<source>diagrams</source>
<translation type="unfinished">діаграми</translation>
</message>
<message>
<source>paintings</source>
<translation type="unfinished">малюнки</translation>
</message>
</context>
<context>
<name>QucsApp</name>
@ -7113,7 +7157,7 @@ Quits the application</source>
</message>
<message>
<source>digital components</source>
<translation>цифрові компоненти</translation>
<translation type="obsolete">цифрові компоненти</translation>
</message>
<message>
<source>Schematic</source>
@ -7177,35 +7221,35 @@ Quits the application</source>
</message>
<message>
<source>lumped components</source>
<translation>дискретні компоненти</translation>
<translation type="obsolete">дискретні компоненти</translation>
</message>
<message>
<source>sources</source>
<translation>джерела</translation>
<translation type="obsolete">джерела</translation>
</message>
<message>
<source>transmission lines</source>
<translation>лінії передачі</translation>
<translation type="obsolete">лінії передачі</translation>
</message>
<message>
<source>nonlinear components</source>
<translation>нелінійні компоненти</translation>
<translation type="obsolete">нелінійні компоненти</translation>
</message>
<message>
<source>file components</source>
<translation>файлові компоненти</translation>
<translation type="obsolete">файлові компоненти</translation>
</message>
<message>
<source>simulations</source>
<translation>види моделювання</translation>
<translation type="obsolete">види моделювання</translation>
</message>
<message>
<source>diagrams</source>
<translation>діаграми</translation>
<translation type="obsolete">діаграми</translation>
</message>
<message>
<source>paintings</source>
<translation>малюнки</translation>
<translation type="obsolete">малюнки</translation>
</message>
<message>
<source>Rename</source>
@ -9499,11 +9543,7 @@ About Qt by Trolltech</source>
</message>
<message>
<source>probes</source>
<translation>проби</translation>
</message>
<message>
<source>verilog-a devices</source>
<translation type="unfinished"></translation>
<translation type="obsolete">проби</translation>
</message>
<message>
<source>&amp;Import/Export Data...</source>