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Added Xyce libcomp support

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This commit is contained in:
Vadim Kuznetzov 2015-02-01 14:46:43 +03:00
parent 4700d7d747
commit 570bbbccfb
8 changed files with 29 additions and 21 deletions
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5
qucs/components/libcomp.cpp
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@ -233,8 +233,11 @@ bool LibComp::createSubNetlist(QTextStream *stream, QStringList &FileList,
} else if(type&4) {
r = loadSection("VerilogModel", FileString, &Includes);
} else if(type&8) {
r = loadSection("Model", FileString, &Includes);
r = loadSection("Model", FileString, &Includes); // Ngspice
FileString = qucs2spice::convert_netlist(FileString);
} else if (type&16) {
r = loadSection("Model", FileString, &Includes); // Xyce
FileString = qucs2spice::convert_netlist(FileString,true);
}
if(r < 0) return false;

4
qucs/extsimkernels/abstractspicekernel.cpp
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@ -60,11 +60,11 @@ void AbstractSpiceKernel::killThemAll()
}
bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream)
bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream, bool xyce)
{
QStringList collect;
QTextEdit *err = new QTextEdit;
Sch->prepareNetlist(stream,collect,err,true);
Sch->prepareNetlist(stream,collect,err,true,xyce);
delete err;
Sch->clearSignalsAndFileList(); // for proper build of subckts
return true; // TODO: Add feature to determine ability of spice simulation

2
qucs/extsimkernels/abstractspicekernel.h
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@ -39,7 +39,7 @@ protected:
Schematic *Sch;
bool prepareSpiceNetlist(QTextStream &stream);
bool prepareSpiceNetlist(QTextStream &stream, bool xyce = false);
virtual void createNetlist(QTextStream& stream, int NumPorts,QStringList& simulations,
QStringList& vars, QStringList &outputs);

7
qucs/extsimkernels/qucs2spice.cpp
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@ -1,6 +1,6 @@
#include "qucs2spice.h"
QString qucs2spice::convert_netlist(QString netlist)
QString qucs2spice::convert_netlist(QString netlist, bool xyce)
{
QStringList net_lst=netlist.split("\n");
@ -28,8 +28,8 @@ QString qucs2spice::convert_netlist(QString netlist)
if (cap_pattern.exactMatch(line)) s += convert_rcl(line);
if (ind_pattern.exactMatch(line)) s += convert_rcl(line);
if (diode_pattern.exactMatch(line)) s += convert_diode(line);
if (mosfet_pattern.exactMatch(line)) s += convert_mosfet(line);
if (jfet_pattern.exactMatch(line)) s += convert_jfet(line);
if (mosfet_pattern.exactMatch(line)) s += convert_mosfet(line,xyce);
if (jfet_pattern.exactMatch(line)) s += convert_jfet(line,xyce);
if (bjt_pattern.exactMatch(line)) s += convert_bjt(line);
if (vccs_pattern.exactMatch(line)) s += convert_vccs(line);
if (vcvs_pattern.exactMatch(line)) s += convert_vcvs(line);
@ -109,6 +109,7 @@ QString qucs2spice::convert_mosfet(QString line, bool xyce)
} else if (s1.startsWith("Type=\"pfet\"")) {
Typ = "PMOS";
} else {
if (!s1.startsWith("N=")) // add ignore list
par_lst.append(s1); // usual parameter
}
}

2
qucs/extsimkernels/qucs2spice.h
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@ -17,7 +17,7 @@ namespace qucs2spice
QString convert_vccs(QString line);
QString convert_vcvs(QString line);
QString convert_vcs(QString line, bool voltage);
QString convert_netlist(QString netlist);
QString convert_netlist(QString netlist, bool xyce=false);
}
#endif // QUCS2SPICE_H

2
qucs/extsimkernels/xyce.cpp
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@ -41,7 +41,7 @@ void Xyce::determineUsedSimulations()
void Xyce::createNetlist(QTextStream &stream, int NumPorts, QStringList &simulations,
QStringList &vars, QStringList &outputs)
{
if(!prepareSpiceNetlist(stream)) return; // Unable to perform ngspice simulation
if(!prepareSpiceNetlist(stream,true)) return; // Unable to perform ngspice simulation
QString s;
for(Component *pc = Sch->DocComps.first(); pc != 0; pc = Sch->DocComps.next()) {

8
qucs/schematic.h
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@ -277,7 +277,7 @@ public:
bool createLibNetlist(QTextStream*, QTextEdit*, int);
bool createSubNetlist(QTextStream *, int&, QStringList&, QTextEdit*, int);
void createSubNetlistPlain(QTextStream*, QTextEdit*, int);
int prepareNetlist(QTextStream&, QStringList&, QTextEdit*,bool spice=false);
int prepareNetlist(QTextStream&, QStringList&, QTextEdit*,bool spice=false, bool xyce = false);
QString createNetlist(QTextStream&, int);
bool loadDocument();
void highlightWireLabels (void);
@ -307,10 +307,12 @@ private:
void throughAllNodes(bool, QStringList&, int&);
void propagateNode(QStringList&, int&, Node*);
void collectDigitalSignals(void);
bool giveNodeNames(QTextStream *, int&, QStringList&, QTextEdit*, int,bool spice = false);
bool giveNodeNames(QTextStream *, int&, QStringList&, QTextEdit*, int,
bool spice = false, bool xyce = false);
void beginNetlistDigital(QTextStream &);
void endNetlistDigital(QTextStream &);
bool throughAllComps(QTextStream *, int&, QStringList&, QTextEdit *, int,bool spice = false);
bool throughAllComps(QTextStream *, int&, QStringList&, QTextEdit *, int,
bool spice = false, bool xyce = false);
DigMap Signals; // collecting node names for VHDL signal declarations
QStringList PortTypes;

20
qucs/schematic_file.cpp
View File

@ -1204,7 +1204,7 @@ void Schematic::propagateNode(QStringList& Collect,
* \return true in case of success (false otherwise)
*/
bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
QStringList& Collect, QTextEdit *ErrText, int NumPorts, bool spice)
QStringList& Collect, QTextEdit *ErrText, int NumPorts, bool spice, bool xyce)
{
bool r;
QString s;
@ -1319,10 +1319,12 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
continue; // insert each library subcircuit just one time
FileList.insert(s, SubFile("LIB", s));
if(isAnalog) {
if (spice) r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 8);
else r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 1);
} else {
if(isAnalog) {
if (spice) {
if (xyce) r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 16);
else r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 8);
} else r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 1);
} else {
if(isVerilog)
r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 4);
else
@ -1403,7 +1405,7 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
// each component. Output into "stream", NodeSets are collected in
// "Collect" and counted with "countInit".
bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
QStringList& Collect, QTextEdit *ErrText, int NumPorts,bool spice)
QStringList& Collect, QTextEdit *ErrText, int NumPorts, bool spice, bool xyce)
{
// delete the node names
for(Node *pn = DocNodes.first(); pn != 0; pn = DocNodes.next()) {
@ -1427,7 +1429,7 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
}
// go through components
if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts,spice))
if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts,spice,xyce))
return false;
// work on named nodes first in order to preserve the user given names
@ -1778,7 +1780,7 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
// ---------------------------------------------------
// Determines the node names and writes subcircuits into netlist file.
int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
QTextEdit *ErrText, bool spice)
QTextEdit *ErrText,bool spice,bool xyce)
{
if(showBias > 0) showBias = -1; // do not show DC bias anymore
@ -1853,7 +1855,7 @@ int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
}
int countInit = 0; // counts the nodesets to give them unique names
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts,spice))
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts,spice,xyce))
return -10;
if(allTypes & isAnalogComponent)