First concept of Verilog-A modules builder. EDD implemented

qucs/components/component.cpp

@@ -671,7 +671,7 @@ QString Component::spice_netlist(bool)
 
 QString Component::va_code()
 {
-    return QString("\n"); // ignore if not implemented
+    return QString(""); // ignore if not implemented
 }
 
 // -------------------------------------------------------

qucs/components/component.h

@@ -43,6 +43,8 @@ public:
   virtual QString getProbeVariable(bool isXyce = false);
   virtual QString getNgspiceBeforeSim(QString sim, int lvl=0);
   virtual QString getNgspiceAfterSim(QString sim, int lvl=0);
+  virtual QString getVAvariables() {return QString("");};
+  virtual QString getVAExpressions() {return QString("");};
   QString get_VHDL_Code(int);
   QString get_Verilog_Code(int);
   void    paint(ViewPainter*);

qucs/components/eqndefined.cpp

@@ -18,6 +18,7 @@
 #include "main.h"
 #include "schematic.h"
 #include "extsimkernels/spicecompat.h"
+#include "extsimkernels/verilogawriter.h"
 #include <QtCore>
 
 #include <QFileInfo>
@@ -152,6 +153,37 @@ QString EqnDefined::spice_netlist(bool isXyce)
     return s;
 }
 
+QString EqnDefined::va_code()
+{
+    QString s;
+
+    if (Props.at(0)->Value=="explicit") {
+        int Nbranch = Props.at(1)->Value.toInt();
+
+        for (int i=0;i<Nbranch;i++) {
+            QString Ieqn = Props.at(2*(i+1))->Value; // parse current equation
+            QStringList Itokens;
+            spicecompat::splitEqn(Ieqn,Itokens);
+            vacompat::convert_functions(Itokens);
+            subsVoltages(Itokens,Nbranch);
+            QString plus = Ports.at(2*i)->Connection->Name;
+            QString minus = Ports.at(2*i+1)->Connection->Name;
+            s += QString("I(%1,%2) <+ %3;\n").arg(plus).arg(minus).arg(Itokens.join(""));
+            QString Qeqn = Props.at(2*(i+1)+1)->Value; // parse charge equation only for Xyce
+            if (Qeqn!="0") {
+                QStringList Qtokens;
+                spicecompat::splitEqn(Qeqn,Qtokens);
+                vacompat::convert_functions(Qtokens);
+                subsVoltages(Qtokens,Nbranch);
+                s += QString("I(%1,%2) <+ ddt(%3);\n").arg(plus).arg(minus).arg(Qtokens.join(""));
+            }
+        }
+    } else {
+        s = "";
+    }
+    return s;
+}
+
 /*!
  * \brief EqnDefined::subsVoltages Substitute volatges in spice Notation in token list
  * \param[in/out] tokens Token list. Should be obtained from spicecompat::splitEqn().
@@ -171,7 +203,7 @@ void EqnDefined::subsVoltages(QStringList &tokens, int Nbranch)
                 if (plus=="gnd") plus="0";
                 QString minus = Ports.at(2*(branch-1)+1)->Connection->Name;
                 if (minus=="gnd") minus="0";
-                *it = QString("(V(%1)-V(%2))").arg(plus).arg(minus);
+                *it = QString("V(%1,%2)").arg(plus).arg(minus);
             }
         }
     }

qucs/components/eqndefined.h

@@ -37,6 +37,7 @@ protected:
   QString netlist();
   void createSymbol();
   QString spice_netlist(bool isXyce);
+  QString va_code();
 };
 
 #endif

qucs/components/equation.cpp

@@ -17,6 +17,7 @@
 #include "equation.h"
 #include "main.h"
 #include "extsimkernels/spicecompat.h"
+#include "extsimkernels/verilogawriter.h"
 
 #include <QFontMetrics>
 
@@ -92,6 +93,28 @@ Element* Equation::info(QString& Name, char* &BitmapFile, bool getNewOne)
   return 0;
 }
 
+QString Equation::getVAvariables()
+{
+    QStringList vars;
+    for (unsigned int i=0;i<Props.count()-1;i++) {
+        vars.append(Props.at(i)->Name);
+    }
+
+    return QString("real %1;\n").arg(vars.join(", "));
+}
+
+QString Equation::getVAExpressions()
+{
+    QString s;
+    for (unsigned int i=0;i<Props.count()-1;i++) {
+        QStringList tokens;
+        spicecompat::splitEqn(Props.at(i)->Value,tokens);
+        vacompat::convert_functions(tokens);
+        s += QString("%1=%2;\n").arg(Props.at(i)->Name).arg(tokens.join(""));
+    }
+    return s;
+}
+
 /*!
  * \brief Equation::getExpression Extract equations that don't contain simualtion variables
  *        (voltages/cureents) in .PARAM section of spice netlist

qucs/components/equation.h

@@ -30,6 +30,8 @@ public:
   static Element* info(QString&, char* &, bool getNewOne=false);
   QString getExpression(bool isXyce);
   QString getEquations(QString sim, QStringList &dep_vars);
+  QString getVAvariables();
+  QString getVAExpressions();
   QString getNgspiceScript();
 
 private:

qucs/extsimkernels/verilogawriter.cpp

@@ -1,5 +1,75 @@
+/*
+ * verilogawriter.cpp - Subcircuit to Verilog-A module converter implementation
+ *
+ * Copyright (C) 2015, Vadim Kuznetsov, ra3xdh@gmail.com
+ *
+ * This file is part of Qucs
+ *
+ * Qucs is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This software is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Qucs.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+
 #include "verilogawriter.h"
 #include <QPlainTextEdit>
+#include "paintings/id_text.h"
+
+void vacompat::convert_functions(QStringList &tokens)
+{
+    QStringList conv_list; // Put here functions need to be converted
+    conv_list<<"q"<<"`P_Q"
+            <<"kB"<<"`P_K"
+            <<"pi"<<"`M_PI";
+
+    for(QStringList::iterator it = tokens.begin();it != tokens.end(); it++) {
+        for(int i=0;i<conv_list.count();i+=2) {
+            if (conv_list.at(i)==(*it))
+                (*it) = conv_list.at(i+1);
+        }
+    }
+
+}
+
+QString vacompat::normalize_value(QString Value)
+{
+    QRegExp r_pattern("^[0-9]+.*Ohm$");
+    QRegExp c_pattern("^[0-9]+.*F$");
+    QRegExp l_pattern("^[0-9]+.*H$");
+    QRegExp v_pattern("^[0-9]+.*V$");
+    QRegExp hz_pattern("^[0-9]+.*Hz$");
+    QRegExp s_pattern("^[0-9]+.*S$");
+
+    QString s = Value.remove(' ');
+    if (s.startsWith('\'')&&s.endsWith('\'')) return Value.remove('\''); // Expression detected
+
+    if (r_pattern.exactMatch(s)) { // Component value
+        s.remove("Ohm");
+    } else if (c_pattern.exactMatch(s)) {
+        s.remove("F");
+    } else if (l_pattern.exactMatch(s)) {
+        s.remove("H");
+    } else if (v_pattern.exactMatch(s)) {
+        s.remove("V");
+    } else if (hz_pattern.exactMatch(s)) {
+        s.remove("Hz");
+    } else if (s_pattern.exactMatch(s)) {
+        s.remove("S");
+    } else
+
+    return s;
+}
+
 
 VerilogAwriter::VerilogAwriter()
 {
@@ -35,27 +105,61 @@ bool VerilogAwriter::createVA_module(QTextStream &stream, Schematic *sch)
     QStringList ports;
     QStringList nodes;
     for(Component *pc = sch->DocComps.first(); pc != 0; pc = sch->DocComps.next()) {
-        if (pc->Model=="Port") {
+        if (pc->Model=="Port") { // Find module ports
             QString s = pc->Ports.first()->Connection->Name;
             if (!ports.contains(s)) ports.append(s);
         } else {
-            foreach(Port *pp,pc->Ports) {
+            foreach(Port *pp,pc->Ports) { // Find all signals
                 QString s = pp->Connection->Name;
                 if (!nodes.contains(s)) nodes.append(s);
             }
         }
     }
 
+    QFileInfo inf(sch->DocName);
+    QString base = inf.completeBaseName();
+    base.remove('-').remove(' ');
 
+    stream<<QString("module %1(%2);\n").arg(base).arg(ports.join(", "));
+    stream<<QString("inout %1;\n").arg(ports.join(", "));
+    stream<<QString("electrical %1;\n").arg(nodes.join(", "));
+
+    Painting *pi; // Find module parameters
+    for(pi = sch->SymbolPaints.first(); pi != 0; pi = sch->SymbolPaints.next())
+      if(pi->Name == ".ID ") {
+        ID_Text *pid = (ID_Text*)pi;
+        QList<SubParameter *>::const_iterator it;
+        for(it = pid->Parameter.constBegin(); it != pid->Parameter.constEnd(); it++) {
+            QString s = "parameter real " + (*it)->Name + ";\n";
+            stream<<s;
+        }
+        break;
+      }
+
+
+    // List all variables
+    for(Component *pc = sch->DocComps.first(); pc != 0; pc = sch->DocComps.next()) {
+        if (pc->isEquation) {
+            stream<<pc->getVAvariables();
+        }
+    }
 
     stream<<"analog begin \n"
             "@(initial model)\n"
             "begin \n";
+    // Output expressions
+    for(Component *pc = sch->DocComps.first(); pc != 0; pc = sch->DocComps.next()) {
+        if (pc->isEquation) {
+            stream<<pc->getVAExpressions();
+        }
+    }
+
     stream<<"end\n";
 
-     for(Component *pc = sch->DocComps.first(); pc != 0; pc = sch->DocComps.next()) {
+    // Convert components to current equations.
+    for(Component *pc = sch->DocComps.first(); pc != 0; pc = sch->DocComps.next()) {
          stream<<pc->getVerilogACode();
-     }
+    }
 
     stream<<"end\n"
             "endmodule\n";

qucs/extsimkernels/verilogawriter.h

@@ -1,9 +1,36 @@
+/*
+ * verilogawriter.h - Subcircuit to Verilog-A module converter declaration
+ *
+ * Copyright (C) 2015, Vadim Kuznetsov, ra3xdh@gmail.com
+ *
+ * This file is part of Qucs
+ *
+ * Qucs is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This software is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Qucs.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
 #ifndef VERILOGAWRITER_H
 #define VERILOGAWRITER_H
 
 #include <QtCore>
 #include <schematic.h>
 
+namespace vacompat {
+    QString normalize_value(QString Value);
+    void convert_functions(QStringList &tokens);
+}
+
 class VerilogAwriter
 {