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Merge pull request #262 from Radvall/add_flip_flops

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Added spice entry for flip-flops
This commit is contained in:
Vadim Kuznetsov 2023-04-21 17:04:56 +02:00 committed by GitHub
commit 7e2f2abcd3
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GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 331 additions and 6 deletions
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218
examples/ngspice/flip_flops_truth_tables.sch Normal file
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<Line 2680 -240 0 2180 #000000 1 1>
<Text 2140 -230 20 #000000 0 "T flip-flop with SR">
<Text 3020 -230 20 #000000 0 "RS flip-flop">
<Line 1860 220 1650 0 #000000 1 1>
<Line 200 -180 3310 0 #000000 1 1>
<Line 200 1690 820 0 #000000 1 1>
<Rectangle 200 220 3310 1720 #000000 1 1 #c0c0c0 1 0>
<Rectangle 200 -240 3310 460 #000000 1 1 #c0c0c0 1 0>
<Text 450 -230 20 #000000 0 "D flip-flop with SR">
<Text 1390 -230 20 #000000 0 "JK flip-flop with SR">
<Line 1850 -240 0 2180 #000000 1 1>
</Paintings>

29
qucs/components/d_flipflop.cpp
View File

@ -17,10 +17,11 @@
#include "d_flipflop.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
D_FlipFlop::D_FlipFlop()
{
Type = isDigitalComponent;
Type = isComponent;
Description = QObject::tr("D flip flop with asynchronous reset");
Props.append(new Property("t", "0", false, QObject::tr("delay time")));
@ -52,6 +53,7 @@ D_FlipFlop::D_FlipFlop()
ty = y2+4;
Model = "DFF";
Name = "Y";
SpiceModel = "A";
}
// -------------------------------------------------------
@ -119,3 +121,28 @@ Element* D_FlipFlop::info(QString& Name, char* &BitmapFile, bool getNewOne)
if(getNewOne) return new D_FlipFlop();
return 0;
}
QString D_FlipFlop::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("t")->Value);
QString SET = "0";
QString QB = "QB_" + Name;
QString D = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
s += QString("C%1 QB_%1 0 1e-9 \n").arg(Name); // capacitor load for unused QB pin
return s;
}

1
qucs/components/d_flipflop.h
View File

@ -31,6 +31,7 @@ public:
protected:
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};
#endif

25
qucs/components/dff_SR.cpp
View File

@ -18,6 +18,7 @@
#include "dff_SR.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
dff_SR::dff_SR()
{
@ -37,6 +38,7 @@ dff_SR::dff_SR()
ty = y2 + 4;
Model = "dff_SR";
Name = "Y";
SpiceModel = "A";
}
Component * dff_SR::newOne()
@ -173,3 +175,26 @@ QString dff_SR::verilogCode( int )
" end\n";
return l;
}
QString dff_SR::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("Delay")->Value);
QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString D = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);
s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
return s;
}

1
qucs/components/dff_SR.h
View File

@ -24,6 +24,7 @@ class dff_SR : public Component
void createSymbol();
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};
#endif /* dff_SR_H */

26
qucs/components/jkff_SR.cpp
View File

@ -18,6 +18,7 @@
#include "jkff_SR.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
jkff_SR::jkff_SR()
{
@ -37,6 +38,7 @@ jkff_SR::jkff_SR()
ty = y2 + 4;
Model = "jkff_SR";
Name = "Y";
SpiceModel = "A";
}
Component * jkff_SR::newOne()
@ -183,3 +185,27 @@ QString jkff_SR::verilogCode( int )
" end\n";
return l;
}
QString jkff_SR::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("Delay")->Value);
QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString J = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString K = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
QString QB = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(6)->Connection->Name);
s += " " + J + " " + K + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_jkff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
return s;
}

1
qucs/components/jkff_SR.h
View File

@ -24,6 +24,7 @@ class jkff_SR : public Component
void createSymbol();
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};
#endif /* jkff_SR_H */

27
qucs/components/tff_SR.cpp
View File

@ -18,6 +18,7 @@
#include "tff_SR.h"
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
tff_SR::tff_SR()
{
@ -36,7 +37,8 @@ tff_SR::tff_SR()
tx = x1 + 4;
ty = y2 + 4;
Model = "tff_SR";
Name = "Y";
Name = "Y";
SpiceModel = "A";
}
Component * tff_SR::newOne()
@ -174,3 +176,26 @@ QString tff_SR::verilogCode( int )
" end\n";
return l;
}
QString tff_SR::spice_netlist(bool isXyce)
{
if (isXyce) return QString("");
QString s = SpiceModel + Name;
QString tmp_model = "model_" + Name;
QString td = spicecompat::normalize_value(getProperty("Delay")->Value);
QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
QString T = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);
s += " " + T + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;
s += " " + tmp_model + "\n";
s += QString(".model %1 d_tff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
.arg(tmp_model).arg(td);
return s;
}

1
qucs/components/tff_SR.h
View File

@ -24,6 +24,7 @@ class tff_SR : public Component
void createSymbol();
QString vhdlCode(int);
QString verilogCode(int);
QString spice_netlist(bool isXyce);
};
#endif /* tff_SR_H */

8
qucs/module.cpp
View File

@ -447,11 +447,7 @@ void Module::registerModules (void) {
REGISTER_DIGITAL_1 (fa1b);
REGISTER_DIGITAL_1 (fa2b);
REGISTER_DIGITAL_1 (RS_FlipFlop);
REGISTER_DIGITAL_1 (D_FlipFlop);
REGISTER_DIGITAL_1 (dff_SR);
REGISTER_DIGITAL_1 (JK_FlipFlop);
REGISTER_DIGITAL_1 (jkff_SR);
REGISTER_DIGITAL_1 (tff_SR);
REGISTER_DIGITAL_1 (gatedDlatch);
REGISTER_DIGITAL_1 (logic_0);
REGISTER_DIGITAL_1 (logic_1);
@ -481,6 +477,10 @@ void Module::registerModules (void) {
REGISTER_DIGITAL_1 (Logical_AND);
REGISTER_DIGITAL_1 (Logical_XOR);
REGISTER_DIGITAL_1 (Logical_XNOR);
REGISTER_DIGITAL_1 (D_FlipFlop);
REGISTER_DIGITAL_1 (dff_SR);
REGISTER_DIGITAL_1 (jkff_SR);
REGISTER_DIGITAL_1 (tff_SR);
}
// file components