2009-04-17 Stefan Jahn <stefan@lkcc.org>

* schematic_file.cpp (createSubNetlistPlain): Create parameter
        lists in Verilog-HDL subcircuits.

2009-04-17  Stefan Jahn  <stefan@lkcc.org>

        * subcircuit.cpp (verilogCode): Passing subcircuit parameters to
        Verilog-HDL subcircuits.

NEWS

@@ -26,6 +26,7 @@ files.
 Version 0.0.15
 --------------
 
+ * VHDL files and subcircuits can handle typed generic parameters
  * translation into Arabic
  * import dialog replaced by complete import/export frontend for the
    Qucs-Converter command line tool

qucs/ChangeLog

@@ -1,3 +1,8 @@
+2009-04-17  Stefan Jahn  <stefan@lkcc.org>
+
+	* schematic_file.cpp (createSubNetlistPlain): Create parameter
+	lists in Verilog-HDL subcircuits.
+
 2009-04-16  Stefan Jahn  <stefan@lkcc.org>
 
 	* dialogs/labeldialog.cpp (LabelDialog): Allow input of global

qucs/components/ChangeLog

@@ -1,3 +1,8 @@
+2009-04-17  Stefan Jahn  <stefan@lkcc.org>
+
+	* subcircuit.cpp (verilogCode): Passing subcircuit parameters to
+	Verilog-HDL subcircuits.
+
 2009-04-13  Stefan Jahn  <stefan@lkcc.org>
 
 	* component.cpp (paint): Made simulation boxes and component texts

qucs/components/logical_inv.cpp

@@ -72,15 +72,14 @@ QString Logical_Inv::verilogCode(int NumPorts)
   QString s ("");
 
   if (synthesize) {
-    s = "  assign ";
+    s = "  assign";
 
-    if(NumPorts <= 0)  // no truth table simulation ?
-      if(strtod(Props.at(1)->Value.latin1(), 0) != 0.0) {  // delay time
-	QString t = Props.current()->Value;
-	if(!Verilog_Time(t, Name))
-	  return t;    // time has not VHDL format
-	s += "#" + t + " ";
-      }
+    if(NumPorts <= 0) { // no truth table simulation ?
+      QString td = Props.at(1)->Value;
+      if(!Verilog_Delay(td, Name))
+	return td;    // time has not VHDL format
+      s += td + " ";
+    }
     s += pp->Connection->Name + " = ";  // output port
     pp = Ports.next();
     s += "~" + pp->Connection->Name;   // input port
@@ -89,13 +88,12 @@ QString Logical_Inv::verilogCode(int NumPorts)
   else {
     s = "  not";
 
-    if(NumPorts <= 0)  // no truth table simulation ?
-      if(strtod(Props.at(1)->Value.latin1(), 0) != 0.0) {  // delay time
-	QString t = Props.current()->Value;
-	if(!Verilog_Time(t, Name))
-	  return t;    // time has not VHDL format
-	s += " #" + t;
-      }
+    if(NumPorts <= 0) { // no truth table simulation ?
+      QString td = Props.at(1)->Value;
+      if(!Verilog_Delay(td, Name))
+	return td;    // time has not VHDL format
+      s += td;
+    }
     s += " " + Name + " (" + pp->Connection->Name;  // output port
     pp = Ports.next();
     s += ", " + pp->Connection->Name; // first input port

qucs/components/mux2to1.cpp

@@ -124,14 +124,10 @@ QString mux2to1::vhdlCode( int )
 
 QString mux2to1::verilogCode( int )
 {
-  QString td = " ";
-
-  if(strtod(Props.at(1)->Value.latin1(), 0) != 0.0) { // delay time
-    td = Props.at(1)->Value;
-    if(!Verilog_Time(td, Name))
-      return td;    // time has not VHDL format.
-    td = " #" + td;
-  }
+  QString td = Props.at(1)->Value;
+  if(!VHDL_Delay(td, Name))
+    return td;      // Time does not have VHDL format.
+  td += " ";
   
   QString l = "";
 
@@ -148,7 +144,7 @@ QString mux2to1::verilogCode( int )
       "  reg     " + v + " = 0;\n" +
       "  always @ (" + En + " or " + A + " or "
                      + D0 + " or " + D1 +  ")\n" +
-      "    " + v + " <=" + td + " (" + D1 + " && " + A + ")" + " || " +
+      "    " + v + " <=" + td + "(" + D1 + " && " + A + ")" + " || " +
                "(" + D0 + " && (~" + A + "));\n" ;
 
   return l;

qucs/components/subcircuit.cpp

@@ -247,9 +247,20 @@ QString Subcircuit::vhdlCode(int)
 QString Subcircuit::verilogCode(int)
 {
   QString f = properFileName(Props.first()->Value);
-  QString s = "  Sub_" + properName(f) + " " + Name + " (";
+  QString s = "  Sub_" + properName(f);
+
+  // output all user defined properties
+  Property *pr = Props.next();
+  if (pr) {
+    s += " #(";
+    s += Verilog_Param(pr->Value);
+    for(pr = Props.next(); pr != 0; pr = Props.next())
+      s += ", " + Verilog_Param(pr->Value);
+    s += ")";
+  }
 
   // output all node names
+  s +=  " " + Name + " (";
   Port *pp = Ports.first();
   if(pp)  s += pp->Connection->Name;
   for(pp = Ports.next(); pp != 0; pp = Ports.next())

qucs/main.cpp

@@ -439,6 +439,41 @@ bool VHDL_Time(QString& t, const QString& Name)
   return true;
 }
 
+// #########################################################################
+// Returns parameters for Verilog modules.
+QString Verilog_Param(const QString Value)
+{
+  if(strtod(Value.latin1(), 0) != 0.0) {
+    QString td = Value;
+    if(!Verilog_Time(td, "parameter"))
+      return Value;
+    else
+      return td;
+  }
+  else
+    return Value;
+}
+
+// #########################################################################
+// Creates and returns delay time for Verilog modules.
+bool Verilog_Delay(QString& td, const QString& Name)
+{
+  if(strtod(td.latin1(), 0) != 0.0) {  // delay time property
+    if(!Verilog_Time(td, Name))
+      return false;    // time has not Verilog format
+    td = " #" + td;
+    return true;
+  }
+  else if(isalpha(td.latin1()[0])) {
+    td = " #" + td;
+    return true;
+  }
+  else {
+    td = "";
+    return true;
+  }
+}
+
 // #########################################################################
 // Checks and corrects a time (number & unit) according Verilog standard.
 bool Verilog_Time(QString& t, const QString& Name)
@@ -463,7 +498,7 @@ bool Verilog_Time(QString& t, const QString& Name)
     return false;
   }
 
-  t = QString::number(Time*factor);  // the space is mandatory !
+  t = QString::number(Time*factor);
   return true;
 }
 

qucs/main.h

@@ -84,6 +84,8 @@ QString properFileName(const QString&);
 bool    VHDL_Time(QString&, const QString&);
 bool    VHDL_Delay(QString&, const QString&);
 bool    Verilog_Time(QString&, const QString&);
+bool    Verilog_Delay(QString&, const QString&);
+QString Verilog_Param(const QString);
 bool    checkVersion(QString&);
 
 #endif

qucs/schematic_file.cpp

@@ -1239,12 +1239,33 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
       }
       (*tstream) << "\n";
 
+      for(pi = SymbolPaints.first(); pi != 0; pi = SymbolPaints.next())
+	if(pi->Name == ".ID ") {
+	  SubParameter *pp;
+	  ID_Text *pid = (ID_Text*)pi;
+	  if(pid->Parameter.first()) {
+	    for(pp = pid->Parameter.first(); pp != 0;) {
+	      s = pp->Name.section('=', 0,0);
+	      QString v = Verilog_Param(pp->Name.section('=', 1,1));
+	      (*tstream) << "  parameter " << s << " = " << v << ";\n";
+	      pp = pid->Parameter.next();
+	    }
+	    (*tstream) << "\n";
+	  }
+	  break;
+	}
+
       if(Signals.find("gnd") != Signals.end())
 	(*tstream) << "  assign gnd = 0;\n";  // should appear only once
 
       // write all components into netlist file
-      for(pc = DocComps.first(); pc != 0; pc = DocComps.next())
-	(*tstream) << pc->get_Verilog_Code(NumPorts);
+      for(pc = DocComps.first(); pc != 0; pc = DocComps.next()) {
+	s = pc->get_Verilog_Code(NumPorts);
+	if(s.at(0) == '§') {
+	  ErrText->insert(s.mid(1));
+	}
+	else (*tstream) << s;
+      }
 
       (*tstream) << "endmodule\n";
     } else {