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2008-01-28 Stefan Jahn <stefan@lkcc.org>

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* schematic_file.cpp: Using "std_logic" instead of "bit" as
        representation of a wire during VHDL simulations.
This commit is contained in:
ela 2008-01-28 17:21:11 +00:00
parent 9e8bebaeb0
commit 8a0049b597
18 changed files with 80 additions and 7 deletions
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5
qucs/ChangeLog
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@ -1,3 +1,8 @@
2008-01-28 Stefan Jahn <stefan@lkcc.org>
* schematic_file.cpp: Using "std_logic" instead of "bit" as
representation of a wire during VHDL simulations.
2008-01-24 Stefan Jahn <stefan@lkcc.org>
* bitmaps/Makefile.am: Added pnp_therm.png and pnpsub_therm.png

4
qucs/qucs_ca.ts
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@ -5908,6 +5908,10 @@ Use: qucsedit [-r] fitxer
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_cs.ts
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@ -6126,6 +6126,10 @@ Použití: qucsedit [-r] soubor
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_de.ts
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@ -6166,6 +6166,10 @@ Verwendung: qucsedit [-r] Datei
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_es.ts
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@ -5911,6 +5911,10 @@ Use: qucsedit [-r] archivo
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_fr.ts
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@ -5936,6 +5936,10 @@ Invocation : qucsedit [-r] fichier
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_he.ts
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@ -5783,6 +5783,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_hu.ts
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@ -5906,6 +5906,10 @@ Digitális szimuláció</translation>
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_it.ts
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@ -6078,6 +6078,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_jp.ts
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@ -5861,6 +5861,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_pl.ts
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@ -5968,6 +5968,10 @@ Stosowanie: qucsedit [-r] plik
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_pt.ts
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@ -5791,6 +5791,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsApp</name>

4
qucs/qucs_ro.ts
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@ -5867,6 +5867,10 @@ Folosire: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_ru.ts
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@ -6165,6 +6165,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_sv.ts
View File

@ -5744,6 +5744,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_tr.ts
View File

@ -5758,6 +5758,10 @@ Kullanım: qucsedit [-r] kütük
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_uk.ts
View File

@ -5766,6 +5766,10 @@ Usage: qucsedit [-r] file
<source>Base width modulation contribution</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>gate resistance</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsApp</name>

18
qucs/schematic_file.cpp
View File

@ -1010,6 +1010,11 @@ bool Schematic::createLibNetlist(QTextStream *stream, QTextEdit *ErrText,
return true;
}
//#define VHDL_SIGNAL_TYPE "bit"
//#define VHDL_LIBRARIES ""
#define VHDL_SIGNAL_TYPE "std_logic"
#define VHDL_LIBRARIES "\nlibrary ieee;\nuse ieee.std_logic_1164.all;\n"
// ---------------------------------------------------
void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
int NumPorts)
@ -1073,7 +1078,7 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
// no "break;" here !!!
default: (*it) += ": " + pc->Props.at(1)->Value;
}
(*it) += " bit";
(*it) += " " VHDL_SIGNAL_TYPE;
}
}
}
@ -1131,7 +1136,8 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
(*tstream) << "endmodule\n";
} else {
// ..... digital subcircuit ...................................
(*tstream) << "\nentity Sub_" << Type << " is\n"
(*tstream) << VHDL_LIBRARIES;
(*tstream) << "entity Sub_" << Type << " is\n"
<< " port (" << SubcircuitPorts.join(";\n ") << ");\n"
<< "end entity;\n"
<< "use work.all;\n"
@ -1139,7 +1145,7 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
<< " is\n";
if(!Signals.isEmpty())
(*tstream) << " signal " << Signals.join(",\n ")
<< " : bit;\n";
<< " : " VHDL_SIGNAL_TYPE ";\n";
(*tstream) << "begin\n";
@ -1256,9 +1262,6 @@ int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
else
stream << "--";
stream << " Qucs " << PACKAGE_VERSION << " " << DocName << "\n";
// if((allTypes & isAnalogComponent) == 0)
// stream << "library ieee;\nuse ieee.std_logic_1164.all;\n\n";
int countInit = 0; // counts the nodesets to give them unique names
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts))
@ -1270,6 +1273,7 @@ int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
if (isVerilog) {
stream << "`timescale 1ps/100fs\n";
} else {
stream << VHDL_LIBRARIES;
stream << "entity TestBench is\n"
<< "end entity;\n"
<< "use work.all;\n";
@ -1289,7 +1293,7 @@ QString Schematic::createNetlist(QTextStream& stream, int NumPorts)
} else {
stream << "architecture Arch_TestBench of TestBench is\n"
<< " signal " << Signals.join(",\n ")
<< " : bit;\n"
<< " : " VHDL_SIGNAL_TYPE ";\n"
<< "begin\n";
}