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Upload generic triac model
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Vadim Kuznetsov
parent
f842cf2d7d
commit
9ce9e0304a
@ -333,3 +333,158 @@ X1 _net0 _net1 _net2 XS8020L
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</Symbol>
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</Component>
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<Component TriacGeneric>
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<Description>
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Generic triac model from ST microelectronics. This model works only with LTSpice compatibility option:
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============================
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* Vdrm : Repetitive forward off-state voltage
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* Ih : Holding current
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* Igt : Gate trigger current
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* Rt : Dynamic on-state resistance
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* Standard : Differenciation between Snubberless and Standard TRIACs
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* (Standard=0 => Snubberless TRIACs, Standard=1 => Standard TRIACs)
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</Description>
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<Model>
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.Def:Thyristor_TriacGeneric _net0 _net1 _net2 Vdrm="400" Igt="20m" Ih="6m" Rt="0.10" Standard="1"
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Sub:X1 _net0 _net2 _net1 gnd Type="TriacST_orig_cir"
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.Def:End
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</Model>
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<ModelIncludes "TriacST_orig.cir.lst">
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<Spice>
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.subckt Triac_ST A K G PARAMS:
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+ Vdrm=400v
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+ Igt=20ma
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+ Ih=6ma
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+ Rt=0.01
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+ Standard=1
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*
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* Vdrm : Repetitive forward off-state voltage
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* Ih : Holding current
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* Igt : Gate trigger current
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* Rt : Dynamic on-state resistance
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* Standard : Differenciation between Snubberless and Standard TRIACs
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* (Standard=0 => Snubberless TRIACs, Standard=1 => Standard TRIACs)
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*
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****************************
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* Power circuit *
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****************************
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*
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****************************
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*Switch circuit*
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****************************
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* Q1 & Q2 Conduction
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S_S3 A Plip1 positive 0 Smain
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*RS_S3 positive 0 1G
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D_DAK1 Plip1 Plip2 Dak
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R_Rlip Plip1 Plip2 1k
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V_Viak Plip2 K DC 0 AC 0
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*
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* Q3 & Q4 Conduction
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S_S4 A Plin1 negative 0 Smain
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*RS_S4 negative 0 1G
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D_DKA1 Plin2 Plin1 Dak
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R_Rlin Plin1 Plin2 1k
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V_Vika K Plin2 DC 0 AC 0
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****************************
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*Gate circuit*
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****************************
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R_Rgk G K 10G
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D_DGKi Pg2 G Dgk
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D_DGKd G Pg2 Dgk
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V_Vig Pg2 K DC 0 AC 0
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R_Rlig G Pg2 1k
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*
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****************************
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*Interface circuit*
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****************************
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* positive pilot
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R_Rp Controlp positive 2.2
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C_Cp 0 positive 1u
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E_IF15OR3 Controlp 0 VALUE {IF( ( (V(CMDIG)>0.5) | (V(CMDILIH)>0.5) | (V(CMDVdrm)>0.5) ),400,0 )}
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*
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* negative pilot
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R_Rn Controln negative 2.2
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C_Cn 0 negative 1u
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E_IF14OR3 Controln 0 VALUE {IF( ( (V(CMDIG)>0.5) | (V(CMDILIHN)>0.5) | (V(CMDVdrm)>0.5) ),400,0 )}
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*
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****************************
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* Pilots circuit *
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****************************
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****************************
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* Pilot Gate *
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****************************
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E_IF1IG inIG 0 VALUE {IF( ( ABS(I(V_Vig)) ) > (Igt-1u) ,1,0 )}
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E_MULT2MULT CMDIG 0 VALUE {V(Q4)*V(inIG)}
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E_IF2Quadrant4 Q4 0 VALUE {IF(((I(V_Vig)>(Igt-0.000001))&((V(A)-V(K))<0)&(Standard==0)),0,1)}
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*
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****************************
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* Pilot IHIL *
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****************************
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*
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E_IF10IL inIL 0 VALUE {IF( ((I(V_Viak))>(Ih/2)),1,0 )}
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E_IF5IH inIH 0 VALUE {IF( ((I(V_Viak))>(Ih/3)),1,0 )}
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*
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* Flip_flop IHIL
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E_IF6DIHIL SDIHIL 0 VALUE {IF((V(inIL)*V(inIH)+V(inIH)*(1-V(inIL))*(V(CMDILIH)) )>0.5,1,0)}
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C_CIHIL CMDILIH 0 1n
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R_RIHIL SDIHIL CMDILIH 1K
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R_RIHIL2 CMDILIH 0 100Meg
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*
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****************************
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* Pilot IHILN *
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****************************
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*
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E_IF11ILn inILn 0 VALUE {IF( ((I(V_Vika))>(Ih/2)),1,0 )}
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E_IF3IHn inIHn 0 VALUE {IF( ((I(V_Vika))>(Ih/3)),1,0 )}
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* Flip_flop IHILn
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E_IF4DIHILN SDIHILN 0 VALUE {IF((V(inILn)*V(inIHn)+V(inIHn)*(1-V(inILn))*(V(CMDILIHN)) )>0.5,1,0)}
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C_CIHILn CMDILIHN 0 1n
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R_RIHILn SDIHILN CMDILIHN 1K
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R_RIHILn2 CMDILIHN 0 100Meg
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*
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****************************
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* Pilot VDRM *
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****************************
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E_IF8Vdrm inVdrm 0 VALUE {IF( (ABS(V(A)-V(K))>(Vdrm*1.3)),1,0 )}
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E_IF9IHVDRM inIhVdrm 0 VALUE {IF( (I(V_Viak)>(Vdrm*1.3)/1.2meg)| (I(V_Vika)>(Vdrm*1.3)/1.2meg),1,0)}
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* Flip_flop VDRM
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E_IF7DVDRM SDVDRM 0 VALUE {IF((V(inVdrm)+(1-V(inVdrm))*V(inIhVdrm)*V(CMDVdrm) )>0.5,1,0)}
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C_CVdrm CMDVdrm 0 1n
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R_RVdrm SDVDRM CMDVdrm 100
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R_RVdrm2 CMDVdrm 0 100Meg
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*
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****************************
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* Switch Model *
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****************************
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.MODEL Smain VSWITCH Roff=1.2meg Ron={Rt} Voff=0 Von=100
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****************
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* Diodes Model *
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****************
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.MODEL Dak D( Is=3E-12 Cjo=5pf)
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.MODEL Dgk D( Is=1E-16 Cjo=50pf Rs=5)
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.ends
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.SUBCKT Thyristor_TriacGeneric gnd _net0 _net1 _net2 Vdrm=400 Igt=20m Ih=6m Rt=0.10 Standard=1
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X1 _net0 _net2 _net1 Triac_ST Vdrm={Vdrm} Igt={Igt} Ih={Ih} Rt={Rt} Standard={Standard}
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.ENDS
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</Spice>
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<Symbol>
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<.ID -20 44 SUB "1=Vdrm=400=Repetitive forward off-state voltage=" "1=Igt=20m=Gate trigger current =" "1=Ih=6m=Holding current =" "1=Rt=0.10=Dynamic on-state resistance=" "1=Standard=1=0 -- Snubberless TRIACs;1 -- Standard TRIACs=">
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<.PortSym 0 -30 1 0 P1>
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<Line 0 6 0 24 #000080 2 1>
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<Line 0 -30 0 24 #000080 2 1>
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<Line 18 6 -36 0 #000080 2 1>
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<Line -30 10 17 0 #000080 2 1>
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<Line -13 10 4 -4 #000080 2 1>
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<Line -9 6 -9 -12 #000080 2 1>
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<Line -9 6 9 -12 #000080 2 1>
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<Line 9 -6 9 12 #000080 2 1>
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<Line 9 -6 -9 12 #000080 2 1>
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<Line 18 -6 -36 0 #000080 2 1>
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<.PortSym 0 30 3 0 P3>
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<.PortSym -30 10 2 0 P2>
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</Symbol>
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</Component>
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