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Added capacitor model

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This commit is contained in:
Vadim Kuznetzov 2015-07-21 14:39:00 +03:00
parent 105ba9d493
commit a70e98c1dc
2 changed files with 9 additions and 0 deletions
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8
qucs/components/capacitor.cpp
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@ -19,6 +19,7 @@
#include "node.h"
#include "misc.h"
#include "extsimkernels/spicecompat.h"
#include "extsimkernels/verilogawriter.h"
Capacitor::Capacitor()
@ -72,6 +73,13 @@ QString Capacitor::spice_netlist(bool)
return s+'\n';
}
QString Capacitor::va_code()
{
QString val = vacompat::normalize_value(Props.at(0)->Value);
return QString("I(%1,%2) <+ ddt(V(%1,%2)*(%3));\n").arg(Ports.at(0)->Connection->Name)
.arg(Ports.at(1)->Connection->Name).arg(val);
}
void Capacitor::createSymbol()
{
if(Props.getLast()->Value.at(0) == 'n') {

1
qucs/components/capacitor.h
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@ -31,6 +31,7 @@ public:
protected:
void createSymbol();
QString spice_netlist(bool isXyce = false);
QString va_code();
};
#endif