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Added 555 timer model from Clyde #252
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Vadim Kuznetsov
parent
0f39840d0d
commit
adf319610a
@ -655,3 +655,154 @@ X1 _net0 _net1 _net5 _net2 _net6 _net3 _net7 _net4 NE555
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</Symbol>
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</Component>
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<Component 555_XSPICE>
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<Description>
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Behavioral 555 timer model developed by Clyde from Ngspice forum. See https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/f535c0f1b9/ for more details.
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</Description>
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<Model>
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.Def:n555timer_555_XSPICE _net0 _net1 _net5 _net2 _net6 _net3 _net7 _net4
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Sub:X1 _net0 _net1 _net5 _net2 _net6 _net3 _net7 _net4 gnd Type="n555_cir"
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.Def:End
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</Model>
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<ModelIncludes "555.cir.lst">
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<Spice>* Qucs 1.0.1 555timer_555_XSPICE.sch
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* 555 Timer behavioral model -- 555.cir
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* 3/31/23 created by Clyde R. Shappee
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* https://sourceforge.net/p/ngspice/discussion/ngspice-tips/thread/f535c0f1b9/
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* Version 2 using generic OpAmp model from the forum.
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* Now supports output voltage set by Vcc Pin.
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* This is mostly a timing model and may not be DC
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* accurate in all cases.
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*
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* Ground
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* | Trigger
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* | | Output
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* | | | Reset
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* | | | | Control
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* | | | | | Threshold
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* | | | | | | Discharge
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* | | | | | | | Vcc
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* | | | | | | | |
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.subckt 555xspice 1 2 3 4 5 6 7 8
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R1 8 5 5000
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R2 5 10 5000
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R3 10 1 5000
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X1 6 5 22 comparator5 ; the reset comparator
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X2 10 2 21 comparator5 ; the set comparator
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a0 z1 pulldown1 ; pull-down for unused clock and data
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* data clock set reset q qbar
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a1 z1 z1 21 25 23 24 flop1 ; the flip flop
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abridge1 [24] [13] dac1 ; bridge qbar to discharge timing cap, turn on Q1
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abridge2 [24] [26] dac1 ; bridge qbar to pseudo tristate driver
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Q1 7 13 1 N ; the discharge transistor
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* Here is the active low master reset function from pin 4.
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abridge3 [4] [30] adc_buff ; bridge pin 4 to the digital domain
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a2 30 31 inv1
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a3 [22 31] 25 or1 ; Reset when the external resit is assered or the comparitor trips.
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*
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* Make the Q output of the flip-flop drive to Vcc when driven
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*
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R4 3 8 100
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Q2 3 26 0 N
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*
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* Models
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*
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.model adc_buff adc_bridge(in_low = 0.7 in_high = 3.0) ; 0.7 V threshold per NE555 data sheet
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.model flop1 d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9
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+ reset_delay = 27.0e-9 ic = 0 rise_delay = 10.0e-9
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+ fall_delay = 3e-9)
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.model pulldown1 d_pulldown(load = 20.0e-12)
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.model dac1 dac_bridge(out_low = 0.1 out_high = 1.0 out_undef = 2.2
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+ input_load = 5.0e-12 t_rise = 50e-9
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+ t_fall = 20e-9)
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.model N NPN
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.model inv1 d_inverter(rise_delay = 0.5e-9 fall_delay = 0.3e-9
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+ input_load = 0.5e-12)
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.model or1 d_or(rise_delay = 0.5e-9 fall_delay = 0.3e-9
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+ input_load = 0.5e-12)
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.ends
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* Simple comparitor with logic output
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*
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.subckt comparator5 1 2 5
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a0 [1 2] 3 sum1
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a1 3 4 limit5
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a2 [4][5] adc_buff
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*
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* Models
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*
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.model adc_buff adc_bridge(in_low = 0.1 in_high = 1.0)
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.model sum1 summer(in_gain=[1.0 -1.0] out_gain=1E6)
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.model limit5 limit(out_lower_limit=-5.0 out_upper_limit=5.0 limit_range=0.10 fraction=FALSE)
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.ends
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.SUBCKT n555_timer_555_XSPICE gnd _net0 _net1 _net5 _net2 _net6 _net3 _net7 _net4
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X1 _net0 _net1 _net5 _net2 _net6 _net3 _net7 _net4 555xspice
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.ENDS
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</Spice>
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<SpiceAttach >
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<Symbol>
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<Rectangle -60 -100 120 200 #000000 1 1 #c0c0c0 1 0>
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<Line 0 100 0 20 #000000 2 1>
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<.ID 70 -96 SUB>
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<Line -20 -120 0 20 #000000 2 1>
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<Line -60 -60 -20 0 #000000 2 1>
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<Line 60 0 20 0 #000000 2 1>
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<Line -60 20 -20 0 #000000 2 1>
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<Line -60 60 -20 0 #000000 2 1>
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<Line 80 60 -20 0 #000000 2 1>
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<Text -55 -70 12 #000000 0 "DIS">
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<Text -55 10 12 #000000 0 "THR">
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<Text -55 50 12 #000000 0 "TRG">
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<Text 30 50 12 #000000 0 "CTL">
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<Text 25 -10 12 #000000 0 "OUT">
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<Text -15 80 12 #000000 0 "GND">
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<Text 5 -100 12 #000000 0 "VCC">
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<Text -35 -100 12 #000000 0 "RST">
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<Line 20 -120 0 20 #000000 2 1>
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<Text -75 40 12 #000000 0 "2">
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<Text 5 100 12 #000000 0 "1">
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<Text 65 -20 12 #000000 0 "3">
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<Text -35 -120 12 #000000 0 "4">
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<Text 25 -120 12 #000000 0 "8">
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<Text -75 -80 12 #000000 0 "7">
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<Text -75 0 12 #000000 0 "6">
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<Text 65 40 12 #000000 0 "5">
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<.PortSym -20 -120 4 0>
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<.PortSym 0 120 1 0>
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<.PortSym -80 60 2 0>
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<.PortSym 80 0 3 180>
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<.PortSym -80 20 6 0>
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<.PortSym 20 -120 8 180>
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<.PortSym 80 60 5 180>
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<.PortSym -80 -60 7 0>
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<Text -40 -40 12 #000000 0 "555 Xspice">
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</Symbol>
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</Component>
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