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Merge pull request #189 from yodalee/add-namespace-to-misc

Browse Source 
add namespace misc to misc.h
This commit is contained in:
YodaLee 2015-01-19 08:14:20 +08:00
commit d4a321ab7e
54 changed files with 198 additions and 196 deletions
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4
qucs/components/andor4x2.cpp
View File

@ -108,7 +108,7 @@ QString andor4x2::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString a11 = Ports.at(0)->Connection->Name;
@ -133,7 +133,7 @@ QString andor4x2::vhdlCode( int )
QString andor4x2::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/andor4x3.cpp
View File

@ -122,7 +122,7 @@ QString andor4x3::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString a11 = Ports.at(0)->Connection->Name;
@ -156,7 +156,7 @@ QString andor4x3::vhdlCode( int )
QString andor4x3::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/andor4x4.cpp
View File

@ -129,7 +129,7 @@ QString andor4x4::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString a11 = Ports.at(0)->Connection->Name;
@ -168,7 +168,7 @@ QString andor4x4::vhdlCode( int )
QString andor4x4::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString a11 = Ports.at(0)->Connection->Name;
QString a12 = Ports.at(1)->Connection->Name;

4
qucs/components/binarytogrey4bit.cpp
View File

@ -104,7 +104,7 @@ QString binarytogrey4bit::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString B0 = Ports.at(0)->Connection->Name;
@ -130,7 +130,7 @@ QString binarytogrey4bit::vhdlCode( int )
QString binarytogrey4bit::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString B0 = Ports.at(0)->Connection->Name;
QString B1 = Ports.at(1)->Connection->Name;

4
qucs/components/comp_1bit.cpp
View File

@ -90,7 +90,7 @@ QString comp_1bit::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString X = Ports.at(0)->Connection->Name;
@ -113,7 +113,7 @@ QString comp_1bit::verilogCode( int )
QString l="";
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString X = Ports.at(0)->Connection->Name;
QString Y = Ports.at(1)->Connection->Name;

4
qucs/components/comp_2bit.cpp
View File

@ -100,7 +100,7 @@ QString comp_2bit::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString X0 = Ports.at(0)->Connection->Name;
@ -125,7 +125,7 @@ QString comp_2bit::verilogCode( int )
QString l="";
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString X0 = Ports.at(0)->Connection->Name;
QString X1 = Ports.at(1)->Connection->Name;

4
qucs/components/comp_4bit.cpp
View File

@ -112,7 +112,7 @@ QString comp_4bit::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString X0 = Ports.at(0)->Connection->Name;
@ -154,7 +154,7 @@ QString comp_4bit::verilogCode( int )
QString l="";
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString X0 = Ports.at(0)->Connection->Name;
QString X1 = Ports.at(1)->Connection->Name;

8
qucs/components/component.cpp
View File

@ -1079,7 +1079,7 @@ int Component::analyseLine(const QString& Row, int numProps)
s = Row.mid(Row.indexOf('"')+1); // Text (can contain " !!!)
s = s.left(s.length()-1);
if(s.isEmpty()) return -1;
convert2Unicode(s);
misc::convert2Unicode(s);
Texts.append(new Text(i1, i2, s, Color, float(i3),
float(cos(float(i4)*M_PI/180.0)),
@ -1368,7 +1368,7 @@ QString GateComponent::vhdlCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td;
if(!misc::VHDL_Delay(td, Name)) return td;
s += td;
}
@ -1399,7 +1399,7 @@ QString GateComponent::verilogCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td;
if(!misc::Verilog_Delay(td, Name)) return td;
s += td;
}
s += " " + pp->Connection->Name + " = "; // output port
@ -1422,7 +1422,7 @@ QString GateComponent::verilogCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td;
if(!misc::Verilog_Delay(td, Name)) return td;
s += td;
}
s += " " + Name + " (" + pp->Connection->Name; // output port

24
qucs/components/componentdialog.cpp
View File

@ -1214,9 +1214,9 @@ void ComponentDialog::slotNumberChanged(const QString&)
QString Unit, tmp;
double x, y, Factor;
if(comboType->currentIndex() == 1) { // logarithmic ?
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;
if(y == 0.0) y = x / 10.0;
if(x == 0.0) x = y * 10.0;
@ -1225,15 +1225,15 @@ void ComponentDialog::slotNumberChanged(const QString&)
Unit = QString::number(x);
}
else {
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;
x = (x - y) / (editNumber->text().toDouble() - 1.0);
QString step = num2str(x);
QString step = misc::num2str(x);
str2num(step, x, Unit, Factor);
misc::str2num(step, x, Unit, Factor);
if(Factor == 1.0)
Unit = "";
@ -1251,25 +1251,25 @@ void ComponentDialog::slotStepChanged(const QString& Step)
QString Unit;
double x, y, Factor;
if(comboType->currentIndex() == 1) { // logarithmic ?
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;
x /= y;
str2num(Step, y, Unit, Factor);
misc::str2num(Step, y, Unit, Factor);
y *= Factor;
x = log10(fabs(x)) * y;
}
else {
str2num(editStop->text(), x, Unit, Factor);
misc::str2num(editStop->text(), x, Unit, Factor);
x *= Factor;
str2num(editStart->text(), y, Unit, Factor);
misc::str2num(editStart->text(), y, Unit, Factor);
y *= Factor;
x -= y;
str2num(Step, y, Unit, Factor);
misc::str2num(Step, y, Unit, Factor);
y *= Factor;
x /= y;

4
qucs/components/d_flipflop.cpp
View File

@ -60,7 +60,7 @@ QString D_FlipFlop::vhdlCode(int NumPorts)
QString s = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
s += td;
}
s += ";\n";
@ -83,7 +83,7 @@ QString D_FlipFlop::verilogCode(int NumPorts)
QString t = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!td.isEmpty()) t = " " + td + ";\n";
}

4
qucs/components/dff_SR.cpp
View File

@ -101,7 +101,7 @@ QString dff_SR::vhdlCode( int )
QString s="";
QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString S = Ports.at(0)->Connection->Name;
@ -130,7 +130,7 @@ QString dff_SR::vhdlCode( int )
QString dff_SR::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/digi_source.cpp
View File

@ -119,7 +119,7 @@ QString Digi_Source::vhdlCode(int NumPorts)
while(!t.isEmpty()) {
s += Out + State + "';"; // next value for signal
if(!VHDL_Delay(t, Name))
if(!misc::VHDL_Delay(t, Name))
return t; // time has not VHDL format
s += t.replace("after","wait for") + ";\n";
@ -165,7 +165,7 @@ QString Digi_Source::verilogCode(int NumPorts)
t = Props.next()->Value.section(';',z,z).trimmed();
while(!t.isEmpty()) {
if(!Verilog_Delay(t, Name))
if(!misc::Verilog_Delay(t, Name))
return t; // time has not VHDL format
s += " " + r + " = " + State + ";\n";
s += " " + t + ";\n";

4
qucs/components/dmux2to4.cpp
View File

@ -106,7 +106,7 @@ QString dmux2to4::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString En = Ports.at(0)->Connection->Name;
@ -130,7 +130,7 @@ QString dmux2to4::vhdlCode( int )
QString dmux2to4::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/dmux3to8.cpp
View File

@ -122,7 +122,7 @@ QString dmux3to8::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString En = Ports.at(0)->Connection->Name;
@ -155,7 +155,7 @@ QString dmux3to8::vhdlCode( int )
QString dmux3to8::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/dmux4to16.cpp
View File

@ -147,7 +147,7 @@ QString dmux4to16::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString En = Ports.at(0)->Connection->Name;
@ -198,7 +198,7 @@ QString dmux4to16::vhdlCode( int )
QString dmux4to16::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/fa1b.cpp
View File

@ -90,7 +90,7 @@ QString fa1b::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString A = Ports.at(0)->Connection->Name;
@ -110,7 +110,7 @@ QString fa1b::vhdlCode( int )
QString fa1b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/fa2b.cpp
View File

@ -109,7 +109,7 @@ QString fa2b::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString D = Ports.at(0)->Connection->Name;
@ -133,7 +133,7 @@ QString fa2b::vhdlCode( int )
QString fa2b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/gatedDlatch.cpp
View File

@ -90,7 +90,7 @@ QString gatedDlatch::vhdlCode( int )
QString s="";
QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString D = Ports.at(0)->Connection->Name;
@ -111,7 +111,7 @@ QString gatedDlatch::vhdlCode( int )
QString gatedDlatch::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/greytobinary4bit.cpp
View File

@ -104,7 +104,7 @@ QString greytobinary4bit::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString G0 = Ports.at(0)->Connection->Name;
@ -129,7 +129,7 @@ QString greytobinary4bit::vhdlCode( int )
QString greytobinary4bit::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString G0 = Ports.at(0)->Connection->Name;
QString G1 = Ports.at(1)->Connection->Name;

4
qucs/components/ha1b.cpp
View File

@ -87,7 +87,7 @@ QString ha1b::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString A = Ports.at(0)->Connection->Name;
@ -106,7 +106,7 @@ QString ha1b::vhdlCode( int )
QString ha1b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/hpribin4bit.cpp
View File

@ -97,7 +97,7 @@ QString hpribin4bit::vhdlCode( int )
QString s;
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString A = Ports.at(0)->Connection->Name;
@ -120,7 +120,7 @@ QString hpribin4bit::vhdlCode( int )
QString hpribin4bit::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

2
qucs/components/ifile.cpp
View File

@ -84,7 +84,7 @@ QString iFile::getSubcircuitFile()
{
// construct full filename
QString FileName = Props.getFirst()->Value;
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
// -------------------------------------------------------

4
qucs/components/jk_flipflop.cpp
View File

@ -72,7 +72,7 @@ QString JK_FlipFlop::vhdlCode(int NumPorts)
QString s = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
s += td;
}
s += ";\n";
@ -104,7 +104,7 @@ QString JK_FlipFlop::verilogCode(int NumPorts)
QString t = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!td.isEmpty()) t = " " + td + ";\n";
}

4
qucs/components/jkff_SR.cpp
View File

@ -105,7 +105,7 @@ QString jkff_SR::vhdlCode( int )
QString s="";
QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString S = Ports.at(0)->Connection->Name;
@ -136,7 +136,7 @@ QString jkff_SR::vhdlCode( int )
QString jkff_SR::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

8
qucs/components/libcomp.cpp
View File

@ -101,7 +101,7 @@ int LibComp::loadSection(const QString& Name, QString& Section,
int Start, End = Section.indexOf(' ', 14);
if(End < 15) return -3;
QString Line = Section.mid(14, End-14);
if(!checkVersion(Line)) // wrong version number ?
if(!misc::checkVersion(Line)) // wrong version number ?
return -3;
if(Name == "Symbol") {
@ -214,7 +214,7 @@ QString LibComp::getSubcircuitFile()
{
QDir Directory(QucsSettings.LibDir);
QString FileName = Directory.absFilePath(Props.first()->Value);
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
// -------------------------------------------------------
@ -261,8 +261,8 @@ bool LibComp::createSubNetlist(QTextStream *stream, QStringList &FileList,
// -------------------------------------------------------
QString LibComp::createType()
{
QString Type = properFileName(Props.first()->Value);
return properName(Type + "_" + Props.next()->Value);
QString Type = misc::properFileName(Props.first()->Value);
return misc::properName(Type + "_" + Props.next()->Value);
}
// -------------------------------------------------------

4
qucs/components/logical_buf.cpp
View File

@ -52,7 +52,7 @@ QString Logical_Buf::vhdlCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!VHDL_Delay(td, Name)) return td;
if(!misc::VHDL_Delay(td, Name)) return td;
s += td;
}
@ -72,7 +72,7 @@ QString Logical_Buf::verilogCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name)) return td;
if(!misc::Verilog_Delay(td, Name)) return td;
s += td;
}
s += " ";

6
qucs/components/logical_inv.cpp
View File

@ -52,7 +52,7 @@ QString Logical_Inv::vhdlCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!VHDL_Delay(td, Name)) return td;
if(!misc::VHDL_Delay(td, Name)) return td;
s += td;
}
@ -72,7 +72,7 @@ QString Logical_Inv::verilogCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name)) return td;
if(!misc::Verilog_Delay(td, Name)) return td;
s += td;
}
s += " ";
@ -86,7 +86,7 @@ QString Logical_Inv::verilogCode(int NumPorts)
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name))
if(!misc::Verilog_Delay(td, Name))
return td; // time has not VHDL format
s += td;
}

4
qucs/components/mux2to1.cpp
View File

@ -101,7 +101,7 @@ QString mux2to1::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value;
if(!VHDL_Delay(td, Name))
if(!misc::VHDL_Delay(td, Name))
return td; // Time does not have VHDL format.
td += ";\n";
@ -122,7 +122,7 @@ QString mux2to1::vhdlCode( int )
QString mux2to1::verilogCode( int )
{
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name))
if(!misc::Verilog_Delay(td, Name))
return td; // Time does not have VHDL format.
td += " ";

4
qucs/components/mux4to1.cpp
View File

@ -109,7 +109,7 @@ QString mux4to1::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString En = Ports.at(0)->Connection->Name;
@ -135,7 +135,7 @@ QString mux4to1::vhdlCode( int )
QString mux4to1::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/mux8to1.cpp
View File

@ -123,7 +123,7 @@ QString mux8to1::vhdlCode( int )
QString s="";
QString td = Props.at(1)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString En = Ports.at(0)->Connection->Name;
@ -159,7 +159,7 @@ QString mux8to1::vhdlCode( int )
QString mux8to1::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

4
qucs/components/rs_flipflop.cpp
View File

@ -60,7 +60,7 @@ QString RS_FlipFlop::vhdlCode(int NumPorts)
QString s = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
s = td;
}
s += ";\n";
@ -81,7 +81,7 @@ QString RS_FlipFlop::verilogCode(int NumPorts)
QString t = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time has not VHDL format
t = td;
}
t += " ";

2
qucs/components/sparamfile.cpp
View File

@ -103,7 +103,7 @@ QString SParamFile::getSubcircuitFile()
{
// construct full filename
QString FileName = Props.getFirst()->Value;
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
// -------------------------------------------------------

14
qucs/components/spicefile.cpp
View File

@ -157,8 +157,8 @@ QString SpiceFile::netlist()
foreach(Port *pp, Ports)
s += " "+pp->Connection->Name; // output all node names
QString f = properFileName(Props.first()->Value);
s += " Type=\""+properName(f)+"\"\n";
QString f = misc::properFileName(Props.first()->Value);
s += " Type=\""+misc::properName(f)+"\"\n";
return s;
}
@ -170,7 +170,7 @@ QString SpiceFile::getSubcircuitFile()
if (FileName.isEmpty())
{
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
QFileInfo FileInfo(FileName);
@ -224,7 +224,7 @@ QString SpiceFile::getSubcircuitFile()
{
// the schematic was not found in the hash table, return
// what would always have been returned in this case
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
else
{
@ -240,7 +240,7 @@ QString SpiceFile::getSubcircuitFile()
{
// the schematic file does not actually exist, return
// what would always have been returned in this case
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
}
@ -419,8 +419,8 @@ bool SpiceFile::recreateSubNetlist(QString *SpiceFile, QString *FileName)
// begin netlist text creation
if(makeSubcircuit) {
QString f = properFileName(*FileName);
NetText += "\n.Def:" + properName(f) + " ";
QString f = misc::properFileName(*FileName);
NetText += "\n.Def:" + misc::properName(f) + " ";
QString PortNames = Props.at(1)->Value;
PortNames.replace(',', ' ');
NetText += PortNames;

24
qucs/components/subcircuit.cpp
View File

@ -162,7 +162,7 @@ int Subcircuit::loadSymbol(const QString& DocName)
return -3;
Line = Line.mid(16, Line.length()-17);
if(!checkVersion(Line)) // wrong version number ?
if(!misc::checkVersion(Line)) // wrong version number ?
return -4;
// read content *************************
@ -207,8 +207,8 @@ QString Subcircuit::netlist()
s += " "+p1->Connection->Name; // node names
// type for subcircuit
QString f = properFileName(Props.first()->Value);
s += " Type=\""+properName(f)+"\"";
QString f = misc::properFileName(Props.first()->Value);
s += " Type=\""+misc::properName(f)+"\"";
// output all user defined properties
for(Property *pp = Props.next(); pp != 0; pp = Props.next())
@ -219,8 +219,8 @@ QString Subcircuit::netlist()
// -------------------------------------------------------
QString Subcircuit::vhdlCode(int)
{
QString f = properFileName(Props.first()->Value);
QString s = " " + Name + ": entity Sub_" + properName(f);
QString f = misc::properFileName(Props.first()->Value);
QString s = " " + Name + ": entity Sub_" + misc::properName(f);
// output all user defined properties
Property *pr = Props.next();
@ -250,16 +250,16 @@ QString Subcircuit::vhdlCode(int)
// -------------------------------------------------------
QString Subcircuit::verilogCode(int)
{
QString f = properFileName(Props.first()->Value);
QString s = " Sub_" + properName(f);
QString f = misc::properFileName(Props.first()->Value);
QString s = " Sub_" + misc::properName(f);
// output all user defined properties
Property *pr = Props.next();
if (pr) {
s += " #(";
s += Verilog_Param(pr->Value);
s += misc::Verilog_Param(pr->Value);
for(pr = Props.next(); pr != 0; pr = Props.next())
s += ", " + Verilog_Param(pr->Value);
s += ", " + misc::Verilog_Param(pr->Value);
s += ")";
}
@ -286,7 +286,7 @@ QString Subcircuit::getSubcircuitFile()
if (FileName.isEmpty())
{
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
QFileInfo FileInfo(FileName);
@ -335,7 +335,7 @@ QString Subcircuit::getSubcircuitFile()
{
// the schematic was not found in the hash table, return
// what would always have been returned in this case
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
else
{
@ -351,7 +351,7 @@ QString Subcircuit::getSubcircuitFile()
{
// the schematic file does not actually exist, return
// what would always have been returned in this case
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
}

4
qucs/components/tff_SR.cpp
View File

@ -101,7 +101,7 @@ QString tff_SR::vhdlCode( int )
QString s="";
QString td = Props.at(2)->Value; // delay time
if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
td += ";\n";
QString S = Ports.at(0)->Connection->Name;
@ -131,7 +131,7 @@ QString tff_SR::vhdlCode( int )
QString tff_SR::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";

2
qucs/components/verilogfile.cpp
View File

@ -164,7 +164,7 @@ QString Verilog_File::getSubcircuitFile()
{
// construct full filename
QString FileName = Props.getFirst()->Value;
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
// -------------------------------------------------------

2
qucs/components/vfile.cpp
View File

@ -86,7 +86,7 @@ QString vFile::getSubcircuitFile()
{
// construct full filename
QString FileName = Props.getFirst()->Value;
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
// -------------------------------------------------------

2
qucs/components/vhdlfile.cpp
View File

@ -207,7 +207,7 @@ QString VHDL_File::getSubcircuitFile()
{
// construct full filename
QString FileName = Props.getFirst()->Value;
return properAbsFileName(FileName);
return misc::properAbsFileName(FileName);
}
// -------------------------------------------------------

4
qucs/diagrams/curvediagram.cpp
View File

@ -157,7 +157,7 @@ if(xAxis.log) {
Lines.prepend(new Line(z, y2, z, 0, GridPen)); // x grid
if((zD < 1.5*zDstep) || (z == 0) || (z == x2)) {
tmp = StringNiceNum(zD);
tmp = misc::StringNiceNum(zD);
if(xAxis.up < 0.0) tmp = '-'+tmp;
w = metrics.width(tmp); // width of text
// center text horizontally under the x tick mark
@ -186,7 +186,7 @@ else { // not logarithmical
z = int(zD); // "int(...)" implies "floor(...)"
while((z <= x2) && (z >= 0)) { // create all grid lines
if(fabs(GridNum) < 0.01*pow(10.0, Expo)) GridNum = 0.0;// make 0 really 0
tmp = StringNiceNum(GridNum);
tmp = misc::StringNiceNum(GridNum);
w = metrics.width(tmp); // width of text
// center text horizontally under the x tick mark
Texts.append(new Text(z-(w>>1), -y1, tmp)); // Text(x, y, str, ...)

10
qucs/diagrams/diagram.cpp
View File

@ -1551,7 +1551,7 @@ void Diagram::createSmithChart(Axis *Axis, int Mode)
if(Below) y = 4;
else y = y2-4-QucsSettings.font.pointSize();
Texts.append(new Text(0, y, StringNum(Axis->up)));
Texts.append(new Text(0, y, misc::StringNum(Axis->up)));
}
}
@ -1632,7 +1632,7 @@ void Diagram::createPolarDiagram(Axis *Axis, int Mode)
for(i=int(numGrids); i>1; i--) { // create all grid circles
z = int(zD);
GridNum += GridStep;
Texts.append(new Text(((x2+z)>>1)-10, tPos, StringNiceNum(GridNum)));
Texts.append(new Text(((x2+z)>>1)-10, tPos, misc::StringNiceNum(GridNum)));
phi = int(16.0*180.0/M_PI*atan(double(2*tHeight)/zD));
if(!Below) tmp = beta + phi;
@ -1649,7 +1649,7 @@ void Diagram::createPolarDiagram(Axis *Axis, int Mode)
}
// create outer circle
Texts.append(new Text(x2-8, tPos, StringNiceNum(Axis->up)));
Texts.append(new Text(x2-8, tPos, misc::StringNiceNum(Axis->up)));
phi = int(16.0*180.0/M_PI*atan(double(2*tHeight)/double(x2)));
if(!Below) tmp = phi;
else tmp = 0;
@ -1911,7 +1911,7 @@ if(Axis->log) {
Lines.prepend(new Line(0, z, x2, z, GridPen)); // y grid
if((zD < 1.5*zDstep) || (z == 0)) {
tmp = StringNiceNum(zD);
tmp = misc::StringNiceNum(zD);
if(Axis->up < 0.0) tmp = '-'+tmp;
w = metrics.width(tmp); // width of text
@ -1946,7 +1946,7 @@ else { // not logarithmical
z = int(zD); // "int(...)" implies "floor(...)"
while((z <= y2) && (z >= 0)) { // create all grid lines
if(fabs(GridNum) < 0.01*pow(10.0, Expo)) GridNum = 0.0;// make 0 really 0
tmp = StringNiceNum(GridNum);
tmp = misc::StringNiceNum(GridNum);
w = metrics.width(tmp); // width of text
if(maxWidth < w) maxWidth = w;

20
qucs/diagrams/marker.cpp
View File

@ -142,11 +142,11 @@ void Marker::initText(int n)
pz = pGraph->cPointsY + 2*n;
Text += pGraph->Var + ": ";
switch(numMode) {
case 0: Text += complexRect(*pz, *(pz+1), Precision);
case 0: Text += misc::complexRect(*pz, *(pz+1), Precision);
break;
case 1: Text += complexDeg(*pz, *(pz+1), Precision);
case 1: Text += misc::complexDeg(*pz, *(pz+1), Precision);
break;
case 2: Text += complexRad(*pz, *(pz+1), Precision);
case 2: Text += misc::complexRad(*pz, *(pz+1), Precision);
break;
}
VarPos[nVarPos] = *pz;
@ -160,9 +160,9 @@ void Marker::initText(int n)
MatchDialog::r2z(Zr, Zi, Z0);
QString Var = pGraph->Var;
if(Var.startsWith("S"))
Text += "\n"+ Var.replace('S', 'Z')+": " +complexRect(Zr, Zi, Precision);
Text += "\n"+ Var.replace('S', 'Z')+": " +misc::complexRect(Zr, Zi, Precision);
else
Text += "\nZ("+ Var+"): " +complexRect(Zr, Zi, Precision);
Text += "\nZ("+ Var+"): " +misc::complexRect(Zr, Zi, Precision);
}
px = VarPos;
if(py != &Dummy) // 2D in 3D diagram ?
@ -230,11 +230,11 @@ void Marker::createText()
Text += pGraph->Var + ": ";
switch(numMode) {
case 0: Text += complexRect(*pz, *(pz+1), Precision);
case 0: Text += misc::complexRect(*pz, *(pz+1), Precision);
break;
case 1: Text += complexDeg(*pz, *(pz+1), Precision);
case 1: Text += misc::complexDeg(*pz, *(pz+1), Precision);
break;
case 2: Text += complexRad(*pz, *(pz+1), Precision);
case 2: Text += misc::complexRad(*pz, *(pz+1), Precision);
break;
}
if(Diag->Name=="Smith") //impedance is useful as well here
@ -246,9 +246,9 @@ void Marker::createText()
MatchDialog::r2z(Zr, Zi, Z0);
QString Var = pGraph->Var;
if(Var.startsWith("S"))
Text += "\n"+ Var.replace('S', 'Z')+": " +complexRect(Zr, Zi, Precision);
Text += "\n"+ Var.replace('S', 'Z')+": " +misc::complexRect(Zr, Zi, Precision);
else
Text += "\nZ("+ Var+"): " +complexRect(Zr, Zi, Precision);
Text += "\nZ("+ Var+"): " +misc::complexRect(Zr, Zi, Precision);
}
VarPos[nVarPos] = *pz;
VarPos[nVarPos+1] = *(pz+1);

4
qucs/diagrams/rect3ddiagram.cpp
View File

@ -662,7 +662,7 @@ int Rect3DDiagram::calcAxis(Axis *Axis, int x, int y,
ystepD = corr * log10(yD / fabs(Axis->low));
while(ystepD <= xD) { // create all grid lines
tmp = StringNiceNum(yD);
tmp = misc::StringNiceNum(yD);
if(Axis->up < 0.0) tmp = '-'+tmp;
w = metrics.width(tmp); // width of text
if(maxWidth < w) maxWidth = w;
@ -698,7 +698,7 @@ int Rect3DDiagram::calcAxis(Axis *Axis, int x, int y,
x = int(xD);
y = int(yD);
if(fabs(GridNum) < 0.01*pow(10.0, Expo)) GridNum = 0.0; // make 0 really 0
tmp = StringNiceNum(GridNum);
tmp = misc::StringNiceNum(GridNum);
w = metrics.width(tmp); // width of text
if(maxWidth < w) maxWidth = w;

4
qucs/diagrams/rectdiagram.cpp
View File

@ -166,7 +166,7 @@ if(xAxis.log) {
Lines.prepend(new Line(z, y2, z, 0, GridPen)); // x grid
if((zD < 1.5*zDstep) || (z == 0) || (z == x2)) {
tmp = StringNiceNum(zD);
tmp = misc::StringNiceNum(zD);
if(xAxis.up < 0.0) tmp = '-'+tmp;
w = metrics.width(tmp); // width of text
// center text horizontally under the x tick mark
@ -195,7 +195,7 @@ else { // not logarithmical
z = int(zD); // "int(...)" implies "floor(...)"
while((z <= x2) && (z >= 0)) { // create all grid lines
if(fabs(GridNum) < 0.01*pow(10.0, Expo)) GridNum = 0.0;// make 0 really 0
tmp = StringNiceNum(GridNum);
tmp = misc::StringNiceNum(GridNum);
w = metrics.width(tmp); // width of text
// center text horizontally under the x tick mark
Texts.append(new Text(z-(w>>1), -y1, tmp)); // Text(x, y, str, ...)

8
qucs/diagrams/tabdiagram.cpp
View File

@ -211,7 +211,7 @@ int TabDiagram::calcDiagram()
y += tHeight*startWriting;
startWriting = 0;
if(y < tHeight) break; // no room for more rows ?
Str = StringNum(*px, 'g', g->Precision);
Str = misc::StringNum(*px, 'g', g->Precision);
colWidth = checkColumnWidth(Str, metrics, colWidth, x, y);
if(colWidth < 0) goto funcEnd;
@ -267,9 +267,9 @@ int TabDiagram::calcDiagram()
if(startWriting-- > 0) continue; // reached visible area ?
if(y < tHeight) break; // no room for more rows ?
switch(g->numMode) {
case 0: Str = complexRect(*py, *(py+1), g->Precision); break;
case 1: Str = complexDeg (*py, *(py+1), g->Precision); break;
case 2: Str = complexRad (*py, *(py+1), g->Precision); break;
case 0: Str = misc::complexRect(*py, *(py+1), g->Precision); break;
case 1: Str = misc::complexDeg (*py, *(py+1), g->Precision); break;
case 2: Str = misc::complexRad (*py, *(py+1), g->Precision); break;
}
colWidth = checkColumnWidth(Str, metrics, colWidth, x, y);

2
qucs/diagrams/timingdiagram.cpp
View File

@ -253,7 +253,7 @@ if(!firstGraph->cPointsX.isEmpty()) {
px += z;
z = pD->count - z;
for( ; z>0; z--) {
Str = num2str(*(px++));
Str = misc::num2str(*(px++));
colWidth = metrics.width(Str); // width of text
if(x+colWidth+2 >= x2) break;

2
qucs/dialogs/digisettingsdialog.cpp
View File

@ -130,7 +130,7 @@ void DigiSettingsDialog::slotOk()
if(SimTime != TimeEdit->text()) {
if(simRadio->isChecked()) {
QString s = TimeEdit->text();
if(!VHDL_Time(s, tr("Document Settings"))) {
if(!misc::VHDL_Time(s, tr("Document Settings"))) {
QMessageBox::critical(this, tr("Error"), s.mid(1));
reject();
return;

8
qucs/dialogs/matchdialog.cpp
View File

@ -517,15 +517,15 @@ QString MatchDialog::calcMatching(double r_real, double r_imag,
// serial component
if (X1 < 0.0) // capacitance ?
Str += ':' + num2str(-1.0 / Omega / X1) + 'F';
Str += ':' + misc::num2str(-1.0 / Omega / X1) + 'F';
else // inductance
Str += ':' + num2str(X1 / Omega) + 'H';
Str += ':' + misc::num2str(X1 / Omega) + 'H';
// parallel component
if (X2 < 0.0) // inductance ?
Str += ':' + num2str(-1.0 / Omega / X2) + 'H';
Str += ':' + misc::num2str(-1.0 / Omega / X2) + 'H';
else // capacitance
Str += ':' + num2str(X2 / Omega) + 'F';
Str += ':' + misc::num2str(X2 / Omega) + 'F';
return Str;
}

2
qucs/dialogs/packagedialog.cpp
View File

@ -376,7 +376,7 @@ void PackageDialog::extractPackage()
}
Version = QString(Content.data()+13);
if(!checkVersion(Version)) {
if(!misc::checkVersion(Version)) {
MsgText->append(tr("ERROR: Wrong version number!"));
goto ErrorEnd;
}

2
qucs/dialogs/simmessage.cpp
View File

@ -254,7 +254,7 @@ void SimMessage::nextSPICE()
}
if(makeSubcircuit) {
Stream << "\n.Def:" << properName(FileName) << " ";
Stream << "\n.Def:" << misc::properName(FileName) << " ";
Line.replace(',', ' ');
Stream << Line;

6
qucs/dialogs/sweepdialog.cpp
View File

@ -137,7 +137,7 @@ void SweepDialog::slotNewValue(int)
QList<Node *>::iterator node_it;
QList<double *>::const_iterator value_it;
for(node_it = NodeList.begin(); node_it != NodeList.end(); node_it++) {
(*node_it)->Name = num2str(*((*value_it)+Index));
(*node_it)->Name = misc::num2str(*((*value_it)+Index));
(*node_it)->Name += ((*node_it)->x1 & 0x10)? "A" : "V";
value_it++;
}
@ -191,7 +191,7 @@ Graph* SweepDialog::setBiasPoints()
pg->Var = pn->Name + ".V";
if(Diag->loadVarData(DataSet, pg)) {
pn->Name = num2str(*(pg->cPointsY)) + "V";
pn->Name = misc::num2str(*(pg->cPointsY)) + "V";
NodeList.append(pn); // remember node ...
ValueList.append(pg->cPointsY); // ... and all of its values
pg->cPointsY = 0; // do not delete it next time !
@ -220,7 +220,7 @@ Graph* SweepDialog::setBiasPoints()
pn->x1 = 0x10; // mark current
pg->Var = pc->Name + ".I";
if(Diag->loadVarData(DataSet, pg)) {
pn->Name = num2str(*(pg->cPointsY)) + "A";
pn->Name = misc::num2str(*(pg->cPointsY)) + "A";
NodeList.append(pn); // remember node ...
ValueList.append(pg->cPointsY); // ... and all of its values
pg->cPointsY = 0; // do not delete it next time !

42
qucs/misc.cpp
View File

@ -35,7 +35,7 @@
#include <QDir>
// #########################################################################
QString complexRect(double real, double imag, int Precision)
QString misc::complexRect(double real, double imag, int Precision)
{
QString Text;
if(fabs(imag) < 1e-250) Text = QString::number(real,'g',Precision);
@ -51,7 +51,7 @@ QString complexRect(double real, double imag, int Precision)
return Text;
}
QString complexDeg(double real, double imag, int Precision)
QString misc::complexDeg(double real, double imag, int Precision)
{
QString Text;
if(fabs(imag) < 1e-250) Text = QString::number(real,'g',Precision);
@ -62,7 +62,7 @@ QString complexDeg(double real, double imag, int Precision)
return Text;
}
QString complexRad (double real, double imag, int Precision)
QString misc::complexRad (double real, double imag, int Precision)
{
QString Text;
if(fabs(imag) < 1e-250) Text = QString::number(real,'g',Precision);
@ -74,7 +74,7 @@ QString complexRad (double real, double imag, int Precision)
}
// #########################################################################
QString StringNum(double num, char form, int Precision)
QString misc::StringNum(double num, char form, int Precision)
{
int a = 0;
char *p, Buffer[512], Format[6] = "%.00g";
@ -104,7 +104,7 @@ QString StringNum(double num, char form, int Precision)
}
// #########################################################################
QString StringNiceNum(double num)
QString misc::StringNiceNum(double num)
{
char Format[6] = "%.8e";
if(fabs(num) < 1e-250) return QString("0"); // avoid many problems
@ -139,7 +139,7 @@ QString StringNiceNum(double num)
}
// #########################################################################
void str2num(const QString& s_, double& Number, QString& Unit, double& Factor)
void misc::str2num(const QString& s_, double& Number, QString& Unit, double& Factor)
{
QString str = s_.stripWhiteSpace();
@ -195,7 +195,7 @@ void str2num(const QString& s_, double& Number, QString& Unit, double& Factor)
}
// #########################################################################
QString num2str(double Num)
QString misc::num2str(double Num)
{
char c = 0;
double cal = fabs(Num);
@ -227,7 +227,7 @@ QString num2str(double Num)
}
// #########################################################################
void convert2Unicode(QString& Text)
void misc::convert2Unicode(QString& Text)
{
bool ok;
int i = 0;
@ -244,7 +244,7 @@ void convert2Unicode(QString& Text)
}
// #########################################################################
void convert2ASCII(QString& Text)
void misc::convert2ASCII(QString& Text)
{
Text.replace('\\', "\\\\");
Text.replace('\n', "\\n");
@ -263,7 +263,7 @@ void convert2ASCII(QString& Text)
// #########################################################################
// Converts a path to an absolute path and resolves paths relative to the
// Qucs home directory
QString properAbsFileName(const QString& Name)
QString misc::properAbsFileName(const QString& Name)
{
QString s = Name;
QFileInfo Info(s);
@ -279,7 +279,7 @@ QString properAbsFileName(const QString& Name)
}
// #########################################################################
QString properFileName(const QString& Name)
QString misc::properFileName(const QString& Name)
{
QFileInfo Info(Name);
return Info.fileName();
@ -287,7 +287,7 @@ QString properFileName(const QString& Name)
// #########################################################################
// Takes a file name (with path) and replaces all special characters.
QString properName(const QString& Name)
QString misc::properName(const QString& Name)
{
QString s = Name;
QFileInfo Info(s);
@ -304,10 +304,10 @@ QString properName(const QString& Name)
// #########################################################################
// Creates and returns delay time for VHDL entities.
bool VHDL_Delay(QString& td, const QString& Name)
bool misc::VHDL_Delay(QString& td, const QString& Name)
{
if(strtod(td.latin1(), 0) != 0.0) { // delay time property
if(!VHDL_Time(td, Name))
if(!misc::VHDL_Time(td, Name))
return false; // time has not VHDL format
td = " after " + td;
return true;
@ -324,7 +324,7 @@ bool VHDL_Delay(QString& td, const QString& Name)
// #########################################################################
// Checks and corrects a time (number & unit) according VHDL standard.
bool VHDL_Time(QString& t, const QString& Name)
bool misc::VHDL_Time(QString& t, const QString& Name)
{
char *p;
double Time = strtod(t.latin1(), &p);
@ -351,11 +351,11 @@ bool VHDL_Time(QString& t, const QString& Name)
// #########################################################################
// Returns parameters for Verilog modules.
QString Verilog_Param(const QString Value)
QString misc::Verilog_Param(const QString Value)
{
if(strtod(Value.latin1(), 0) != 0.0) {
QString td = Value;
if(!Verilog_Time(td, "parameter"))
if(!misc::Verilog_Time(td, "parameter"))
return Value;
else
return td;
@ -366,10 +366,10 @@ QString Verilog_Param(const QString Value)
// #########################################################################
// Creates and returns delay time for Verilog modules.
bool Verilog_Delay(QString& td, const QString& Name)
bool misc::Verilog_Delay(QString& td, const QString& Name)
{
if(strtod(td.latin1(), 0) != 0.0) { // delay time property
if(!Verilog_Time(td, Name))
if(!misc::Verilog_Time(td, Name))
return false; // time has not Verilog format
td = " #" + td;
return true;
@ -386,7 +386,7 @@ bool Verilog_Delay(QString& td, const QString& Name)
// #########################################################################
// Checks and corrects a time (number & unit) according Verilog standard.
bool Verilog_Time(QString& t, const QString& Name)
bool misc::Verilog_Time(QString& t, const QString& Name)
{
char *p;
double Time = strtod(t.latin1(), &p);
@ -413,7 +413,7 @@ bool Verilog_Time(QString& t, const QString& Name)
}
// #########################################################################
bool checkVersion(QString& Line)
bool misc::checkVersion(QString& Line)
{
QStringList sl = QStringList::split('.',PACKAGE_VERSION);
QStringList ll = QStringList::split('.',Line);

38
qucs/misc.h
View File

@ -21,21 +21,23 @@
class QString;
QString complexRect(double, double, int Precision=3);
QString complexDeg (double, double, int Precision=3);
QString complexRad (double, double, int Precision=3);
QString StringNum (double, char form='g', int Precision=3);
void str2num (const QString&, double&, QString&, double&);
QString num2str (double);
QString StringNiceNum(double);
void convert2Unicode(QString&);
void convert2ASCII(QString&);
QString properName(const QString&);
QString properAbsFileName(const QString&);
QString properFileName(const QString&);
bool VHDL_Time(QString&, const QString&);
bool VHDL_Delay(QString&, const QString&);
bool Verilog_Time(QString&, const QString&);
bool Verilog_Delay(QString&, const QString&);
QString Verilog_Param(const QString);
bool checkVersion(QString&);
namespace misc {
QString complexRect(double, double, int Precision=3);
QString complexDeg (double, double, int Precision=3);
QString complexRad (double, double, int Precision=3);
QString StringNum (double, char form='g', int Precision=3);
void str2num (const QString&, double&, QString&, double&);
QString num2str (double);
QString StringNiceNum(double);
void convert2Unicode(QString&);
void convert2ASCII(QString&);
QString properName(const QString&);
QString properAbsFileName(const QString&);
QString properFileName(const QString&);
bool VHDL_Time(QString&, const QString&);
bool VHDL_Delay(QString&, const QString&);
bool Verilog_Time(QString&, const QString&);
bool Verilog_Delay(QString&, const QString&);
QString Verilog_Param(const QString);
bool checkVersion(QString&);
}

8
qucs/paintings/graphictext.cpp
View File

@ -163,7 +163,7 @@ bool GraphicText::load(const QString& s)
Text.truncate(Text.length()-1);
if(Text.isEmpty()) return false;
convert2Unicode(Text);
misc::convert2Unicode(Text);
// get size of text using the screen-compatible metric
QFontMetrics metrics(QucsSettings.font, 0);
QSize r = metrics.size(0, Text); // get overall size of text
@ -177,7 +177,7 @@ bool GraphicText::load(const QString& s)
QString GraphicText::save()
{
QString t = Text;
convert2ASCII(t);
misc::convert2ASCII(t);
// The 'Text' property has to be the last within the line !
QString s = Name+QString::number(cx)+" "+QString::number(cy)+" "
@ -190,7 +190,7 @@ QString GraphicText::save()
QString GraphicText::saveCpp()
{
QString t = Text;
convert2ASCII(t);
misc::convert2ASCII(t);
QString s =
QString ("new Text (%1, %2, \"%3\", QColor (\"%4\"), %5, %6, %7)").
@ -204,7 +204,7 @@ QString GraphicText::saveCpp()
QString GraphicText::saveJSON()
{
QString t = Text;
convert2ASCII(t);
misc::convert2ASCII(t);
QString s =
QString ("{\"type\" : \"graphictext\", "

32
qucs/schematic_file.cpp
View File

@ -371,13 +371,13 @@ int Schematic::saveDocument()
stream << " <showFrame=" << showFrame << ">\n";
QString t;
convert2ASCII(t = Frame_Text0);
misc::convert2ASCII(t = Frame_Text0);
stream << " <FrameText0=" << t << ">\n";
convert2ASCII(t = Frame_Text1);
misc::convert2ASCII(t = Frame_Text1);
stream << " <FrameText1=" << t << ">\n";
convert2ASCII(t = Frame_Text2);
misc::convert2ASCII(t = Frame_Text2);
stream << " <FrameText2=" << t << ">\n";
convert2ASCII(t = Frame_Text3);
misc::convert2ASCII(t = Frame_Text3);
stream << " <FrameText3=" << t << ">\n";
stream << "</Properties>\n";
@ -567,10 +567,10 @@ bool Schematic::loadProperties(QTextStream *stream)
else SimRunScript = true;
else if(cstr == "showFrame")
showFrame = nstr.at(0).toLatin1() - '0';
else if(cstr == "FrameText0") convert2Unicode(Frame_Text0 = nstr);
else if(cstr == "FrameText1") convert2Unicode(Frame_Text1 = nstr);
else if(cstr == "FrameText2") convert2Unicode(Frame_Text2 = nstr);
else if(cstr == "FrameText3") convert2Unicode(Frame_Text3 = nstr);
else if(cstr == "FrameText0") misc::convert2Unicode(Frame_Text0 = nstr);
else if(cstr == "FrameText1") misc::convert2Unicode(Frame_Text1 = nstr);
else if(cstr == "FrameText2") misc::convert2Unicode(Frame_Text2 = nstr);
else if(cstr == "FrameText3") misc::convert2Unicode(Frame_Text3 = nstr);
else {
QMessageBox::critical(0, QObject::tr("Error"),
QObject::tr("Format Error:\nUnknown property: ")+cstr);
@ -854,7 +854,7 @@ bool Schematic::loadDocument()
}
Line = Line.mid(16, Line.length()-17);
if(!checkVersion(Line)) { // wrong version number ?
if(!misc::checkVersion(Line)) { // wrong version number ?
QMessageBox::StandardButton result;
result = QMessageBox::warning(0,
@ -1092,7 +1092,7 @@ int Schematic::testFile(const QString& DocName)
}
Line = Line.mid(16, Line.length()-17);
if(!checkVersion(Line)) { // wrong version number ?
if(!misc::checkVersion(Line)) { // wrong version number ?
if (!QucsSettings.IgnoreFutureVersion) {
file.close();
return -4;
@ -1475,7 +1475,7 @@ int NumPorts)
QTextStream * tstream = stream;
QFile ofile;
if(creatingLib) {
QString f = properAbsFileName(DocName) + ".lst";
QString f = misc::properAbsFileName(DocName) + ".lst";
ofile.setFileName(f);
if(!ofile.open(IO_WriteOnly)) {
ErrText->insert(tr("ERROR: Cannot create library file \"%s\".").arg(f));
@ -1562,8 +1562,8 @@ int NumPorts)
}
}
QString f = properFileName(DocName);
QString Type = properName(f);
QString f = misc::properFileName(DocName);
QString Type = misc::properName(f);
Painting *pi;
if(isAnalog) {
@ -1619,7 +1619,7 @@ int NumPorts)
ID_Text *pid = (ID_Text*)pi;
for(it = pid->Parameter.constBegin(); it != pid->Parameter.constEnd(); it++) {
s = (*it)->Name.section('=', 0,0);
QString v = Verilog_Param((*it)->Name.section('=', 1,1));
QString v = misc::Verilog_Param((*it)->Name.section('=', 1,1));
(*tstream) << " parameter " << s << " = " << v << ";\n";
}
(*tstream) << "\n";
@ -1910,9 +1910,9 @@ QString Schematic::createNetlist(QTextStream& stream, int NumPorts)
} else {
Time = pc->Props.at(1)->Value;
if (isVerilog) {
if(!Verilog_Time(Time, pc->Name)) return Time;
if(!misc::Verilog_Time(Time, pc->Name)) return Time;
} else {
if(!VHDL_Time(Time, pc->Name)) return Time; // wrong time format
if(!misc::VHDL_Time(Time, pc->Name)) return Time; // wrong time format
}
}
}