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2007-03-28 Stefan Jahn <stefan@lkcc.org>

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* schematic_file.cpp (createNetlist): Fixed a bug in
        determining the simulation time of digital simulations
        occurring when there are other disabled simulations
        placed on the schematic.
        (createSubNetlist): Implemented subcircuit modules for
        Verilog simulations.

2007-03-28  Stefan Jahn  <stefan@lkcc.org>

        * d_flipflop.cpp (verilogCode): Fixed Verilog code of
        D-flipflop.  Is working now, can be used as template for
        other flipflops.
This commit is contained in:
ela 2007-03-28 16:02:00 +00:00
parent 00b2e689ab
commit dd8174d44d
11 changed files with 156 additions and 62 deletions
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9
qucs/ChangeLog
View File

@ -1,3 +1,12 @@
2007-03-28 Stefan Jahn <stefan@lkcc.org>
* schematic_file.cpp (createNetlist): Fixed a bug in
determining the simulation time of digital simulations
occurring when there are other disabled simulations
placed on the schematic.
(createSubNetlist): Implemented subcircuit modules for
Verilog simulations.
2007-03-26 Stefan Jahn <stefan@lkcc.org>
* qucsveri: New digital simulation wrapper for Icarus

6
qucs/components/ChangeLog
View File

@ -1,3 +1,9 @@
2007-03-28 Stefan Jahn <stefan@lkcc.org>
* d_flipflop.cpp (verilogCode): Fixed Verilog code of
D-flipflop. Is working now, can be used as template for
other flipflops.
2007-03-26 Stefan Jahn <stefan@lkcc.org>
* digi_sim.cpp (Digi_Sim): Can select between VHDL and Verilog

14
qucs/components/component.cpp
View File

@ -639,9 +639,11 @@ QString Component::get_Verilog_Code(int NumPorts)
}
// Component is shortened.
QString Node1 = Ports.first()->Connection->Name;
QString s = " wire " + Node1 + ";\n";
s += " assign " + Node1 + " = " + Ports.next()->Connection->Name + ";\n";
Port *p = Ports.first();
QString Node1 = p->Connection->Name;
QString s = "";
for(p = Ports.next(); p != 0; p = Ports.next())
s += " assign " + p->Connection->Name + " = " + Node1 + ";\n";
return s;
}
@ -1261,15 +1263,15 @@ QString GateComponent::verilogCode(int NumPorts)
Port *pp = Ports.first();
QString s = " " + Model.lower();
if(NumPorts <= 0) // no truth table simulation ?
if(strtod(Props.at(2)->Value.latin1(), 0) != 0.0) { // delay time
QString t = Props.current()->Value;
if(!Verilog_Time(t, Name))
return t; // time has not VHDL format
return t; // time has not VHDL format
s += " #" + t;
}
s += " " + Name + " (" + pp->Connection->Name; // output port;
s += " " + Name + " (" + pp->Connection->Name; // output port
pp = Ports.next();
s += ", " + pp->Connection->Name; // first input port

47
qucs/components/d_flipflop.cpp
View File

@ -19,6 +19,7 @@
#include "d_flipflop.h"
#include "node.h"
#include "main.h"
D_FlipFlop::D_FlipFlop()
{
@ -79,30 +80,30 @@ QString D_FlipFlop::vhdlCode(int NumPorts)
// -------------------------------------------------------
QString D_FlipFlop::verilogCode(int NumPorts)
{
QString s = ";\n";
QString d = " #0" + s;
QString t = "";
if(NumPorts <= 0) // no truth table simulation ?
if(strtod(Props.getFirst()->Value.latin1(), 0) != 0.0) // delay time
d = " #" + Props.getFirst()->Value + s;
s = "module " + Name + "(" +
Ports.at(2)->Connection->Name + ", " +
Ports.at(0)->Connection->Name + ", " +
Ports.at(1)->Connection->Name + ", " +
Ports.at(3)->Connection->Name + ")" + s + " input " +
Ports.at(0)->Connection->Name + ", " +
Ports.at(1)->Connection->Name + ", " +
Ports.at(3)->Connection->Name + s + " output reg " +
Ports.at(2)->Connection->Name + s + " always @(" +
Ports.at(0)->Connection->Name + " or " +
Ports.at(1)->Connection->Name + " or " +
Ports.at(3)->Connection->Name + ") begin\n" + d + " if (" +
Ports.at(3)->Connection->Name + ") " +
Ports.at(2)->Connection->Name + " <= 0" + s + " if (~" +
Ports.at(3)->Connection->Name + " && " +
Ports.at(1)->Connection->Name + ") " +
Ports.at(2)->Connection->Name + " <= " +
Ports.at(0)->Connection->Name + s + " end\nendmodule\n";
if(strtod(Props.getFirst()->Value.latin1(), 0) != 0.0) { // delay time
t = Props.getFirst()->Value;
if(!Verilog_Time(t, Name))
return t; // time has not VHDL format
t = " #" + t + ";\n";
}
QString s = "";
QString q = Ports.at(2)->Connection->Name;
QString d = Ports.at(0)->Connection->Name;
QString r = Ports.at(3)->Connection->Name;
QString c = Ports.at(1)->Connection->Name;
QString v = "net_reg" + Name + q;
s = "\n // " + Name + " D-flipflop\n" +
" assign " + q + " = " + v + ";\n" +
" reg " + v + ";\n" +
" initial " + v + " = 0;\n" +
" always @ (" + c + " or " + r + ") begin\n" + t +
" if (" + r + ") " + v + " <= 0;\n" +
" else if (~" + r + " && " + c + ") " + v + " <= " + d + ";\n" +
" end\n\n";
return s;
}

19
qucs/components/digi_source.cpp
View File

@ -147,11 +147,13 @@ QString Digi_Source::vhdlCode(int NumPorts)
// -------------------------------------------------------
QString Digi_Source::verilogCode(int NumPorts)
{
QString s, t, n;
QString s, t, n, r;
s = "\n // " + Name + " digital source\n";
n = Ports.getFirst()->Connection->Name;
s += " reg " + n + ";\n";
r = "net_src" + n;
s = "\n // " + Name + " digital source\n";
s += " assign " + n + " = " + r + ";\n";
s += " reg " + r + ";\n";
int z = 0;
char State;
@ -160,23 +162,26 @@ QString Digi_Source::verilogCode(int NumPorts)
State = '0';
else
State = '1';
s += " initial #0 " + n + " = " + State + ";\n always begin\n";
s += " always begin\n";
t = Props.next()->Value.section(';',z,z).stripWhiteSpace();
while(!t.isEmpty()) {
if(!Verilog_Time(t, Name))
return t; // time has not VHDL format
s += " " + r + " = " + State + ";\n";
s += " #" + t + ";\n";
State ^= 1;
s += " #" + t + " " + n + " = " + State + ";\n";
z++;
t = Props.current()->Value.section(';',z,z).stripWhiteSpace();
}
}
else { // truth table simulation
int Num = Props.getFirst()->Value.toInt() - 1;
s += " initial #0 " + n + " = " + "0;\n always begin\n";
s += " always begin\n";
s += " " + r + " = 0;\n";
for(z=1<<(NumPorts-Num); z>0; z--) {
s += " #"+ QString::number(1 << Num) + " " + n + " = !" + n + ";\n";
s += " #"+ QString::number(1 << Num) + ";\n";
s += " " + r + " = !" + r + ";\n";
}
}

4
qucs/components/logical_inv.cpp
View File

@ -75,10 +75,10 @@ QString Logical_Inv::verilogCode(int NumPorts)
if(strtod(Props.at(1)->Value.latin1(), 0) != 0.0) { // delay time
QString t = Props.current()->Value;
if(!Verilog_Time(t, Name))
return t; // time has not VHDL format
return t; // time has not VHDL format
s += " #" + t;
}
s += " " + Name + " (" + pp->Connection->Name; // output port;
s += " " + Name + " (" + pp->Connection->Name; // output port
pp = Ports.next();
s += ", " + pp->Connection->Name; // first input port

16
qucs/components/subcircuit.cpp
View File

@ -227,3 +227,19 @@ QString Subcircuit::vhdlCode(int)
s += ");\n";
return s;
}
// -------------------------------------------------------
QString Subcircuit::verilogCode(int)
{
QString s = " Sub_" +
properName(Props.getFirst()->Value) + " " + Name + " (";
// output all node names
Port *pp = Ports.first();
if(pp) s += pp->Connection->Name;
for(pp = Ports.next(); pp != 0; pp = Ports.next())
s += ", "+pp->Connection->Name; // node names
s += ");\n";
return s;
}

1
qucs/components/subcircuit.h
View File

@ -31,6 +31,7 @@ public:
protected:
QString netlist();
QString vhdlCode(int);
QString verilogCode(int);
void createSymbol();
void remakeSymbol(int No);
int loadSymbol(const QString&);

6
qucs/components/subcirport.cpp
View File

@ -117,3 +117,9 @@ QString SubCirPort::vhdlCode(int)
s += pn->Name + " or '0';\n";
return s;
}
// -------------------------------------------------------
QString SubCirPort::verilogCode(int)
{
return QString("");
}

1
qucs/components/subcirport.h
View File

@ -31,6 +31,7 @@ public:
protected:
QString netlist();
QString vhdlCode(int);
QString verilogCode(int);
void createSymbol();
};

95
qucs/schematic_file.cpp
View File

@ -859,6 +859,7 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
return false;
}
d->DocName = s;
d->isVerilog = isVerilog;
r = d->createSubNetlist(stream, countInit, Collect, ErrText, NumPorts);
delete d;
if(!r) return false;
@ -961,6 +962,9 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
else it++;*/
QStringList SubcircuitPorts;
QStringList InPorts;
QStringList OutPorts;
QStringList InOutPorts;
QStringList::Iterator it;
Component *pc;
// collect subcircuit ports and sort their node names into "SubcircuitPorts"
@ -977,16 +981,31 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
it = SubcircuitPorts.at(i-1);
(*it) = pc->Ports.getFirst()->Connection->Name;
if(NumPorts >= 0) {
Signals.remove(Signals.find(*it)); // remove node name of output port
switch(pc->Props.at(1)->Value.at(0).latin1()) {
if (isVerilog) {
Signals.remove(Signals.find(*it)); // remove node name
switch(pc->Props.at(1)->Value.at(0).latin1()) {
case 'a':
InOutPorts.append(*it);
break;
case 'o':
OutPorts.append(*it);
break;
default:
InPorts.append(*it);
}
}
else {
Signals.remove(Signals.find(*it)); // remove node name of output port
switch(pc->Props.at(1)->Value.at(0).latin1()) {
case 'a': (*it) += ": inout"; // attribut "analog" is "inout"
break;
break;
case 'o': Signals.append(*it); // output ports need workaround
(*it) = "net_out" + (*it);
// no "break;" here !!!
(*it) = "net_out" + (*it);
// no "break;" here !!!
default: (*it) += ": " + pc->Props.at(1)->Value;
}
(*it) += " bit";
}
(*it) += " bit";
}
}
}
}
@ -1017,25 +1036,52 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
}
else {
// ..... digital subcircuit ...................................
(*stream) << "\nentity Sub_" << Type << " is\n"
<< " port (" << SubcircuitPorts.join(";\n ") << ");\n"
<< "end entity;\n"
<< "use work.all;\n"
<< "architecture Arch_Sub_" << Type << " of Sub_" << Type << " is\n";
if(!Signals.isEmpty())
(*stream) << " signal " << Signals.join(",\n ") << " : bit;\n";
if (isVerilog) {
// ..... digital subcircuit ...................................
(*stream) << "\nmodule Sub_" << Type << " ("
<< SubcircuitPorts.join(", ") << ");\n";
if(!InPorts.isEmpty())
(*stream) << " input " << InPorts.join(", ") << ";\n";
if(!OutPorts.isEmpty())
(*stream) << " output " << OutPorts.join(", ") << ";\n";
if(!InOutPorts.isEmpty())
(*stream) << " inout " << InOutPorts.join(", ") << ";\n";
if(!Signals.isEmpty())
(*stream) << " wire " << Signals.join(",\n ")
<< ";\n";
(*stream) << "\n";
(*stream) << "begin\n";
if(Signals.findIndex("gnd") >= 0)
(*stream) << " assign gnd = 0;\n"; // should appear only once
if(Signals.findIndex("gnd") >= 0)
(*stream) << " gnd <= '0';\n"; // should appear only once
// write all components into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next())
(*stream) << pc->get_Verilog_Code(NumPorts);
// write all components into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next())
(*stream) << pc->get_VHDL_Code(NumPorts);
(*stream) << "endmodule\n\n";
} else {
// ..... digital subcircuit ...................................
(*stream) << "\nentity Sub_" << Type << " is\n"
<< " port (" << SubcircuitPorts.join(";\n ") << ");\n"
<< "end entity;\n"
<< "use work.all;\n"
<< "architecture Arch_Sub_" << Type << " of Sub_" << Type
<< " is\n";
if(!Signals.isEmpty())
(*stream) << " signal " << Signals.join(",\n ")
<< " : bit;\n";
(*stream) << "end architecture;\n\n";
(*stream) << "begin\n";
if(Signals.findIndex("gnd") >= 0)
(*stream) << " gnd <= '0';\n"; // should appear only once
// write all components into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next())
(*stream) << pc->get_VHDL_Code(NumPorts);
(*stream) << "end architecture;\n\n";
}
}
Signals.clear(); // was filled in "giveNodeNames()"
@ -1139,7 +1185,8 @@ QString Schematic::createNetlist(QTextStream& stream, int NumPorts)
if(NumPorts >= 0) {
if (isVerilog) {
stream << "module TestBench ();\n"
<< " wire gnd;\n";
<< " wire " << Signals.join(",\n ")
<< ";\n\n";
} else {
stream << "architecture Arch_TestBench of TestBench is\n"
<< " signal " << Signals.join(",\n ")
@ -1164,7 +1211,7 @@ QString Schematic::createNetlist(QTextStream& stream, int NumPorts)
s = pc->getNetlist();
}
else {
if(pc->Model.at(0) == '.') { // simulation component ?
if(pc->Model == ".Digi" && pc->isActive) { // simulation component ?
if(NumPorts > 0) { // truth table simulation ?
if (isVerilog)
Time = QString::number((1 << NumPorts));