SIM/qucs_s
1
0
Fork 0
mirror of https://github.com/ra3xdh/qucs_s synced 2025-03-28 21:13:26 +00:00
Code Issues Packages Projects Releases Wiki Activity

2009-05-04 Stefan Jahn <stefan@lkcc.org>

Browse Source 
* equation.cpp (verilogCode, vhdlCode): Added code for equations.

2009-05-04  Stefan Jahn  <stefan@lkcc.org>

        * schematic_file.cpp (createSubNetlistPlain): Allow equations to
        be put into Verilog and VHDL netlists.
This commit is contained in:
ela 2009-05-04 20:24:30 +00:00
parent 7fd7b39c8c
commit e0a1995b85
25 changed files with 162 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
NEWS
View File

@ -26,6 +26,8 @@ files.
Version 0.0.16
--------------
* allow equations in Verilog-HDL and VHDL subcircuits
Version 0.0.15
--------------

2
qucs-filter-v2/qf_matrix.h
View File

@ -22,7 +22,7 @@ class qf_matrix {
// There is no way to copy a matrix
qf_matrix& operator = (const qf_matrix& M) {return (*this);}
qf_matrix& operator = (const qf_matrix&) {return (*this);}
qf_matrix (const qf_matrix& M) : n (M.n), H (M.H) {}
public:

5
qucs/ChangeLog
View File

@ -1,3 +1,8 @@
2009-05-04 Stefan Jahn <stefan@lkcc.org>
* schematic_file.cpp (createSubNetlistPlain): Allow equations to
be put into Verilog and VHDL netlists.
2009-04-17 Stefan Jahn <stefan@lkcc.org>
* schematic_file.cpp (createSubNetlistPlain): Create parameter

4
qucs/components/ChangeLog
View File

@ -1,3 +1,7 @@
2009-05-04 Stefan Jahn <stefan@lkcc.org>
* equation.cpp (verilogCode, vhdlCode): Added code for equations.
2009-04-29 Stefan Jahn <stefan@lkcc.org>
* jk_flipflop.cpp, d_flipflop.cpp (verilogCode): Fixed malformed

22
qucs/components/component.cpp
View File

@ -31,8 +31,7 @@
#include <qpainter.h>
#include <qtabwidget.h>
#include <qmessagebox.h>
#include <qdom.h>
// ***********************************************************************
// ********** **********
@ -680,6 +679,25 @@ QString Component::get_VHDL_Code(int NumPorts)
// -------------------------------------------------------
QString Component::save()
{
#if XML
QDomDocument doc;
QDomElement el = doc.createElement (Model);
doc.appendChild (el);
el.setTagName (Model);
el.setAttribute ("inst", Name.isEmpty() ? "*" : Name);
el.setAttribute ("display", isActive | (showName ? 4 : 0));
el.setAttribute ("cx", cx);
el.setAttribute ("cy", cy);
el.setAttribute ("tx", tx);
el.setAttribute ("ty", ty);
el.setAttribute ("mirror", mirroredX);
el.setAttribute ("rotate", rotated);
for (Property *pr = Props.first(); pr != 0; pr = Props.next()) {
el.setAttribute (pr->Name, (pr->display ? "1@" : "0@") + pr->Value);
}
qDebug (doc.toString());
#endif
QString s = "<" + Model;
if(Name.isEmpty()) s += " * ";

23
qucs/components/equation.cpp
View File

@ -21,6 +21,7 @@
Equation::Equation()
{
Type = isComponent; // Analogue and digital component.
Description = QObject::tr("equation");
QFont f = QucsSettings.font;
@ -53,6 +54,28 @@ Equation::~Equation()
{
}
// -------------------------------------------------------
QString Equation::verilogCode(int)
{
QString s;
// output all equations
for(Property *pr = Props.first(); pr != 0; pr = Props.next())
if(pr->Name != "Export")
s += " real "+pr->Name+"; initial "+pr->Name+" = "+pr->Value+";\n";
return s;
}
// -------------------------------------------------------
QString Equation::vhdlCode(int)
{
QString s;
// output all equations
for(Property *pr = Props.first(); pr != 0; pr = Props.next())
if(pr->Name != "Export")
s += " constant "+pr->Name+" : time := "+pr->Value+";\n";
return s;
}
Component* Equation::newOne()
{
return new Equation();

5
qucs/components/equation.h
View File

@ -22,11 +22,16 @@
class Equation : public Component {
public:
Equation();
~Equation();
Component* newOne();
static Element* info(QString&, char* &, bool getNewOne=false);
protected:
QString vhdlCode(int);
QString verilogCode(int);
};
#endif

4
qucs/qucs_ar.ts
View File

@ -6760,6 +6760,10 @@ qucsedit [-r] file :إستعمال
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsApp</name>

4
qucs/qucs_ca.ts
View File

@ -7004,6 +7004,10 @@ Use: qucsedit [-r] fitxer
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_cs.ts
View File

@ -7226,6 +7226,10 @@ Použití: qucsedit [-r] soubor
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_de.ts
View File

@ -7282,6 +7282,10 @@ Verwendung: qucsedit [-r] Datei
<source>generic variable</source>
<translation>generische Variable</translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_es.ts
View File

@ -7028,6 +7028,10 @@ Use: qucsedit [-r] archivo
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_fr.ts
View File

@ -7032,6 +7032,10 @@ Invocation : qucsedit [-r] fichier
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_he.ts
View File

@ -6859,6 +6859,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_hu.ts
View File

@ -7002,6 +7002,10 @@ Digitális szimuláció</translation>
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_it.ts
View File

@ -7177,6 +7177,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_jp.ts
View File

@ -6958,6 +6958,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_pl.ts
View File

@ -7064,6 +7064,10 @@ Stosowanie: qucsedit [-r] plik
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_pt.ts
View File

@ -6870,6 +6870,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsApp</name>

4
qucs/qucs_ro.ts
View File

@ -6943,6 +6943,10 @@ Folosire: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_ru.ts
View File

@ -7273,6 +7273,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_sv.ts
View File

@ -6824,6 +6824,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_tr.ts
View File

@ -6867,6 +6867,10 @@ Kullanım: qucsedit [-r] kütük
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsActions</name>

4
qucs/qucs_uk.ts
View File

@ -6862,6 +6862,10 @@ Usage: qucsedit [-r] file
<source>generic variable</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>WARNING: Equations in &quot;%1&quot; are &apos;time&apos; typed.</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsApp</name>

42
qucs/schematic_file.cpp
View File

@ -1224,12 +1224,16 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
// ..... digital subcircuit ...................................
(*tstream) << "\nmodule Sub_" << Type << " ("
<< SubcircuitPortNames.join(", ") << ");\n";
// subcircuit in/out connections
if(!InPorts.isEmpty())
(*tstream) << " input " << InPorts.join(", ") << ";\n";
if(!OutPorts.isEmpty())
(*tstream) << " output " << OutPorts.join(", ") << ";\n";
if(!InOutPorts.isEmpty())
(*tstream) << " inout " << InOutPorts.join(", ") << ";\n";
// subcircuit connections
if(!Signals.isEmpty()) {
QValueList<DigSignal> values = Signals.values();
QValueList<DigSignal>::iterator it;
@ -1239,6 +1243,7 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
}
(*tstream) << "\n";
// subcircuit parameters
for(pi = SymbolPaints.first(); pi != 0; pi = SymbolPaints.next())
if(pi->Name == ".ID ") {
SubParameter *pp;
@ -1255,16 +1260,25 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
break;
}
// write all equations into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next()) {
if(pc->Model == "Eqn") {
(*tstream) << pc->get_Verilog_Code(NumPorts);
}
}
if(Signals.find("gnd") != Signals.end())
(*tstream) << " assign gnd = 0;\n"; // should appear only once
// write all components into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next()) {
s = pc->get_Verilog_Code(NumPorts);
if(s.at(0) == '§') {
ErrText->insert(s.mid(1));
if(pc->Model != "Eqn") {
s = pc->get_Verilog_Code(NumPorts);
if(s.at(0) == '§') {
ErrText->insert(s.mid(1));
}
else (*tstream) << s;
}
else (*tstream) << s;
}
(*tstream) << "endmodule\n";
@ -1308,6 +1322,16 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
}
}
// write all equations into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next()) {
if(pc->Model == "Eqn") {
ErrText->insert(
QObject::tr("WARNING: Equations in \"%1\" are 'time' typed.").
arg(pc->Name));
(*tstream) << pc->get_VHDL_Code(NumPorts);
}
}
(*tstream) << "begin\n";
if(Signals.find("gnd") != Signals.end())
@ -1315,11 +1339,13 @@ void Schematic::createSubNetlistPlain(QTextStream *stream, QTextEdit *ErrText,
// write all components into netlist file
for(pc = DocComps.first(); pc != 0; pc = DocComps.next()) {
s = pc->get_VHDL_Code(NumPorts);
if(s.at(0) == '§') {
ErrText->insert(s.mid(1));
if(pc->Model != "Eqn") {
s = pc->get_VHDL_Code(NumPorts);
if(s.at(0) == '§') {
ErrText->insert(s.mid(1));
}
else (*tstream) << s;
}
else (*tstream) << s;
}
(*tstream) << "end architecture;\n";