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2007-03-25 Stefan Jahn <stefan@lkcc.org>

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* component.cpp (verilogHDL_Code): New virtual function which
        is used to produce Verilog HDL code.

        * d_flipflop.cpp (verilogHDL_Code): Added the first Verilog HDL
        code.  Provided by Ozgur.
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ela 2007-03-25 11:20:15 +00:00
parent 9463bba1ce
commit e5b6be4fb2
5 changed files with 46 additions and 0 deletions
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8
qucs/components/ChangeLog
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@ -1,3 +1,11 @@
2007-03-25 Stefan Jahn <stefan@lkcc.org>
* component.cpp (verilogHDL_Code): New virtual function which
is used to produce Verilog HDL code.
* d_flipflop.cpp (verilogHDL_Code): Added the first Verilog HDL
code. Provided by Ozgur.
2007-03-06 Stefan Jahn <stefan@lkcc.org>
* twistedpair.cpp (TwistedPair): Added some new properties

6
qucs/components/component.cpp
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@ -622,6 +622,12 @@ QString Component::getNetlist()
return s;
}
// -------------------------------------------------------
QString Component::verilogHDL_Code(int)
{
return QString(""); // no digital model
}
// -------------------------------------------------------
QString Component::vhdlCode(int)
{

1
qucs/components/component.h
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@ -79,6 +79,7 @@ public:
protected:
virtual QString netlist();
virtual QString vhdlCode(int);
virtual QString verilogHDL_Code(int);
int analyseLine(const QString&, int);
bool getIntegers(const QString&, int *i1=0, int *i2=0, int *i3=0,

30
qucs/components/d_flipflop.cpp
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@ -76,6 +76,36 @@ QString D_FlipFlop::vhdlCode(int NumPorts)
return s;
}
// -------------------------------------------------------
QString D_FlipFlop::verilogHDL_Code(int NumPorts)
{
QString s = ";\n";
QString d = " #0" + s;
if(NumPorts <= 0) // no truth table simulation ?
if(strtod(Props.getFirst()->Value.latin1(), 0) != 0.0) // delay time
d = " #" + Props.getFirst()->Value + s;
s = "module " + Name + "(" +
Ports.at(2)->Connection->Name + ", " +
Ports.at(0)->Connection->Name + ", " +
Ports.at(1)->Connection->Name + ", " +
Ports.at(3)->Connection->Name + ")" + s + " input " +
Ports.at(0)->Connection->Name + ", " +
Ports.at(1)->Connection->Name + ", " +
Ports.at(3)->Connection->Name + s + " output reg " +
Ports.at(2)->Connection->Name + s + " always @(" +
Ports.at(0)->Connection->Name + " or " +
Ports.at(1)->Connection->Name + " or " +
Ports.at(3)->Connection->Name + ") begin\n" + d + " if (" +
Ports.at(3)->Connection->Name + ") " +
Ports.at(2)->Connection->Name + " <= 0" + s + " if (~" +
Ports.at(3)->Connection->Name + " && " +
Ports.at(1)->Connection->Name + ") " +
Ports.at(2)->Connection->Name + " <= " +
Ports.at(0)->Connection->Name + s + " end\nendmodule\n";
return s;
}
// -------------------------------------------------------
Component* D_FlipFlop::newOne()
{

1
qucs/components/d_flipflop.h
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@ -30,6 +30,7 @@ public:
protected:
QString vhdlCode(int);
QString verilogHDL_Code(int);
};
#endif