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https://github.com/ra3xdh/qucs_s
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Fixed double .subckt addition in nested Subcircuits
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@ -86,7 +86,7 @@ void AbstractSpiceKernel::killThemAll()
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* prepared for Xyce simulator. For Ngspice should be false.
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* \return Returns true if success, false if netlist preparation fails
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*/
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bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream)
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bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream, bool isSubckt)
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{
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QStringList collect;
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QPlainTextEdit *err = new QPlainTextEdit;
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@ -96,7 +96,8 @@ bool AbstractSpiceKernel::prepareSpiceNetlist(QTextStream &stream)
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return false;
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}
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delete err;
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Sch->clearSignalsAndFileList(); // for proper build of subckts
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if (isSubckt) Sch->clearSignals();
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else Sch->clearSignalsAndFileList(); // for proper build of subckts
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return true; // TODO: Add feature to determine ability of spice simulation
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}
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@ -197,7 +198,7 @@ void AbstractSpiceKernel::createSubNetlsit(QTextStream &stream, bool lib)
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header = QString(".SUBCKT %1 ").arg(misc::properName(f));
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QList< QPair<int,QString> > ports;
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if(!prepareSpiceNetlist(stream)) {
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if(!prepareSpiceNetlist(stream,true)) {
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emit finished();
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emit errors(QProcess::FailedToStart);
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return;
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@ -57,7 +57,7 @@ protected:
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bool DC_OP_only; // only calculate operating point to show DC bias
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Schematic *Sch;
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bool prepareSpiceNetlist(QTextStream &stream);
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bool prepareSpiceNetlist(QTextStream &stream, bool isSubckt = false);
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virtual void startNetlist(QTextStream& stream, bool xyce = false);
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virtual void createNetlist(QTextStream& stream, int NumPorts,QStringList& simulations,
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QStringList& vars, QStringList &outputs);
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@ -283,6 +283,7 @@ public:
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bool loadDocument();
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void highlightWireLabels (void);
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void clearSignalsAndFileList();
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void clearSignals();
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private:
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int saveDocument();
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@ -1999,3 +1999,8 @@ void Schematic::clearSignalsAndFileList()
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Signals.clear(); // was filled in "giveNodeNames()"
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FileList.clear();
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}
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void Schematic::clearSignals()
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{
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Signals.clear();
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}
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