SIM/qucs_s
1
0
Fork 0
mirror of https://github.com/ra3xdh/qucs_s synced 2025-03-28 21:13:26 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix component-from-library-lookup error message

Browse Source 
ERROR: "someinstance": could not load "somemodel" from "somelib"

instead of

ERROR: "someinstance": bad.
This commit is contained in:
Felix Salfelder 2015-10-02 12:52:18 +02:00
parent a29d3cb955
commit ea57204668
2 changed files with 33 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
qucs/main.cpp
View File

@ -289,7 +289,8 @@ int doNetlist(QString schematic, QString netlist)
if(SimPorts < -5) {
NetlistFile.close();
fprintf(stderr, "Error: Could not prepare the netlist...\n");
QByteArray ba = netlist.toLatin1();
fprintf(stderr, "Error: Could not prepare netlist %s\n", ba.data());
/// \todo better handling for error/warnings
qCritical() << ErrText->toPlainText();
return 1;

51
qucs/schematic_file.cpp
View File

@ -1305,32 +1305,28 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
continue;
} // if(pc->Model == "Sub")
// handle library symbols
if(pc->Model == "Lib") {
if(LibComp* lib = dynamic_cast</*const*/LibComp*>(pc)) {
if(creatingLib) {
ErrText->appendPlainText(
QObject::tr("WARNING: Skipping library component \"%1\".").
arg(pc->Name));
continue;
}
s = pc->getSubcircuitFile() + "/" + pc->Props.at(1)->Value;
QString scfile = pc->getSubcircuitFile();
s = scfile + "/" + pc->Props.at(1)->Value;
SubMap::Iterator it = FileList.find(s);
if(it != FileList.end())
continue; // insert each library subcircuit just one time
FileList.insert(s, SubFile("LIB", s));
if(isAnalog)
r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 1);
else {
if(isVerilog)
r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 4);
else
r = ((LibComp*)pc)->createSubNetlist(stream, Collect, 2);
}
//FIXME: use different netlister for different purposes
unsigned whatisit = isAnalog?1:(isVerilog?4:2);
r = lib->createSubNetlist(stream, Collect, whatisit);
if(!r) {
ErrText->appendPlainText(
QObject::tr("ERROR: Cannot load library component \"%1\".").
arg(pc->Name));
QObject::tr("ERROR: \"%1\": Cannot load library component \"%2\" from \"%3\"").
arg(pc->Name, pc->Props.at(1)->Value, scfile));
return false;
}
continue;
@ -1355,7 +1351,9 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
SpiceFile *sf = (SpiceFile*)pc;
r = sf->createSubNetlist(stream);
ErrText->appendPlainText(sf->getErrorText());
if(!r) return false;
if(!r){
return false;
}
continue;
}
@ -1383,13 +1381,17 @@ bool Schematic::throughAllComps(QTextStream *stream, int& countInit,
VHDL_File *vf = (VHDL_File*)pc;
r = vf->createSubNetlist(stream);
ErrText->appendPlainText(vf->getErrorText());
if(!r) return false;
if(!r) {
return false;
}
}
if(pc->Model == "Verilog") {
Verilog_File *vf = (Verilog_File*)pc;
r = vf->createSubNetlist(stream);
ErrText->appendPlainText(vf->getErrorText());
if(!r) return false;
if(!r) {
return false;
}
}
continue;
}
@ -1426,8 +1428,10 @@ bool Schematic::giveNodeNames(QTextStream *stream, int& countInit,
}
// go through components
if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts))
if(!throughAllComps(stream, countInit, Collect, ErrText, NumPorts)){
fprintf(stderr, "Error: Could not go throughAllComps\n");
return false;
}
// work on named nodes first in order to preserve the user given names
throughAllNodes(true, Collect, countInit);
@ -1756,8 +1760,10 @@ bool Schematic::createSubNetlist(QTextStream *stream, int& countInit,
// int Collect_count = Collect.count(); // position for this subcircuit
// TODO: NodeSets have to be put into the subcircuit block.
if(!giveNodeNames(stream, countInit, Collect, ErrText, NumPorts))
if(!giveNodeNames(stream, countInit, Collect, ErrText, NumPorts)){
fprintf(stderr, "Error giving NodeNames in createSubNetlist\n");
return false;
}
/* Example for TODO
for(it = Collect.at(Collect_count); it != Collect.end(); )
@ -1851,11 +1857,14 @@ int Schematic::prepareNetlist(QTextStream& stream, QStringList& Collect,
}
int countInit = 0; // counts the nodesets to give them unique names
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts))
if(!giveNodeNames(&stream, countInit, Collect, ErrText, NumPorts)){
fprintf(stderr, "Error giving NodeNames\n");
return -10;
}
if(allTypes & isAnalogComponent)
if(allTypes & isAnalogComponent){
return NumPorts;
}
if (!isVerilog) {
stream << VHDL_LIBRARIES;
@ -1959,3 +1968,5 @@ QString Schematic::createNetlist(QTextStream& stream, int NumPorts)
return Time;
}
// vim:ts=8:sw=2:noet