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2009-10-24 Stefan Jahn <stefan@lkcc.org>

Browse Source 
* syntax.cpp (highlightParagraph): Added syntaxhighlighting for
        Verilog-A sources.

        * qucs.cpp (initContentListView): Added new 'Verilog-A' file
        content tab.  VA files can now be edited in builtin text editor.


git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1753 b5b04e8c-4942-46c9-ab4f-83783d557d1c
This commit is contained in:
ela 2009-10-24 20:41:14 +00:00
parent f001c03fde
commit f7d2a6a995
24 changed files with 358 additions and 60 deletions
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6
qucs/ChangeLog
View File

@ -1,5 +1,11 @@
2009-10-24 Stefan Jahn <stefan@lkcc.org>
* syntax.cpp (highlightParagraph): Added syntaxhighlighting for
Verilog-A sources.
* qucs.cpp (initContentListView): Added new 'Verilog-A' file
content tab. VA files can now be edited in builtin text editor.
* textdoc.cpp (becomeCurrent): Changing menu entry for skeleton
inserting depending on the language.
(commentSelected): Disabling code depending on language.

49
qucs/qucs.cpp
View File

@ -124,6 +124,7 @@ QucsApp::QucsApp()
tr("Qucs Documents")+" (*.sch *.dpl);;"+
tr("VHDL Sources")+" (*.vhdl *.vhd);;"+
tr("Verilog Sources")+" (*.v);;"+
tr("Verilog-A Sources")+" (*.va);;"+
tr("Any File")+" (*)";
QucsWorkDir.setPath(QDir::homeDirPath()+QDir::convertSeparators ("/.qucs"));
QucsHomeDir.setPath(QDir::homeDirPath()+QDir::convertSeparators ("/.qucs"));
@ -190,6 +191,7 @@ void QucsApp::initContentListView()
ConDatasets = new QListViewItem(Content, tr("Datasets"));
ConDisplays = new QListViewItem(Content, tr("Data Displays"));
ConVerilog = new QListViewItem(Content, tr("Verilog"));
ConVerilogA = new QListViewItem(Content, tr("Verilog-A"));
ConSources = new QListViewItem(Content, tr("VHDL"));
ConSchematics = new QListViewItem(Content, tr("Schematics"));
}
@ -619,6 +621,8 @@ QString QucsApp::fileType (const QString& Ext)
QString Type = tr("unknown");
if (Ext == "v")
Type = tr("Verilog source");
else if (Ext == "va")
Type = tr("Verilog-A source");
else if (Ext == "vhd" || Ext == "vhdl")
Type = tr("VHDL source");
else if (Ext == "dat")
@ -648,7 +652,7 @@ void QucsApp::slotCMenuDelGroup ()
const char * extensions[] =
{ "sch", "dpl", "dat", "vhdl", "vhd", "v", "sym",
"vhdl.cfg", "vhd.cfg", 0 };
"vhdl.cfg", "vhd.cfg", "va", 0 };
int i;
for (i = 0; extensions[i] != 0; i++) {
@ -831,17 +835,18 @@ void QucsApp::readProjectFiles()
delete ConSources->firstChild();
while(ConVerilog->firstChild())
delete ConVerilog->firstChild();
while(ConVerilogA->firstChild())
delete ConVerilogA->firstChild();
while(ConOthers->firstChild())
delete ConOthers->firstChild();
int n;
// put all files into "Content"-ListView
QStringList Elements = QucsWorkDir.entryList("*", QDir::Files, QDir::Name);
QStringList::iterator it;
QString Str;
for(it = Elements.begin(); it != Elements.end(); ++it) {
Str = (*it).section('.',1);
Str = QucsDoc::fileSuffix (*it);
if(Str == "sch") {
n = testFile(QucsWorkDir.filePath((*it).ascii()));
if(n >= 0) {
@ -859,6 +864,8 @@ void QucsApp::readProjectFiles()
new QListViewItem(ConSources, (*it).ascii());
else if(Str == "v")
new QListViewItem(ConVerilog, (*it).ascii());
else if(Str == "va")
new QListViewItem(ConVerilogA, (*it).ascii());
else
new QListViewItem(ConOthers, (*it).ascii());
}
@ -1203,6 +1210,7 @@ bool QucsApp::saveAs()
if(isTextDocument (w))
Filter = tr("VHDL Sources")+" (*.vhdl *.vhd);;" +
tr("Verilog Sources")+" (*.v);;"+
tr("Verilog-A Sources")+" (*.va);;"+
tr("Any File")+" (*)";
else
Filter = QucsFileFilter;
@ -1245,16 +1253,19 @@ bool QucsApp::saveAs()
if(Info.dirPath(true) == QucsWorkDir.absPath())
if(!ProjName.isEmpty()) {
s = Info.fileName(); // remove path from file name
if(Info.extension(false) == "sch")
QString ext = Info.extension (false);
if(ext == "sch")
Content->setSelected(new QListViewItem(ConSchematics, s), true);
else if(Info.extension(false) == "dpl")
else if(ext == "dpl")
Content->setSelected(new QListViewItem(ConDisplays, s), true);
else if(Info.extension(false) == "dat")
else if(ext == "dat")
Content->setSelected(new QListViewItem(ConDatasets, s), true);
else if((Info.extension(false) == "vhdl") || (Info.extension(false) == "vhd"))
else if((ext == "vhdl") || (ext == "vhd"))
Content->setSelected(new QListViewItem(ConSources, s), true);
else if(Info.extension(false) == "v")
else if(ext == "v")
Content->setSelected(new QListViewItem(ConVerilog, s), true);
else if(ext == "va")
Content->setSelected(new QListViewItem(ConVerilogA, s), true);
else
Content->setSelected(new QListViewItem(ConOthers, s), true);
}
@ -1449,10 +1460,11 @@ void QucsApp::updatePortNumber(QucsDoc *currDoc, int No)
if(No<0) return;
QString pathName = currDoc->DocName;
QFileInfo Info(pathName);
QString ext = currDoc->fileSuffix ();
QFileInfo Info (pathName);
QString Model, File, Name = Info.fileName();
if(Info.extension() == "sch") {
if (ext == "sch") {
Model = "Sub";
// enter new port number into ListView
@ -1465,10 +1477,10 @@ void QucsApp::updatePortNumber(QucsDoc *currDoc, int No)
}
}
}
else if(Info.extension() == "vhdl" || Info.extension() == "vhd") {
else if (ext == "vhdl" || ext == "vhd") {
Model = "VHDL";
}
else if(Info.extension() == "v") {
else if (ext == "v") {
Model = "Verilog";
}
@ -1811,12 +1823,11 @@ void QucsApp::slotChangePage(QString& DocName, QString& DataDisplay)
if(d)
DocumentTab->setCurrentPage(z);
else { // no open page found ?
if(DataDisplay.section('.',1).left(3) != "vhd" &&
DataDisplay.section('.',1).left(4) != "vhdl" &&
DataDisplay.section('.',1).left(1) != "v")
d = new Schematic(this, Name);
QString ext = QucsDoc::fileSuffix (DataDisplay);
if (ext != "vhd" && ext != "vhdl" && ext != "v" && ext != "va")
d = new Schematic (this, Name);
else
d = new TextDoc(this, Name);
d = new TextDoc (this, Name);
QFile file(Name);
if(file.open(IO_ReadOnly)) { // try to load document
@ -1890,8 +1901,8 @@ void QucsApp::slotOpenContent(QListViewItem *item)
QFileInfo Info(QucsWorkDir.filePath(item->text(0)));
QString Suffix = Info.extension(false);
if(Suffix == "sch" || Suffix == "dpl" || Suffix.left(3) == "vhd" ||
Suffix == "v") {
if (Suffix == "sch" || Suffix == "dpl" || Suffix == "vhdl" ||
Suffix == "v" || Suffix == "va") {
gotoPage(Info.absFilePath());
if(item->text(1).isEmpty()) // is subcircuit ?

2
qucs/qucs.h
View File

@ -166,7 +166,7 @@ private:
QListBox *Projects;
QListView *Content;
QListViewItem *ConSchematics, *ConSources, *ConDisplays, *ConDatasets,
*ConOthers, *ConVerilog;
*ConOthers, *ConVerilog, *ConVerilogA;
QComboBox *CompChoose;

12
qucs/qucs_ar.ts
View File

@ -8979,6 +8979,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_ca.ts
View File

@ -9669,6 +9669,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_cs.ts
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@ -10072,6 +10072,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_de.ts
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@ -10134,6 +10134,18 @@ Konvertiert Datendatei in verschiedene Datenformate</translation>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_es.ts
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@ -9701,6 +9701,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_fr.ts
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@ -9765,6 +9765,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_he.ts
View File

@ -9398,6 +9398,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_hu.ts
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@ -9755,6 +9755,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_it.ts
View File

@ -10123,6 +10123,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_jp.ts
View File

@ -9604,6 +9604,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_kk.ts
View File

@ -8915,6 +8915,18 @@ Trolltech Qt жайлы</translation>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_pl.ts
View File

@ -9752,6 +9752,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_pt.ts
View File

@ -8888,6 +8888,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_ro.ts
View File

@ -9488,6 +9488,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_ru.ts
View File

@ -10115,6 +10115,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_sv.ts
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@ -9368,6 +9368,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_tr.ts
View File

@ -9454,6 +9454,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

12
qucs/qucs_uk.ts
View File

@ -9575,6 +9575,18 @@ Convert data file to various file formats</source>
<source>Cannot delete %1: `%2&apos;!</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A Sources</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A</source>
<translation type="unfinished"></translation>
</message>
<message>
<source>Verilog-A source</source>
<translation type="unfinished"></translation>
</message>
</context>
<context>
<name>QucsAttenuator</name>

3
qucs/schematic_element.cpp
View File

@ -2243,7 +2243,8 @@ Component* Schematic::searchSelSubcircuit()
for(Component *pc = Components->first(); pc != 0; pc = Components->next()) {
if(!pc->isSelected) continue;
if(pc->Model != "Sub")
if(pc->Model != "VHDL") continue;
if(pc->Model != "VHDL")
if(pc->Model != "Verilog") continue;
if(sub != 0) return 0; // more than one subcircuit selected
sub = pc;

140
qucs/syntax.cpp
View File

@ -139,7 +139,8 @@ int SyntaxHighlighter::highlightParagraph(const QString& text, int state)
continue;
}
// ----- maybe a Verilog comment -------------------------------
else if(language == LANG_VERILOG && c == '/') {
else if((language == LANG_VERILOG || language == LANG_VERILOGA)
&& c == '/') {
if(i > 0)
if(text.at(i-1) == '/') { // Verilog comment starts with //
setFormat(i-1, text.length()-i, QucsSettings.VHDL_Comment);
@ -149,9 +150,11 @@ int SyntaxHighlighter::highlightParagraph(const QString& text, int state)
}
// ----- no special syntax yet (or anymore) --------------
else {
if(language == LANG_VERILOG && c == '`' && text.at(i+1).isLetter())
if((language == LANG_VERILOG || language == LANG_VERILOGA)
&& c == '`' && text.at(i+1).isLetter())
iWord = i;
else if(language == LANG_VERILOG && c == '$' && text.at(i+1).isLetter())
else if((language == LANG_VERILOG || language == LANG_VERILOGA)
&& c == '$' && text.at(i+1).isLetter())
iWord = i;
else if(c.isLetter())
iWord = i; // start a word
@ -174,8 +177,8 @@ int SyntaxHighlighter::highlightParagraph(const QString& text, int state)
else if(c == '"')
iString = i;
}
if (language == LANG_VERILOG &&
i > 0 && c == '*' && text.at(i-1) == '(') {
if ((language == LANG_VERILOG || language == LANG_VERILOGA)
&& i > 0 && c == '*' && text.at(i-1) == '(') {
if (state >= STATE_COMMENT) state++;
else state = STATE_COMMENT;
iComment = i-1;
@ -291,6 +294,54 @@ pChar V_List_Functions[] =
"stime", "realtime", "timeformat", "printtimescale", "random", "readmemb",
"readmemh", "finish", "stop", 0};
// ---------------------------------------------------
// reserved Verilog-A words in alphabetical order
pChar VA_List_A[] = {"abstol", "access", "analog", "ac_stim", "analysis", 0};
pChar VA_List_B[] = {"begin", "branch", "bound_step", 0};
pChar VA_List_C[] = {"case", 0};
pChar VA_List_D[] = {"discipline", "ddt_nature", "ddt", "delay",
"discontinuity", "default", 0 };
pChar VA_List_E[] = {"enddiscipline", "else", "end", "endnature", "exclude",
"endfunction", "endmodule", "electrical", "endcase", 0};
pChar VA_List_F[] = {"for", "flow", "from", "final_step", "flicker_noise",
"function", 0};
pChar VA_List_G[] = {"generate", "ground", 0};
pChar VA_List_I[] = {"if", "idt_nature", "inf", "idt", "initial_step",
"input", "inout", 0};
pChar VA_List_L[] = {"laplace_nd", "laplace_np", "laplace_zd", "laplace_zp",
"last_crossing", 0};
pChar VA_List_M[] = {"module", 0};
pChar VA_List_N[] = {"nature", "noise_table", 0};
pChar VA_List_P[] = {"potential", "parameter", 0};
pChar VA_List_S[] = {"slew", 0};
pChar VA_List_T[] = {"timer", "transition", 0};
pChar VA_List_U[] = {"units", 0};
pChar VA_List_W[] = {"white_noise", "while", 0};
pChar VA_List_Z[] = {"zi_nd", "zi_np", "zi_zd", "zi_zp", 0};
ppChar VA_WordList[] =
{(ppChar)&VA_List_A, (ppChar)&VA_List_B, (ppChar)&VA_List_C,
(ppChar)&VA_List_D, (ppChar)&VA_List_E, (ppChar)&VA_List_F,
(ppChar)&VA_List_G, 0, (ppChar)&VA_List_I,
0, 0, (ppChar)&VA_List_L,
(ppChar)&VA_List_M, (ppChar)&VA_List_N, 0,
(ppChar)&VA_List_P, 0, 0,
(ppChar)&VA_List_S, (ppChar)&VA_List_T, (ppChar)&VA_List_U,
0, (ppChar)&VA_List_W, 0,
0, (ppChar)&VA_List_Z };
pChar VA_List_Units[] =
{"T", "G", "M", "K", "m", "u", "n", "p", "f", "a", 0};
pChar VA_List_Directives[] =
{"define", "else", "undef", "ifdef", "endif", "include", "resetall", 0};
pChar VA_List_DataTypes[] = {
"integer", "real", 0};
pChar VA_List_Functions[] =
{"realtime", "temperature", "vt", "display", "strobe", 0};
// ---------------------------------------------------
void SyntaxHighlighter::markWord(const QString& text, int start, int len)
{
@ -324,7 +375,7 @@ void SyntaxHighlighter::markWord(const QString& text, int start, int len)
List = V_WordList[idx];
break;
default:
List = 0;
List = VA_WordList[idx];;
break;
}
@ -347,7 +398,7 @@ void SyntaxHighlighter::markWord(const QString& text, int start, int len)
List = V_List_DataTypes;
break;
default:
List = 0;
List = VA_List_DataTypes;
break;
}
if(List)
@ -361,6 +412,10 @@ void SyntaxHighlighter::markWord(const QString& text, int start, int len)
switch (language) {
case LANG_VHDL:
List = VHD_List_Units;
break;
case LANG_VERILOGA:
List = VA_List_Units;
break;
default:
List = 0;
break;
@ -374,41 +429,48 @@ void SyntaxHighlighter::markWord(const QString& text, int start, int len)
}
if (Word.at(0) == '`' || Word.at(0) == '$')
if (Word.at(0) == '`' || Word.at(0) == '$') {
Word = Word.mid(1);
// mark directives
switch (language) {
case LANG_VERILOG:
List = V_List_Directives;
break;
default:
List = 0;
break;
}
if(List)
for( ; *List != 0; List++)
if(Word == *List) {
newFont.setWeight(QFont::Bold);
setFormat(start, len, newFont, QucsSettings.VHDL_Attributes);
return;
}
// mark directives
switch (language) {
case LANG_VERILOG:
List = V_List_Directives;
break;
case LANG_VERILOGA:
List = VA_List_Directives;
break;
default:
List = 0;
break;
}
if(List)
for( ; *List != 0; List++)
if(Word == *List) {
newFont.setWeight(QFont::Bold);
setFormat(start, len, newFont, QucsSettings.VHDL_Attributes);
return;
}
// mark special functions
switch (language) {
case LANG_VERILOG:
List = V_List_Functions;
break;
default:
List = 0;
break;
// mark special functions
switch (language) {
case LANG_VERILOG:
List = V_List_Functions;
break;
case LANG_VERILOGA:
List = VA_List_Functions;
break;
default:
List = 0;
break;
}
if(List)
for( ; *List != 0; List++)
if(Word == *List) {
newFont.setWeight(QFont::Bold);
setFormat(start, len, newFont, QucsSettings.VHDL_Types);
return;
}
}
if(List)
for( ; *List != 0; List++)
if(Word == *List) {
newFont.setWeight(QFont::Bold);
setFormat(start, len, newFont, QucsSettings.VHDL_Types);
return;
}
}
// ---------------------------------------------------

2
qucs/textdoc.cpp
View File

@ -207,6 +207,8 @@ void TextDoc::becomeCurrent (bool)
App->insEntity->setWhatsThis (
tr("Verilog entity\n\nInserts the skeleton of a Verilog module"));
}
App->simulate->setEnabled (true);
App->editActivate->setEnabled (true);
}
// ---------------------------------------------------