SIM/qucs_s
1
0
Fork 0
mirror of https://github.com/ra3xdh/qucs_s synced 2025-03-28 21:13:26 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update digital libraries

Browse Source
This commit is contained in:
Vadim Kuznetsov 2025-01-05 11:19:59 +03:00
parent 38434ff353
commit fbcb9da573
6 changed files with 1814 additions and 737 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/CMakeLists.txt
View File

@ -9,7 +9,7 @@ Crystal.lib
Diodes.lib
DiodesSchottky.lib
Diodes_Extended.lib
Digital_CD4000.lib
Digital_CD.lib
Digital_HC.lib
Digital_LV.lib
GeDiodes.lib

698
library/Digital_CD4000.lib
View File

@ -1,698 +0,0 @@
<Qucs Library 24.4.1 "Digital_CD4000">
<Component CD4011>
<Description>
Quad 2-Input CMOS NAND
</Description>
<Model>
.Def:Digital_CD4000_CD4011 _net0 _net2 _net1
Sub:X1 _net0 _net2 _net1 gnd Type="CD4011_cir"
.Def:End
</Model>
<ModelIncludes "CD4011.cir.lst">
<Spice>
* ----------------------- CD4011B -------------------------
*
* Quad 2-Input NAND Gate
*
* The CMOS Logic Data Book, 1991, Motorola Pages 6-5 to 6-14
* jds 6/6/94
* This part is shown in the data book as MC14011B
*
.SUBCKT CD4011B IN1A IN2A OUTA
+ optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ params: MNTYMXDLY=0 IO_LEVEL=0
*
Uf0 nand(2) VDD VSS
+ IN1A IN2A OUTA
+ DLY_MOD IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (TPLHMN=-1 TPLHTY=125ns TPLHMX=250ns
+ TPHLMN=-1 TPHLTY=125ns TPHLMX=250ns)
.ENDS CD4011B
*
.SUBCKT Digital_CD4000_CD4011 gnd _net0 _net2 _net1
X1 _net0 _net2 _net1 CD4011B
.ENDS
</Spice>
<Symbol>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Line -10 20 0 -40 #000080 2 1>
<Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
<Line 10 0 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
<Line -30 10 20 0 #000080 2 1>
<.PortSym -30 -10 1 0 P1>
<.PortSym -30 10 2 0 P2>
<.PortSym 30 0 3 180 P3>
<.ID 10 14 Y>
</Symbol>
</Component>
<Component CD4013>
<Description>
Two D-type CMOS Flip-flops
</Description>
<Model>
.Def:Digital_CD4000_CD4013 _net0 _net1 _net2 _net3 _net4 _net5
Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 gnd Type="CD4013_cir"
.Def:End
</Model>
<ModelIncludes "CD4013.cir.lst">
<Spice>
* ----------------------------- CD4013B ------------------------
*
* Dual Type D Flip-Flop
*
* The CMOS Logic Data Book, 1991, Motorola Pages 6-33 to 6-36
* jds 6/6/94
* This part is shown in the data book as MC14013B
*
.SUBCKT CD4013B SA RA CA DA QA QABAR
+ optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ params: MNTYMXDLY=0 IO_LEVEL=0
*
Uf0 inva(2) VDD VSS
+ SA RA prebar clrbar
+ D0_GATE IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf1 dff(1) VDD VSS
+ prebar clrbar CA DA Q_A Q_ABAR
+ DFF4013B IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DFF4013B UEFF(TWPCLMN=250NS TWPCLTY=125NS TWPCLMX=-1
+ TWCLKLMN=250NS TWCLKLTY=125NS TWCLKLMX=-1
+ TWCLKHMN=250NS TWCLKHTY=125NS TWCLKHMX=-1
+ TSUDCLKMN=-1NS TSUDCLKTY=250NS TSUDCLKMX=-1
+ THDCLKMN=40NS THDCLKTY=20NS THDCLKMX=-1)
U3 PINDLY(2,0,3) VDD VSS
+ Q_A Q_ABAR
+ CA SA RA
+ QA QABAR
+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+ EDGE = {CHANGED_LH(CA,0)}
+ SET = {CHANGED_LH(SA,0)}
+ CLEAR = {CHANGED_LH(RA,0)}
+ PINDLY:
+ QA QABAR = {
+ CASE(
+ SET, DELAY(-1,175NS,350NS),
+ CLEAR, DELAY(-1,225NS,450NS),
+ EDGE & (TRN_LH | TRN_HL), DELAY(-1,175NS,350NS),
+ DELAY(-1,226NS,451NS))}
U4 CONSTRAINT(3) VDD VSS
+ CA SA RA
+ IO_4000B IO_LEVEL={IO_LEVEL}
+ FREQ:
+ NODE = CA
+ MAXFREQ = 2MEG
+ SETUP_HOLD:
+ CLOCK LH = CA
+ DATA(2) = SA RA
+ SETUPTIME_LO = 80NS
+ HOLDTIME_LO = 50NS
.ENDS CD4013B
*
.SUBCKT Digital_CD4000_CD4013 gnd _net0 _net1 _net2 _net3 _net4 _net5
X1 _net0 _net1 _net2 _net3 _net4 _net5 CD4013B
.ENDS
</Spice>
<Symbol>
<Rectangle -30 -40 60 80 #000080 2 1 #c0c0c0 1 0>
<Line -50 20 20 0 #000080 2 1>
<Line -50 -20 20 0 #000080 2 1>
<Line 30 -20 20 0 #000080 2 1>
<Line 0 -40 0 -20 #000080 2 1>
<Line 30 20 20 0 #000080 2 1>
<Line 14 11 12 0 #000080 2 1>
<Line -15 20 -15 -10 #000080 2 1>
<Line -30 30 15 -10 #000080 2 1>
<.PortSym -50 20 3 0 CA>
<.PortSym -50 -20 4 0 DA>
<.PortSym 50 -20 5 180 QA>
<.PortSym 50 20 6 180 QAB>
<.PortSym 0 -60 2 0 RA>
<.PortSym 0 60 1 0 SA>
<Line 0 61 0 -20 #000080 2 1>
<.ID 20 44 Y>
<Text -4 -40 12 #000080 0 "R">
<Text -4 18 12 #000080 0 "S">
<Text -27 -30 12 #000080 0 "D">
<Text 14 -30 12 #000080 0 "Q">
<Text 14 10 12 #000080 0 "Q">
</Symbol>
</Component>
<Component CD4017>
<Description>
Decade counter with 10 decoded outputs
</Description>
<Model>
.Def:Digital_CD4000_CD4017 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12
Sub:X1 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 gnd Type="CD4017_cir"
.Def:End
</Model>
<ModelIncludes "CD4017.cir.lst">
<Spice>
* ------------------- CD4017B----------------
*
* Decade Counter
*
* The CMOS Logic Data Book, 1991, Motorola Pages 6-54 to 6-58
* jds 6/6/94
* This part is shown in the data book as MC14017B
* Note that the NAND gate feeding into the 3rd flip-flops D input should
* be an AND gate for the circuit to operate as in the timing diagram.
*
.SUBCKT CD4017B CLK CLKENBAR RESET COUT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
+ optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ params: MNTYMXDLY=0 IO_LEVEL=0
U14017B LOGICEXP(13,14) VDD VSS
+ CLK CLKENBAR RESET q1ff q2ff q3ff q4ff q5ff
+ q1ffbar q2ffbar q3ffbar q4ffbar q5ffbar
+ clock clear i1
+ COUT_O Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O Q8_O Q9_O
+ D0_GATE IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ LOGIC:
+ clock = {( CLK & ~CLKENBAR )}
+ clear = { (~RESET) }
+ i1 = { (q2ff & (q1ff | q3ff)) }
+ Q0_O = { (q1ffbar & q5ffbar) }
+ Q1_O = { (q1ff & q2ffbar) }
+ Q2_O = { (q2ff & q3ffbar) }
+ Q3_O = { (q3ff & q4ffbar) }
+ Q4_O = { (q4ff & q5ffbar) }
+ Q5_O = { (q1ff & q5ff) }
+ Q6_O = { (q1ffbar & q2ff) }
+ Q7_O = { (q2ffbar & q3ff) }
+ Q8_O = { (q3ffbar & q4ff) }
+ Q9_O = { (q5ff & q4ffbar) }
+ COUT_O = { q5ffbar }
Uf0 dff(5) VDD VSS
+ $D_HI clear clock q5ffbar q1ff i1 q3ff q4ff
+ q1ff q2ff q3ff q4ff q5ff q1ffbar q2ffbar q3ffbar q4ffbar q5ffbar
+ DLY_DFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_DFF UEFF(TWCLKLMN=-1 TWCLKLTY=125NS TWCLKLMX=250NS
+ TWCLKHMN=-1 TWCLKHTY=125NS TWCLKHMX=250NS)
Udly PINDLY (11,0,2) VDD VSS
+ COUT_O Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O Q8_O Q9_O
+ CLK RESET
+ COUT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ BOOLEAN:
+ CP = {CHANGED_LH(CLK,0)}
+ CLR = { CHANGED_LH(RESET,0) }
+
+ PINDLY:
+ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 = {
+ CASE(
+ CLR, DELAY(-1,500ns,1us),
+ CP, DELAY(-1,500ns,1us),
+ DELAY(-1,501ns,1.001us)
+ )
+ }
+ COUT = {
+ CASE(
+ CLR, DELAY(-1,400ns,800ns),
+ CP, DELAY(-1,400ns,800ns),
+ DELAY(-1,401ns,801ns)
+ )
+ }
Ucnstr CONSTRAINT(3) VDD VSS
+ CLKENBAR CLK RESET
+ IO_4000B
+
+ FREQ:
+ NODE = CLK
+ MAXFREQ = 5MEG
+ WIDTH:
+ NODE = RESET
+ MIN_HI = 250ns
+ SETUP_HOLD:
+ CLOCK LH = CLK
+ DATA(1) = CLKENBAR
+ SETUPTIME_HI = 175ns
+ SETUPTIME_LO = 260ns
+ WHEN = { RESET != '1 }
+ SETUP_HOLD:
+ CLOCK LH = CLK
+ DATA(1) = RESET
+ SETUPTIME_LO = 375ns
.ENDS CD4017B
*
.SUBCKT Digital_CD4000_CD4017 gnd _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12
X1 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 CD4017B
.ENDS
</Spice>
<Symbol>
<Line 30 20 20 0 #000080 2 1>
<Text 4 -11 12 #000080 0 "Q0">
<Text 4 29 12 #000080 0 "Q2">
<Text 4 49 12 #000080 0 "Q3">
<Text 4 69 12 #000080 0 "Q4">
<Rectangle -30 -20 60 250 #000080 2 1 #c0c0c0 1 0>
<Line 30 0 20 0 #000080 2 1>
<Text 4 109 12 #000080 0 "Q6">
<Text 4 129 12 #000080 0 "Q7">
<Line 30 60 20 0 #000080 2 1>
<Line 30 40 20 0 #000080 2 1>
<Line 30 100 20 0 #000080 2 1>
<Line 30 80 20 0 #000080 2 1>
<Line 30 140 20 0 #000080 2 1>
<Line 30 120 20 0 #000080 2 1>
<Line 30 160 20 0 #000080 2 1>
<Line 30 180 20 0 #000080 2 1>
<Text 4 169 12 #000080 0 "Q9">
<Line -50 0 20 0 #000080 2 1>
<Line -15 0 -15 -10 #000080 2 1>
<Line -30 10 15 -10 #000080 2 1>
<.PortSym -50 0 1 0 CLK>
<Line -50 60 20 0 #000080 2 1>
<Text -28 50 12 #000080 0 "RST">
<.PortSym 50 0 5 180 Q0>
<.PortSym 50 20 6 180 Q1>
<.PortSym 50 40 7 180 Q2>
<.PortSym 50 60 8 180 Q3>
<.PortSym 50 80 9 180 Q4>
<.PortSym 50 100 10 180 Q5>
<.PortSym 50 120 11 180 Q6>
<.PortSym 50 140 12 180 Q7>
<.PortSym 50 160 13 180 Q8>
<.PortSym 50 180 14 180 Q9>
<Text 4 9 12 #000080 0 "Q1">
<Text 4 89 12 #000080 0 "Q5">
<Text 4 149 12 #000080 0 "Q8">
<.ID -10 234 Y>
<.PortSym -50 60 3 0 RST>
<Text -28 10 12 #000080 0 "ENB">
<.PortSym -50 20 2 0 CLKENB>
<Line 30 210 20 0 #000080 2 1>
<Text -16 199 12 #000080 0 "COUT">
<.PortSym 50 210 4 180 COUT>
<Line -50 20 20 0 #000080 2 1>
<Ellipse -31 16 -8 8 #000080 1 1 #000080 1 1>
</Symbol>
</Component>
<Component CD4022>
<Description>
Octal counter with 8 decoded outputs
</Description>
<Model>
.Def:Digital_CD4000_CD4022 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10
Sub:X1 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 gnd Type="CD4022_cir"
.Def:End
</Model>
<ModelIncludes "CD4022.cir.lst">
<Spice>
*---------------------------CD4022B----------------------------------
*
* Divide by 8 Counter/Divider with 8 Decoded Outputs
* National Semiconductor, CMOS Logic Databook, 1988, pages 5-57 to 5-62
* jat 8/18/95
* Note that there should only be a single inversion in front of COUT, not
* a double inversion as shown in the logic diagram.
.SUBCKT CD4022B
+ CLK CLKENBAR RESET COUT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
+ OPTIONAL: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(11,12) VDD VSS
+ CLK CLKENBAR RESET Q1FF Q2FF Q3FF Q4FF Q1FFBAR Q2FFBAR Q3FFBAR Q4FFBAR
+ CLOCK CLEAR D3 COUT_O Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O
+ D0_GATE IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+ CLOCK = {(CLK & (~CLKENBAR))}
+ CLEAR = {(~RESET)}
+ D3 = {~(Q2FFBAR | (~(Q1FF | Q2FFBAR | Q3FF)))}
+ Q0_O = {(Q1FFBAR & Q4FFBAR) }
+ Q1_O = {(Q1FF & Q2FFBAR)}
+ Q2_O = {(Q2FF & Q3FFBAR)}
+ Q3_O = {(Q3FF & Q4FFBAR)}
+ Q4_O = {(Q1FF & Q4FF)}
+ Q5_O = {(Q1FFBAR & Q2FF)}
+ Q6_O = {(Q2FFBAR & Q3FF)}
+ Q7_O = {(Q3FFBAR & Q4FF)}
+ COUT_O = {~Q4FF}
U2 DFF(4) VDD VSS
+ $D_HI CLEAR CLOCK
+ Q4FFBAR Q1FF D3 Q3FF
+ Q1FF Q2FF Q3FF Q4FF Q1FFBAR Q2FFBAR Q3FFBAR Q4FFBAR
+ DLY_DFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_DFF UEFF(TWCLKLMN=-1 TWCLKLTY=125NS TWCLKLMX=250NS
+ TWCLKHMN=-1 TWCLKHTY=125NS TWCLKHMX=250NS)
U3 PINDLY(9,0,2) VDD VSS
+ COUT_O Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O
+ CLK RESET
+ COUT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+ EDGE = {CHANGED_LH(CLK,0)}
+ CLR = {CHANGED_LH(RESET,0)}
+ PINDLY:
+ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = {
+ CASE(
+ EDGE & (TRN_LH | TRN_HL), DELAY(-1,500NS,1000NS),
+ CLR & (TRN_LH | TRN_HL), DELAY(-1,500NS,1000NS),
+ DELAY(-1,501NS,1001NS))}
+ COUT = {
+ CASE(
+ EDGE & (TRN_LH | TRN_HL), DELAY(-1,415NS,800NS),
+ CLR & (TRN_LH | TRN_HL), DELAY(-1,415NS,800NS),
+ DELAY(-1,416NS,801NS))}
U4 CONSTRAINT(3) VDD VSS
+ CLKENBAR CLK RESET
+ IO_4000B IO_LEVEL={IO_LEVEL}
+ FREQ:
+ NODE = CLK
+ MAXFREQ = 2MEG
+ WIDTH:
+ NODE = RESET
+ MIN_HI = 200NS
+ SETUP_HOLD:
+ CLOCK LH = CLK
+ DATA(1) = CLKENBAR
+ SETUPTIME_HI = 120NS
+ WHEN = { RESET != '1 }
+ SETUP_HOLD:
+ CLOCK LH = CLK
+ DATA(1) = RESET
+ SETUPTIME_LO = 75NS
.ENDS CD4022B
.SUBCKT Digital_CD4000_CD4022 gnd _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10
X1 _net11 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 CD4022B
.ENDS
</Spice>
<Symbol>
<Line 30 20 20 0 #000080 2 1>
<Text 4 -11 12 #000080 0 "Q0">
<Text 4 29 12 #000080 0 "Q2">
<Text 4 49 12 #000080 0 "Q3">
<Text 4 69 12 #000080 0 "Q4">
<Rectangle -30 -20 60 220 #000080 2 1 #c0c0c0 1 0>
<Line 30 0 20 0 #000080 2 1>
<Text 4 109 12 #000080 0 "Q6">
<Text 4 129 12 #000080 0 "Q7">
<Line 30 60 20 0 #000080 2 1>
<Line 30 40 20 0 #000080 2 1>
<Line 30 100 20 0 #000080 2 1>
<Line 30 80 20 0 #000080 2 1>
<Line 30 140 20 0 #000080 2 1>
<Line 30 120 20 0 #000080 2 1>
<Line 30 180 20 0 #000080 2 1>
<Line -50 0 20 0 #000080 2 1>
<Line -15 0 -15 -10 #000080 2 1>
<Line -30 10 15 -10 #000080 2 1>
<.PortSym -50 0 1 0 CLK>
<Line -50 60 20 0 #000080 2 1>
<Text -28 50 12 #000080 0 "RST">
<.PortSym 50 0 5 180 Q0>
<.PortSym 50 20 6 180 Q1>
<.PortSym 50 40 7 180 Q2>
<.PortSym 50 60 8 180 Q3>
<.PortSym 50 80 9 180 Q4>
<.PortSym 50 100 10 180 Q5>
<.PortSym 50 120 11 180 Q6>
<.PortSym 50 140 12 180 Q7>
<Text 4 9 12 #000080 0 "Q1">
<Text 4 89 12 #000080 0 "Q5">
<.PortSym -50 60 3 0 RST>
<Text -28 10 12 #000080 0 "ENB">
<.PortSym -50 20 2 0 CLKENB>
<Line -50 20 20 0 #000080 2 1>
<Ellipse -31 16 -8 8 #000080 1 1 #000080 1 1>
<Text -16 169 12 #000080 0 "COUT">
<.PortSym 50 180 4 180 COUT>
<.ID -10 204 Y>
</Symbol>
</Component>
<Component CD4040>
<Description>
</Description>
<Model>
.Def:Digital_CD4000_CD4040 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
Sub:X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="CD4040_cir"
.Def:End
</Model>
<ModelIncludes "CD4040.cir.lst">
<Spice>
* ----------------------- CD4040B -----------------------
*
* 12-Stage Binary Counter
*
* The CMOS Logic Data Book, 1991, Motorola Pages 6-108 to 6-111
* jds 6/8/94
* This part is shown in the data book as MC14040B
*
.SUBCKT CD4040B CLK RESET Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
+ optional: VDD=$G_CD4000_VDD VSS=$G_CD4000_VSS
+ params: MNTYMXDLY=0 IO_LEVEL=0
USTBUF BUF VDD VSS
+ CLK CLKST
+ D0_GATE IO_4000B_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
uf0 inv VDD VSS
+ RESET clr
+ D0_GATE IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf1 jkff(1) VDD VSS
+ $D_HI clr CLKST $D_HI $D_HI Q1_O Q1BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf2 jkff(1) VDD VSS
+ $D_HI clr Q1_O $D_HI $D_HI Q2_O Q2BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf3 jkff(1) VDD VSS
+ $D_HI clr Q2_O $D_HI $D_HI Q3_O Q3BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf4 jkff(1) VDD VSS
+ $D_HI clr Q3_O $D_HI $D_HI Q4_O Q4BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf5 jkff(1) VDD VSS
+ $D_HI clr Q4_O $D_HI $D_HI Q5_O Q5BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf6 jkff(1) VDD VSS
+ $D_HI clr Q5_O $D_HI $D_HI Q6_O Q6BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf7 jkff(1) VDD VSS
+ $D_HI clr Q6_O $D_HI $D_HI Q7_O Q7BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf8 jkff(1) VDD VSS
+ $D_HI clr Q7_O $D_HI $D_HI Q8_O Q8BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf9 jkff(1) VDD VSS
+ $D_HI clr Q8_O $D_HI $D_HI Q9_O Q9BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf10 jkff(1) VDD VSS
+ $D_HI clr Q9_O $D_HI $D_HI Q10_O Q10BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf11 jkff(1) VDD VSS
+ $D_HI clr Q10_O $D_HI $D_HI Q11_O Q11BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Uf12 jkff(1) VDD VSS
+ $D_HI clr Q11_O $D_HI $D_HI Q12_O Q12BAR_O
+ D0_EFF IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
Udly PINDLY (12,0,13) VDD VSS
+ Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O Q8_O Q9_O Q10_O Q11_O Q12_O
+ CLK RESET Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR Q6BAR Q7BAR
+ Q8BAR Q9BAR Q10BAR Q11BAR
+ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
+ IO_4000B MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ PINDLY:
+ Q1 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(CLK,0), DELAY(-1,260ns,520ns),
+ DELAY(-1,261ns,521ns)
+ )
+ }
+ Q2 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q1_O,0), DELAY(-1,384.1ns,768.2ns),
+ DELAY(-1,385.1ns,769.2ns)
+ )
+ }
+ Q3 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q2_O,0), DELAY(-1,508.2ns,1016.4ns),
+ DELAY(-1,509.2ns,1017.4ns)
+ )
+ }
+ Q4 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q3_O,0), DELAY(-1,632.3ns,1264.6ns),
+ DELAY(-1,633.3ns,1265.6ns)
+ )
+ }
+ Q5 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q4_O,0), DELAY(-1,756.4ns,1512.8ns),
+ DELAY(-1,757.4ns,1513.8ns)
+ )
+ }
+ Q6 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q5_O,0), DELAY(-1,880.5ns,1761ns),
+ DELAY(-1,881.5ns,1762ns)
+ )
+ }
+ Q7 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q6_O,0), DELAY(-1,1004.6ns,2009.2ns),
+ DELAY(-1,1005.6ns,2010.2ns)
+ )
+ }
+ Q8 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q7_O,0), DELAY(-1,1128.7ns,2257.4ns),
+ DELAY(-1,1129.7ns,2258.4ns)
+ )
+ }
+ Q9 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q8_O,0), DELAY(-1,1252.8ns,2505.6ns),
+ DELAY(-1,1253.8ns,2506.6ns)
+ )
+ }
+ Q10 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q9_O,0), DELAY(-1,1376.9ns,2753.8ns),
+ DELAY(-1,1377.9ns,2754.8ns)
+ )
+ }
+ Q11 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q10_O,0), DELAY(-1,1501ns,3002ns),
+ DELAY(-1,1502ns,3003ns)
+ )
+ }
+ Q12 = {
+ CASE(
+ CHANGED(RESET,0) & TRN_HL, DELAY(-1,370ns,740ns),
+ CHANGED_HL(Q11_O,0), DELAY(-1,1625ns,3250ns),
+ DELAY(-1,1626ns,3251ns)
+ )
+ }
Ucnstr CONSTRAINT(2) VDD VSS
+ CLK RESET
+ IO_4000B
+
+ FREQ:
+ NODE = CLK
+ MAXFREQ = 2.1MEG
+ WIDTH:
+ NODE = CLK
+ MIN_HI = 140ns
+ WIDTH:
+ NODE = RESET
+ MIN_HI = 320ns
+ SETUP_HOLD:
+ CLOCK HL = CLK
+ DATA(1) = RESET
+ SETUPTIME_LO = 65ns
.ENDS CD4040B
*
.SUBCKT Digital_CD4000_CD4040 gnd _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
X1 _net12 _net13 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 CD4040B
.ENDS
</Spice>
<Symbol>
<Line 30 20 20 0 #000080 2 1>
<Text 4 9 12 #000080 0 "QB">
<Text 4 -11 12 #000080 0 "QA">
<Text 4 29 12 #000080 0 "QC">
<Text 4 49 12 #000080 0 "QD">
<Text 4 69 12 #000080 0 "QE">
<Rectangle -30 -20 60 260 #000080 2 1 #c0c0c0 1 0>
<Line 30 0 20 0 #000080 2 1>
<Text 4 89 12 #000080 0 "QF">
<Text 4 109 12 #000080 0 "QG">
<Text 4 129 12 #000080 0 "QH">
<Line 30 60 20 0 #000080 2 1>
<Line 30 40 20 0 #000080 2 1>
<Line 30 100 20 0 #000080 2 1>
<Line 30 80 20 0 #000080 2 1>
<Line 30 140 20 0 #000080 2 1>
<Line 30 120 20 0 #000080 2 1>
<Line 30 160 20 0 #000080 2 1>
<Line 30 180 20 0 #000080 2 1>
<Line 30 200 20 0 #000080 2 1>
<Line 30 220 20 0 #000080 2 1>
<.PortSym 50 0 3 180 QA>
<.PortSym 50 20 4 180 QB>
<.PortSym 50 40 5 180 QC>
<.PortSym 50 60 6 180 QD>
<.PortSym 50 80 7 180 QE>
<.PortSym 50 100 8 180 QF>
<.PortSym 50 120 9 180 QG>
<.PortSym 50 140 10 180 QH>
<.PortSym 50 160 11 180 QI>
<.PortSym 50 180 12 180 QJ>
<Text 4 149 12 #000080 0 "QI">
<Text 4 169 12 #000080 0 "QJ">
<Text 4 189 12 #000080 0 "QK">
<Text 4 209 12 #000080 0 "QL">
<.ID -10 244 Y>
<.PortSym 50 200 13 180 QK>
<.PortSym 50 220 14 180 QL>
<Line -50 0 20 0 #000080 2 1>
<Line -15 0 -15 -10 #000080 2 1>
<Line -30 10 15 -10 #000080 2 1>
<Line -50 60 20 0 #000080 2 1>
<Text -28 50 12 #000080 0 "CLR">
<.PortSym -50 60 2 0 RES>
<.PortSym -50 0 1 0 CLK>
</Symbol>
</Component>

1028
library/Digital_HC.lib
View File

File diff suppressed because it is too large Load Diff

819
library/Digital_LV.lib
View File

@ -1,9 +1,9 @@
<Qucs Library 24.3.99 "Digital_LV">
<Qucs Library 24.4.99 "Digital_LV">
<Component 74LV00>
<Description>
2-Input Nand Gate
2-Input NAND Gate
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
@ -43,7 +43,6 @@ X1 _net0 _net1 _net2 74LV00A
</Spice>
<Symbol>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Line -10 20 0 -40 #000000 2 1>
<Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
<Line 10 0 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
@ -52,13 +51,280 @@ X1 _net0 _net1 _net2 74LV00A
<.PortSym -30 10 2 0 P2>
<.PortSym 30 0 3 180 P3>
<.ID 10 14 Y>
<Line -10 20 0 -40 #000080 2 1>
</Symbol>
</Component>
<Component 74LV02>
<Description>
2-Input NOR Gate
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV02 _net0 _net1 _net2
Sub:X1 _net0 _net1 _net2 gnd Type="n74LV02_cir"
.Def:End
</Model>
<ModelIncludes "74LV02.cir.lst">
<Spice>
* ---------------------------------- 74LV02A ---------------------
* Quad 2-Input Nor Gates
*
* TI PDF File
* bss 2/18/03
*
.SUBCKT 74LV02A 1A 1B 1Y
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR_3V DGND_3V
+ 1A 1B 1Y
+ DLY_LV02 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LV02 ugate (tplhTY=7.6ns tplhMX=11.4ns tphlTY=7.6ns tphlMX=11.4ns)
.ENDS 74LV02A
*
.SUBCKT Digital_LV_74LV02 gnd _net0 _net1 _net2
X1 _net0 _net1 _net2 74LV02A
.ENDS
</Spice>
<Symbol>
<.PortSym -30 -10 1 0 P1>
<.PortSym -30 10 2 0 P2>
<.PortSym 30 0 3 180 P3>
<.ID 10 14 Y>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
<Line 10 0 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
<Line -30 10 20 0 #000080 2 1>
<EArc -20 -20 10 40 4320 2880 #000080 2 1>
<Line -10 20 -5 0 #000080 2 1>
<Line -10 -20 -5 0 #000080 2 1>
</Symbol>
</Component>
<Component 74LV04>
<Description>
Inverter
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV04 _net0 _net1
Sub:X1 _net0 _net1 gnd Type="n74LV04_cir"
.Def:End
</Model>
<ModelIncludes "74LV04.cir.lst">
<Spice>
* -------------------------- 74LV04A --------------------------------
* Hex Inverters
*
* TI PDF File
* bss 1/2/03
*
.SUBCKT 74LV04A 1A 1Y
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR_3V DGND_3V
+ 1A 1Y
+ DLY_LV04 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LV04 ugate (tplhTY=7.3ns tplhMX=10.6ns tphlTY=7.3ns tphlMX=10.6ns)
.ENDS 74LV04A
*
.SUBCKT Digital_LV_74LV04 gnd _net0 _net1
X1 _net0 _net1 74LV04A
.ENDS
</Spice>
<Symbol>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Line -10 20 0 -40 #000080 2 1>
<Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
<Line 10 0 20 0 #000080 2 1>
<.ID 10 14 Y>
<.PortSym 30 0 2 180 P2>
<Line -30 0 20 0 #000080 2 1>
<.PortSym -30 0 1 0 P1>
</Symbol>
</Component>
<Component 74LV08>
<Description>
2-Input AND Gate
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV08 _net0 _net1 _net2
Sub:X1 _net0 _net1 _net2 gnd Type="n74LV08_cir"
.Def:End
</Model>
<ModelIncludes "74LV08.cir.lst">
<Spice>
* ---------------------------- 74LV08A ------------------------------
* Quad 2-Input AND Gate
*
* TI PDF File
* bss 2/21/03
*
.SUBCKT 74LV08A 1A 1B 1Y
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR_3V DGND_3V
+ 1A 1B 1Y
+ DLY_LV08 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LV08 ugate (tplhTY=7.5ns tplhMX=12.3ns tphlTY=7.5ns tphlMX=12.3ns)
.ENDS 74LV08A
*
.SUBCKT Digital_LV_74LV08 gnd _net0 _net1 _net2
X1 _net0 _net1 _net2 74LV08A
.ENDS
</Spice>
<Symbol>
<.PortSym -30 -10 1 0 P1>
<.PortSym -30 10 2 0 P2>
<.PortSym 30 0 3 180 P3>
<.ID 10 14 Y>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Line -10 20 0 -40 #000080 2 1>
<Line 10 0 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
<Line -30 10 20 0 #000080 2 1>
</Symbol>
</Component>
<Component 74LV20>
<Description>
4-Input NAND Gate
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV20 _net0 _net1 _net2 _net3 _net4
Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="n74LV20_cir"
.Def:End
</Model>
<ModelIncludes "74LV20.cir.lst">
<Spice>
* ----------------------------- 74LV20A -------------------------
* Dual 4-Input Nand Gate
*
* TI PDF File
* bss 2/24/03
*
.SUBCKT 74LV20A 1A 1B 1C 1D 1Y
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR_3V DGND_3V
+ 1A 1B 1C 1D 1Y
+ DLY_LV20 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LV20 ugate (tplhTY=6.5ns tplhMX=10.1ns tphlTY=6.5ns tphlMX=10.1ns)
.ENDS 74LV20A
*
.SUBCKT Digital_LV_74LV20 gnd _net0 _net1 _net2 _net3 _net4
X1 _net0 _net1 _net2 _net3 _net4 74LV20A
.ENDS
</Spice>
<Symbol>
<Line -30 -30 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
<Line -30 10 20 0 #000080 2 1>
<Line -30 30 20 0 #000080 2 1>
<Line -10 40 0 -80 #000080 2 1>
<Ellipse 20 -4 8 8 #000080 1 1 #000080 1 1>
<EArc -20 -20 40 40 4320 2880 #000080 2 1>
<Line 0 20 -10 0 #000080 2 1>
<.PortSym -30 -30 1 0 P1>
<.PortSym -30 -10 2 0 P2>
<.PortSym -30 10 3 0 P3>
<.PortSym -30 30 4 0 P4>
<.PortSym 40 0 5 180 P5>
<.ID 20 14 Y>
<Line 28 0 12 0 #000080 2 1>
<Line 0 -20 -10 0 #000080 2 1>
</Symbol>
</Component>
<Component 74LV32>
<Description>
2-Input OR Gate
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV32 _net0 _net1 _net2
Sub:X1 _net0 _net1 _net2 gnd Type="n74LV32_cir"
.Def:End
</Model>
<ModelIncludes "74LV32.cir.lst">
<Spice>
* -------------------------- 74LV32A ----------------------------
* Quad 2-Input Or Gate
*
* TI PDF File
* bss 2/24/03
*
.SUBCKT 74LV32A 1A 1B 1Y
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR_3V DGND_3V
+ 1A 1B 1Y
+ DLY_LV32 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LV32 ugate (tplhTY=6.9ns tplhMX=11.4ns tphlTY=6.9ns tphlMX=11.4ns)
.ENDS 74LV32A
*
.SUBCKT Digital_LV_74LV32 gnd _net0 _net1 _net2
X1 _net0 _net1 _net2 74LV32A
.ENDS
</Spice>
<Symbol>
<.PortSym -30 -10 1 0 P1>
<.PortSym -30 10 2 0 P2>
<.PortSym 30 0 3 180 P3>
<.ID 10 14 Y>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Line 10 0 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
<Line -30 10 20 0 #000080 2 1>
<EArc -20 -20 10 40 4320 2880 #000080 2 1>
<Line -10 20 -5 0 #000080 2 1>
<Line -10 -20 -5 0 #000080 2 1>
</Symbol>
</Component>
<Component 74LV74>
<Description>
D-Type Positive Edge Triggered Flip-Flop With Preset And Clear
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
@ -73,7 +339,7 @@ Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 gnd Type="n74LV74_cir"
* The timing parameters for all of these models were taken from the specifications for a
* 3.3V power supply and a 50pF capacitive load.
*
* ----------------------------------------------------------- 74LV74A ------
* -------------------------------------- 74LV74A ---------------------------
* Dual Positive Edge Triggered D-Type Flip-Flop
*
* TI PDF File
@ -127,3 +393,544 @@ X1 _net0 _net1 _net2 _net3 _net4 _net5 74LV74A
</Symbol>
</Component>
<Component 74LV86>
<Description>
2-Input Exclusive-OR Gate
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV86 _net0 _net1 _net2
Sub:X1 _net0 _net1 _net2 gnd Type="n74LV86_cir"
.Def:End
</Model>
<ModelIncludes "74LV86.cir.lst">
<Spice>
* ----------------------------------------------------------- 74LV86A ------
* Quad 2-Input Exclusive-Or Gate
*
* TI PDF File
* bss 2/24/03
*
.SUBCKT 74LV86 1A 1B 1Y
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR_3V DGND_3V
+ 1A 1B 1Y
+ DLY_LV86 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LV86 ugate (tplhTY=7.4ns tplhMX=14.5ns tphlTY=7.4ns tphlMX=14.5ns)
.ENDS 74LV86
*
.SUBCKT Digital_LV_74LV86 gnd _net0 _net1 _net2
X1 _net0 _net1 _net2 74LV86
.ENDS
</Spice>
<Symbol>
<.PortSym -30 -10 1 0 P1>
<.PortSym -30 10 2 0 P2>
<.PortSym 30 0 3 180 P3>
<.ID 10 14 Y>
<EArc -30 -20 40 40 4320 2880 #000080 2 1>
<Line 10 0 20 0 #000080 2 1>
<Line -30 -10 20 0 #000080 2 1>
<Line -30 10 20 0 #000080 2 1>
<EArc -20 -20 10 40 4320 2880 #000080 2 1>
<EArc -15 -20 10 40 4320 2880 #000080 2 1>
</Symbol>
</Component>
<Component 74LV138>
<Description>
3-Line To 8-Line Decoder/Demultiplexer
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV138 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74LV138_cir"
.Def:End
</Model>
<ModelIncludes "74LV138.cir.lst">
<Spice>
*-----------------------------------------------------------74LV138A-----
* 3-Line To 8-Line Decoder/Demultiplexer
*
* TI PDF File
* bss 2/25/03
.SUBCKT 74LV138A A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(6,8) DPWR_3V DGND_3V
+ A B C G1 G2ABAR G2BBAR
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+ ENAB = {G1 & ~G2ABAR & ~G2BBAR}
+ Y0O = {~(~A & ~B & ~C & ENAB)}
+ Y1O = {~(A & ~B & ~C & ENAB)}
+ Y2O = {~(~A & B & ~C & ENAB)}
+ Y3O = {~(A & B & ~C & ENAB)}
+ Y4O = {~(~A & ~B & C & ENAB)}
+ Y5O = {~(A & ~B & C & ENAB)}
+ Y6O = {~(~A & B & C & ENAB)}
+ Y7O = {~(A & B & C & ENAB)}
U2 PINDLY(8,0,6) DPWR_3V DGND_3V
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ A B C G1 G2ABAR G2BBAR
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+ IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+ ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
+ EN = {CHANGED(G1,0)}
+ PINDLY:
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+ CASE(
+ EN & TRN_LH, DELAY(-1,10.6ns,16.3ns),
+ EN & TRN_HL, DELAY(-1,10.6ns,16.3ns),
+ ENBAR & TRN_LH, DELAY(-1,10ns,14.9ns),
+ ENBAR & TRN_HL, DELAY(-1,10ns,14.9ns),
+ IN & TRN_LH, DELAY(-1,10.3ns,15.8ns),
+ IN & TRN_HL, DELAY(-1,10.3ns,15.8ns),
+ DELAY(-1,11ns,17ns))}
.ENDS 74LV138A
*
.SUBCKT Digital_LV_74LV138 gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74LV138A
.ENDS
</Spice>
<Symbol>
<Line 30 20 20 0 #000080 2 1>
<Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
<Line 30 0 20 0 #000080 2 1>
<Line 30 60 20 0 #000080 2 1>
<Line 30 40 20 0 #000080 2 1>
<Line 30 100 20 0 #000080 2 1>
<Line 30 80 20 0 #000080 2 1>
<Line 30 140 20 0 #000080 2 1>
<Line 30 120 20 0 #000080 2 1>
<Line -50 0 20 0 #000080 2 1>
<.PortSym 50 0 7 180 Y0>
<.PortSym 50 20 8 180 Y1>
<.PortSym 50 40 9 180 Y2>
<.PortSym 50 60 10 180 Y3>
<.PortSym 50 80 11 180 Y4>
<.PortSym 50 100 12 180 Y5>
<.PortSym 50 120 13 180 Y6>
<.PortSym 50 140 14 180 Y7>
<Line -50 20 20 0 #000080 2 1>
<Line -50 40 20 0 #000080 2 1>
<.PortSym -50 20 2 0 B>
<.PortSym -50 0 1 0 A>
<.PortSym -50 40 3 0 C>
<Line -50 80 20 0 #000080 2 1>
<Line -50 100 20 0 #000080 2 1>
<Ellipse -31 96 -8 8 #000080 1 1 #000080 1 1>
<Line -50 120 20 0 #000080 2 1>
<Ellipse -31 116 -8 8 #000080 1 1 #000080 1 1>
<.PortSym -50 80 4 0 G1>
<.PortSym -50 100 5 0 G2AB>
<.PortSym -50 120 6 0 G2BB>
<Text -25 -11 12 #000080 0 "A">
<Text 6 29 12 #000080 0 "Y2">
<Text 6 49 12 #000080 0 "Y3">
<Text 6 129 12 #000080 0 "Y7">
<Text 6 9 12 #000080 0 "Y1">
<Text 6 89 12 #000080 0 "Y5">
<Text 6 -11 12 #000080 0 "Y0">
<Text 6 69 12 #000080 0 "Y4">
<Text 6 109 12 #000080 0 "Y6">
<Text -25 9 12 #000080 0 "B">
<Text -25 69 12 #000080 0 "G1">
<Text -25 89 12 #000080 0 "G2">
<Text -25 109 12 #000080 0 "G3">
<.ID -10 164 Y>
<Text -25 29 12 #000080 0 "C">
</Symbol>
</Component>
<Component 74LV164>
<Description>
8-Bit Parallel-Out Serial Shift Register
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
.PARAM: vcc=5
</Description>
<Model>
.Def:Digital_LV_74LV164 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="n74LV164_cir"
.Def:End
</Model>
<ModelIncludes "74LV164.cir.lst">
<Spice>
* ----------------------------------------------------------- 74LV164 ------
* 8-Bit Parallel-Out Serial Shift Register
*
* TI PDF File
* bss 2/26/03
*
.SUBCKT 74LV164 A B CLRBAR CLK QA QB QC QD QE QF QG QH
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U74164 LOGICEXP (3,3) DPWR_3V DGND_3V
+ CLK A B
+ r0 s0 clkbar
+ D0_GATE IO_LV-A IO_LEVEL={IO_LEVEL}
+
+ LOGIC:
+ r0 = { (~(A & B)) }
+ s0 = { (~r0) }
+ clkbar = { (~CLK) }
uf0 JKff(8) DPWR_3V DGND_3V
+ $D_HI CLRBAR clkbar
+ s0 QA_O QB_O QC_O QD_O QE_O QF_O QG_O
+ r0 qabar qbbar qcbar qdbar qebar qfbar qgbar
+ QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
+ qabar qbbar qcbar qdbar qebar qfbar qgbar qhbar
+ D0_EFF IO_LV-A
Udly PINDLY (8,0,2) DPWR_3V DGND_3V
+ QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
+ CLRBAR CLK
+ QA QB QC QD QE QF QG QH
+ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+ BOOLEAN:
+ CLOCK= { CHANGED(CLK,0) }
+ CLEAR= { CHANGED_HL(CLRBAR,0) }
+
+ PINDLY:
+ QA QB QC QD QE QF QG QH = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,7.9ns,16.3ns),
+ CLOCK, DELAY(-1,8.3ns,16.3ns),
+ DELAY(-1,9ns,17ns)
+ )
+ }
Ucnstr CONSTRAINT(4) DPWR_3V DGND_3V
+ CLRBAR CLK A B
+ IO_LV-A
+
+ FREQ:
+ NODE = CLK
+ MAXFREQ = 120MEG
+ WIDTH:
+ NODE = CLK
+ MIN_HI = 5ns
+ MIN_LO = 5ns
+ WIDTH:
+ NODE = CLRBAR
+ MIN_LO = 5ns
+ SETUP_HOLD:
+ CLOCK LH = CLK
+ DATA(2) = A B
+ SETUPTIME = 5ns
+ WHEN = { CLRBAR != '0 }
+ SETUP_HOLD:
+ DATA(1) = CLRBAR
+ CLOCK LH = CLK
+ SETUPTIME_HI = 2.5ns
.ENDS 74LV164
*
.SUBCKT Digital_LV_74LV164 gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 74LV164
.ENDS
</Spice>
<Symbol>
<Line 30 20 20 0 #000080 2 1>
<Text 4 9 12 #000080 0 "QB">
<Text 4 -11 12 #000080 0 "QA">
<Text 4 29 12 #000080 0 "QC">
<Text 4 49 12 #000080 0 "QD">
<Text 4 69 12 #000080 0 "QE">
<Line -50 0 20 0 #000080 2 1>
<Text -28 -10 12 #000080 0 "A">
<Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
<Line 30 0 20 0 #000080 2 1>
<Text 4 89 12 #000080 0 "QF">
<Text 4 109 12 #000080 0 "QG">
<Text 4 129 12 #000080 0 "QH">
<Line 30 60 20 0 #000080 2 1>
<Line 30 40 20 0 #000080 2 1>
<Line 30 100 20 0 #000080 2 1>
<Line 30 80 20 0 #000080 2 1>
<Line 30 140 20 0 #000080 2 1>
<Line 30 120 20 0 #000080 2 1>
<Line -50 20 20 0 #000080 2 1>
<Line -50 60 20 0 #000080 2 1>
<Text -28 10 12 #000080 0 "B">
<Text -28 50 12 #000080 0 "CLR">
<Ellipse -31 56 -8 8 #000080 1 1 #000080 1 1>
<Line -50 140 20 0 #000080 2 1>
<Line -15 140 -15 -10 #000080 2 1>
<Line -30 150 15 -10 #000080 2 1>
<.PortSym -50 60 3 0 CLRBAR>
<.ID -10 164 Y>
<.PortSym -50 0 1 0 A>
<.PortSym -50 20 2 0 B>
<.PortSym -50 140 4 0 CLK>
<.PortSym 50 0 5 180 QA>
<.PortSym 50 20 6 180 QB>
<.PortSym 50 40 7 180 QC>
<.PortSym 50 60 8 180 QD>
<.PortSym 50 80 9 180 QE>
<.PortSym 50 100 10 180 QF>
<.PortSym 50 120 11 180 QG>
<.PortSym 50 140 12 180 QH>
</Symbol>
</Component>
<Component 74LV4040>
<Description>
12-Stage Binary Ripple Counter
XSPICE Based Model
Requirements:
.spiceinit: set ngbehavior=psa
</Description>
<Model>
.Def:Digital_LV_74LV4040 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74LV4040_cir"
.Def:End
</Model>
<ModelIncludes "74LV4040.cir.lst">
<Spice>
*
*---------------------74LV4040A-----------------------
* 12-Bit Asynchronous Binary Counter
*
* TI PDF File
* bss 2/28/03
.SUBCKT 74LV4040 CLR CLK QA QB QC QD QE QF QG QH QI QJ QK QL
+ optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
+ params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(1,1) DPWR_3V DGND_3V
+ CLR
+ RESETBAR
+ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+ RESETBAR = {~CLR}
U2 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR CLK
+ $D_HI $D_HI Q_A $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_A
+ $D_HI $D_HI Q_B $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_B
+ $D_HI $D_HI Q_C $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_C
+ $D_HI $D_HI Q_D $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_D
+ $D_HI $D_HI Q_E $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U7 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_E
+ $D_HI $D_HI Q_F $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U8 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_F
+ $D_HI $D_HI Q_G $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U9 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_G
+ $D_HI $D_HI Q_H $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U10 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_H
+ $D_HI $D_HI Q_I $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U11 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_I
+ $D_HI $D_HI Q_J $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U12 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_J
+ $D_HI $D_HI Q_K $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U13 JKFF(1) DPWR_3V DGND_3V
+ $D_HI RESETBAR Q_K
+ $D_HI $D_HI Q_L $D_NC
+ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U14 PINDLY(12,0,2) DPWR_3V DGND_3V
+ Q_A Q_B Q_C Q_D Q_E Q_F Q_G Q_H Q_I Q_J Q_K Q_L
+ CLR CLK
+ QA QB QC QD QE QF QG QH QI QJ QK QL
+ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+ CLEAR = {CHANGED_LH(CLR,0)}
+ ACLK = {CHANGED_HL(CLK,0)}
+ PINDLY:
+ QA = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,7.5ns,15.4ns),
+ DELAY(-1,10ns,17ns))}
+ QB = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,8.7ns,19.8ns),
+ DELAY(-1,10ns,20ns))}
+ QC = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,9.9ns,24.2ns),
+ DELAY(-1,10ns,25ns))}
+ QD = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,11.1ns,28.6ns),
+ DELAY(-1,12ns,29ns))}
+ QE = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,12.3ns,33ns),
+ DELAY(-1,13ns,34ns))}
+ QF = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,13.5ns,37.4ns),
+ DELAY(-1,14ns,38ns))}
+ QG = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,14.7ns,41.8ns),
+ DELAY(-1,15ns,42ns))}
+ QH = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,15.9ns,46.2ns),
+ DELAY(-1,16ns,47ns))}
+ QI = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,17.1ns,50.6ns),
+ DELAY(-1,18ns,51ns))}
+ QJ = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,18.3ns,55ns),
+ DELAY(-1,19ns,56ns))}
+ QK = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,19.5ns,59.4ns),
+ DELAY(-1,20ns,60ns))}
+ QL = {
+ CASE(
+ CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
+ ACLK, DELAY(-1,20.7ns,63.8ns),
+ DELAY(-1,21ns,64ns))}
U15 CONSTRAINT(2) DPWR_3V DGND_3V
+ CLK CLR
+ IO_LV-A IO_LEVEL={IO_LEVEL}
+ SETUP_HOLD:
+ CLOCK HL = CLK
+ DATA(1) = CLR
+ SETUPTIME_LO = 5NS
+ WIDTH:
+ NODE = CLK
+ MIN_HI = 5NS
+ MIN_LO = 5NS
+ WIDTH:
+ NODE = CLR
+ MIN_HI = 5NS
+ FREQ:
+ NODE = CLK
+ MAXFREQ = 130MEG
.ENDS 74LV4040
*
.SUBCKT Digital_LV_74LV4040 gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74LV4040
.ENDS
</Spice>
<Symbol>
<Line 30 20 20 0 #000080 2 1>
<Text 4 9 12 #000080 0 "QB">
<Text 4 -11 12 #000080 0 "QA">
<Text 4 29 12 #000080 0 "QC">
<Text 4 49 12 #000080 0 "QD">
<Text 4 69 12 #000080 0 "QE">
<Rectangle -30 -20 60 260 #000080 2 1 #c0c0c0 1 0>
<Line 30 0 20 0 #000080 2 1>
<Text 4 89 12 #000080 0 "QF">
<Text 4 109 12 #000080 0 "QG">
<Text 4 129 12 #000080 0 "QH">
<Line 30 60 20 0 #000080 2 1>
<Line 30 40 20 0 #000080 2 1>
<Line 30 100 20 0 #000080 2 1>
<Line 30 80 20 0 #000080 2 1>
<Line 30 140 20 0 #000080 2 1>
<Line 30 120 20 0 #000080 2 1>
<Line 30 160 20 0 #000080 2 1>
<Line 30 180 20 0 #000080 2 1>
<Line 30 200 20 0 #000080 2 1>
<Line 30 220 20 0 #000080 2 1>
<.PortSym 50 0 3 180 QA>
<.PortSym 50 20 4 180 QB>
<.PortSym 50 40 5 180 QC>
<.PortSym 50 60 6 180 QD>
<.PortSym 50 80 7 180 QE>
<.PortSym 50 100 8 180 QF>
<.PortSym 50 120 9 180 QG>
<.PortSym 50 140 10 180 QH>
<.PortSym 50 160 11 180 QI>
<.PortSym 50 180 12 180 QJ>
<Text 4 149 12 #000080 0 "QI">
<Text 4 169 12 #000080 0 "QJ">
<Text 4 189 12 #000080 0 "QK">
<Text 4 209 12 #000080 0 "QL">
<.ID -10 244 Y>
<.PortSym 50 200 13 180 QK>
<.PortSym 50 220 14 180 QL>
<.PortSym -50 0 2 0 CLK>
<Line -50 0 20 0 #000080 2 1>
<Line -15 0 -15 -10 #000080 2 1>
<Line -30 10 15 -10 #000080 2 1>
<Line -50 60 20 0 #000080 2 1>
<Text -28 50 12 #000080 0 "CLR">
<.PortSym -50 60 1 0 CLR>
</Symbol>
</Component>

2
library/qucs.blacklist
View File

@ -1,6 +1,6 @@
SpiceOpamp.lib
Cores.lib
Digital_CD4000.lib
Digital_CD.lib
Digital_HC.lib
Digital_LV.lib
Transformers.lib

2
library/xyce.blacklist
View File

@ -1,6 +1,6 @@
Substrates.lib
Xanalogue.lib
PWM_Controller.lib
Digital_CD4000.lib
Digital_CD.lib
Digital_HC.lib
Digital_LV.lib