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Add swtich to supress digital model generation when creating library

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This commit is contained in:
Vadim Kuznetsov 2025-01-19 13:50:33 +03:00
parent 6adc782cff
commit fcdcaeaebe
3 changed files with 11 additions and 4 deletions
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8
qucs/components/libcomp.cpp
View File

@ -424,10 +424,10 @@ QString LibComp::getSpiceLibrary()
return QString();
}
for (const auto &file : attach) {
if (file.endsWith(".cir") ||
file.endsWith(".ckt") ||
file.endsWith(".lib") ||
file.endsWith(".sp")) {
if (file.endsWith(".cir", Qt::CaseInsensitive) ||
file.endsWith(".ckt", Qt::CaseInsensitive) ||
file.endsWith(".lib", Qt::CaseInsensitive) ||
file.endsWith(".sp", Qt::CaseInsensitive)) {
files.append(getSubcircuitFile()+'/'+file);
}
}

6
qucs/dialogs/librarydialog.cpp
View File

@ -105,6 +105,10 @@ LibraryDialog::LibraryDialog(QWidget *parent)
hCheck->addStretch();
connect(checkDescr, SIGNAL(stateChanged(int)), this, SLOT(slotCheckDescrChanged(int)));
checkAnalogLib = new QCheckBox(tr("Analog models only"));
checkAnalogLib->setChecked(true);
selectSubcktLayout->addWidget(checkAnalogLib);
// ...........................................................
QGridLayout *gridButts = new QGridLayout();
selectSubcktLayout->addLayout(gridButts);
@ -523,6 +527,7 @@ void LibraryDialog::slotSave()
QucsSettings.DefaultSimulator = sim;
//}
if (!checkAnalogLib->isChecked()) {
// save verilog model
tmp.truncate(0);
Doc->setIsVerilog(true);
@ -597,6 +602,7 @@ void LibraryDialog::slotSave()
else {
ErrText->insertPlainText("\n");
}
}
Stream << " <Symbol>\n";
Doc->createSubcircuitSymbol();

1
qucs/dialogs/librarydialog.h
View File

@ -94,6 +94,7 @@ private:
QStringList SelectedNames;
QStringList Descriptions;
QCheckBox *checkDescr;
QCheckBox *checkAnalogLib;
QFile LibFile;
QDir LibDir;