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12 Commits

Author SHA1 Message Date
Krasilnikov Sergei
05177da97b working with qt6 2023-01-17 13:27:12 +03:00
Krasilnikov Sergey
b70e615020 replace foreach macro 2023-01-15 01:17:09 +03:00
Vadim Kuznetsov
aa3fe8c2d6 Implmented extra internal nodes extraction for complex components 2015-11-11 11:34:57 +03:00
MikeBrinson
9d9ac0d047 Removed node gnd from capacitor and inductor models. 2015-11-11 11:34:56 +03:00
Vadim Kuznetzov
c9c35dbcad Added voltages and current normalization to exclude ground node 2015-11-11 11:34:56 +03:00
Vadim Kuznetzov
c18fb6450a Fixed different bugs: 
1. No log at empty simulation list for Xyce. Added error message
2. Ignoring of disabled (red cross) equations in Verilog-A modules
builder
 2015-11-11 11:34:56 +03:00
Vadim Kuznetzov
e87d05d039 Added Doxygen entries for verilogwriter.cpp 2015-11-11 11:34:55 +03:00
Vadim Kuznetzov
8e3c3cbe1a Added error message on building Verilog-A module attempt not from subcircuit 2015-11-11 11:34:55 +03:00
MikeBrinson
eea3c7778b Improved externsimdialog text 2015-11-11 11:34:19 +03:00
Vadim Kuznetzov
10cac57daf Resistor model added 2015-11-11 11:34:18 +03:00
Vadim Kuznetzov
6b51f5bc37 First concept of Verilog-A modules builder. EDD implemented 2015-11-11 11:34:18 +03:00
Vadim Kuznetzov
f3bd5aec7d Initial Verilog-A routines 2015-11-11 11:34:18 +03:00