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6 Commits

Author SHA1 Message Date
luz paz
10c1ee639c Fix various typos (including documenation) 
Found via `codespell -q 3 -S *.ts,./qucs/ChangeLog -L ba,coul,inout,leaded,nd,numer,ro`
 2022-07-05 07:08:28 -04:00
Vadim Kuznetsov
5084662512 Remove QtCore include to supress warning on Qt5.12 2022-02-15 22:41:25 +01:00
Vadim Kuznetzov
c9c35dbcad Added voltages and current normalization to exclude ground node 2015-11-11 11:34:56 +03:00
Vadim Kuznetzov
e87d05d039 Added Doxygen entries for verilogwriter.cpp 2015-11-11 11:34:55 +03:00
Vadim Kuznetzov
6b51f5bc37 First concept of Verilog-A modules builder. EDD implemented 2015-11-11 11:34:18 +03:00
Vadim Kuznetzov
f3bd5aec7d Initial Verilog-A routines 2015-11-11 11:34:18 +03:00