* schematic_file.cpp: Some code cleanup. Also fixed a problem
with subcircuits containing VHDL files: passing signal types up
also when more than one instance of the subcircuit is on the
schematic.
* schematic_file.cpp (createSubNetlistPlain): Adjusting type
specifiers of VHDL subcircuits according to arbitrary signal types
in VHDL files.
2009-03-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (loadFile): Extracting signal types and passing
them to port specifications.
* schematic_file.cpp (giveNodeNames): Using QPtrListIterator for
iterating the DocComps list. This is because the current item of
the list itself may be modified during iteration in the
drawContents() method due to a repaint event.
* dialogs/librarydialog.cpp (LibraryDialog): Added
"Select/Deselect All" buttons.
(slotNext): Reversed order of include files (important for VHDL
simulations).
* dialogs/librarydialog.cpp (slotNext): Library creation now
includes file handling. Separate subcircuit files (VHDL, Verilog,
Qucs-Subcircuit, SPICE) used by library elements are stored in an
extra sub-directory.
* schematic_file.cpp (giveNodeNames): Saving included files in a
different manner in the global list.
(createSubNetlistPlain): Allow subcircuit files to be stored in a
dedicated file. Used during library file creations.
* main.cpp (properAbsFileName, properFileName): Added two new
helper functions for file name mangling.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* qucslib.cpp (slotShowComponent): Allow also VHDL and Verilog
entries to define a model. Fixed drag'n'drop ability for digital
only models.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (getSubcircuitFile), verilogfile.cpp
(getSubcircuitFile), subcircuit.cpp (netlist), spicefile.cpp
(recreateSubNetlist): Using new file name mangling functions.
* libcomp.cpp (loadSection): Additionally loading the file include
references.
(createSubNetlist): Also put file includes into the netlist
stream.
* qucs_uk.ts, qtgeneric_uk.ts: Updated Ukrainian translations.
Thanks to Hse?
* schematic_file.cpp (giveNodeNames): Allow library component to
emit analog as well as digital netlist code.
2007-05-09 Stefan Jahn <stefan@lkcc.org>
* libcomp.cpp: Enabled library component to emit analog as well as
digital netlist code.
* dialogs/librarydialog.cpp (slotNext): Beside analog models now
also verilog and vhdl models are saved.
* schematic_file.cpp (giveNodeNames): Using new file component
netlist creators.
2007-05-08 Stefan Jahn <stefan@lkcc.org>
* verilogfile.cpp, vhdlfile.cpp, spicefile.cpp (createSubNetlist):
File components can now create the netlist parts on their own.
* textdoc.cpp (TextDoc): Using mono-spaced font in text
editor.
* schematic_file.cpp (giveNodeNames): Fixed loading of
Verilog files during VHDL run and vice versa.
* qucs.cpp (initContentListView): Added verilog files in
content tab.
2007-03-31 Stefan Jahn <stefan@lkcc.org>
* docs/qucsveri.1: Added manpage for the qucsveri wrapper
script for digital simulations.
2007-03-31 Stefan Jahn <stefan@lkcc.org>
* verilogfile.h: Added new component. Can handle external
verilog files. Can be used as subcircuit.
* schematic_file.cpp (createNetlist): Fixed a bug in
determining the simulation time of digital simulations
occurring when there are other disabled simulations
placed on the schematic.
(createSubNetlist): Implemented subcircuit modules for
Verilog simulations.
2007-03-28 Stefan Jahn <stefan@lkcc.org>
* d_flipflop.cpp (verilogCode): Fixed Verilog code of
D-flipflop. Is working now, can be used as template for
other flipflops.
* qucsveri: New digital simulation wrapper for Icarus
verilog added.
* schematic_file.cpp (prepareNetlist): Started to implement
Verilog HDL interface.
2007-03-26 Stefan Jahn <stefan@lkcc.org>
* digi_sim.cpp (Digi_Sim): Can select between VHDL and Verilog
netlist format.
* component.cpp (get_Verilog_Code): Gate components and digital
sources now working with Verilog HDL.
* dialogs/simmessage.cpp (startSimulator): Investigation
about path names under Win32. It looks like only one
argument can be quoted on the command line of a batch
file. Do not know (yet) if this also applies to other
binaries (*.exe files).
* qucsdigi (IEEELIBS): Linking with IEEE libraries. Thus
it is now possible to the IEEE libraries shipped with
FreeHDL as well. Also made this modification in the
'qucsdigi.bat' batch file for Win32.
* main.cpp (checkVersion): Added a convenience function for
version checks which was broken due to the 0.0.10 bump.
Using the function several times throughout the code.
