* dialogs/settingsdialog.cpp (SettingsDialog): Added script
setting to simulations. The script can be enabled to be run after
simulation.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1818 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* paintings/rectangle.cpp, paintings/portsymbol.cpp,
paintings/id_text.cpp, paintings/graphictext.cpp,
paintings/graphicline.cpp, paintings/ellipsearc.cpp,
paintings/ellipse.cpp, paintings/arrow.cpp (saveCpp): Added
support functions for saving drawing as C++ code snippet.
* dialogs/vasettingsdialog.cpp (VASettingsDialog): Added new
property dialog for Verilog-A files.
* textdoc.cpp (getModuleName): Added function to obtain
module/entity name of a text file (e.g. Verilog or VHDL).
(saveSettings): Saving additional settings for Verilog-A text
files.
* schematic_file.cpp (saveSymbolCpp): Added code to save C++
symbol drawing code into the dataset of a schematic.
(saveDocument): Usin above function to save C++ code of a symbol
drawing document associated with a Verilog-A file.
* schematic.cpp (adjustPortNumbers): Creating/updating Verilog-A
text file's default symbol when switching to symbol page.
2009-10-27 Stefan Jahn <stefan@lkcc.org>
* vafile.cpp (VerilogA_File_Info): Added new class parsing ports
and module name of a Verilog-A file.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1755 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* paintings/rectangle.cpp, paintings/portsymbol.cpp,
paintings/id_text.cpp, paintings/graphictext.cpp,
paintings/graphicline.cpp, paintings/ellipsearc.cpp,
paintings/ellipse.cpp, paintings/arrow.cpp (saveCpp): Added
support functions for saving drawing as C++ code snippet.
* dialogs/vasettingsdialog.cpp (VASettingsDialog): Added new
property dialog for Verilog-A files.
* textdoc.cpp (getModuleName): Added function to obtain
module/entity name of a text file (e.g. Verilog or VHDL).
(saveSettings): Saving additional settings for Verilog-A text
files.
* schematic_file.cpp (saveSymbolCpp): Added code to save C++
symbol drawing code into the dataset of a schematic.
(saveDocument): Usin above function to save C++ code of a symbol
drawing document associated with a Verilog-A file.
* schematic.cpp (adjustPortNumbers): Creating/updating Verilog-A
text file's default symbol when switching to symbol page.
2009-10-27 Stefan Jahn <stefan@lkcc.org>
* vafile.cpp (VerilogA_File_Info): Added new class parsing ports
and module name of a Verilog-A file.
* syntax.cpp (highlightParagraph): Added support for (* *)
comments in Verilog-HDL files. Also nested comments are allowed.
* schematic.cpp (adjustPortNumbers): Support for ceation of
Verilog-HDL text file's default symbol.
2009-10-23 Stefan Jahn <stefan@lkcc.org>
* verilogfile.cpp (Verilog_File_Info): Added class for parsing
port information from Verilog-HDL code/files.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1751 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* syntax.cpp (highlightParagraph): Added support for (* *)
comments in Verilog-HDL files. Also nested comments are allowed.
* schematic.cpp (adjustPortNumbers): Support for ceation of
Verilog-HDL text file's default symbol.
2009-10-23 Stefan Jahn <stefan@lkcc.org>
* verilogfile.cpp (Verilog_File_Info): Added class for parsing
port information from Verilog-HDL code/files.
* textdoc.cpp: Moved syntax highligther class into 'syntax.cpp'
file.
* schematic.cpp (adjustPortNumbers): If symbol for text file is
requested, then create default symbol for VHDL files.
* qucs.cpp (slotSymbolEdit): Allowing to edit symbols for text
documents.
2009-10-19 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (VHDL_File_Info): Allowing function to read VHDL
file information directly from files.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1749 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* textdoc.cpp: Moved syntax highligther class into 'syntax.cpp'
file.
* schematic.cpp (adjustPortNumbers): If symbol for text file is
requested, then create default symbol for VHDL files.
* qucs.cpp (slotSymbolEdit): Allowing to edit symbols for text
documents.
2009-10-19 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (VHDL_File_Info): Allowing function to read VHDL
file information directly from files.
* diagrams/graph.cpp (paint): Using 'PrinterScale' to magnify line
thickness of graphs correctly.
* viewpainter.cpp (drawTextMapped): Introduced 'PrinterScale'
property and thus are able to print subscript and superscript
correctly.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1456 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* diagrams/graph.cpp (paint): Using 'PrinterScale' to magnify line
thickness of graphs correctly.
* viewpainter.cpp (drawTextMapped): Introduced 'PrinterScale'
property and thus are able to print subscript and superscript
correctly.
* dialogs/librarydialog.cpp (slotNext): Library creation now
includes file handling. Separate subcircuit files (VHDL, Verilog,
Qucs-Subcircuit, SPICE) used by library elements are stored in an
extra sub-directory.
* schematic_file.cpp (giveNodeNames): Saving included files in a
different manner in the global list.
(createSubNetlistPlain): Allow subcircuit files to be stored in a
dedicated file. Used during library file creations.
* main.cpp (properAbsFileName, properFileName): Added two new
helper functions for file name mangling.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* qucslib.cpp (slotShowComponent): Allow also VHDL and Verilog
entries to define a model. Fixed drag'n'drop ability for digital
only models.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (getSubcircuitFile), verilogfile.cpp
(getSubcircuitFile), subcircuit.cpp (netlist), spicefile.cpp
(recreateSubNetlist): Using new file name mangling functions.
* libcomp.cpp (loadSection): Additionally loading the file include
references.
(createSubNetlist): Also put file includes into the netlist
stream.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1239 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* dialogs/librarydialog.cpp (slotNext): Library creation now
includes file handling. Separate subcircuit files (VHDL, Verilog,
Qucs-Subcircuit, SPICE) used by library elements are stored in an
extra sub-directory.
* schematic_file.cpp (giveNodeNames): Saving included files in a
different manner in the global list.
(createSubNetlistPlain): Allow subcircuit files to be stored in a
dedicated file. Used during library file creations.
* main.cpp (properAbsFileName, properFileName): Added two new
helper functions for file name mangling.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* qucslib.cpp (slotShowComponent): Allow also VHDL and Verilog
entries to define a model. Fixed drag'n'drop ability for digital
only models.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (getSubcircuitFile), verilogfile.cpp
(getSubcircuitFile), subcircuit.cpp (netlist), spicefile.cpp
(recreateSubNetlist): Using new file name mangling functions.
* libcomp.cpp (loadSection): Additionally loading the file include
references.
(createSubNetlist): Also put file includes into the netlist
stream.
* textdoc.cpp (print): Also fixed print scale for text
documents.
* schematic.cpp (print): Fixed print scale for schematics. It
assumed a screen resolution of 72dpi.
* mouseactions.cpp (rotateElements): Made rotation sticky while
placing elements from the component tab as well as when pasting
elements from the clipboard into the schematic.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1186 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* textdoc.cpp (print): Also fixed print scale for text
documents.
* schematic.cpp (print): Fixed print scale for schematics. It
assumed a screen resolution of 72dpi.
* mouseactions.cpp (rotateElements): Made rotation sticky while
placing elements from the component tab as well as when pasting
elements from the clipboard into the schematic.
