* qucs.cpp (slotOpenContent): Allowing double click on .vhd files.
* schematic_file.cpp (saveSymbolCpp): Including terminal centers
into computation of the boundig box when exporting the C++ code
for the symbol.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1835 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* dialogs/settingsdialog.cpp (SettingsDialog): Added script
setting to simulations. The script can be enabled to be run after
simulation.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1818 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* paintings/rectangle.cpp, paintings/portsymbol.cpp,
paintings/id_text.cpp, paintings/graphictext.cpp,
paintings/graphicline.cpp, paintings/ellipsearc.cpp,
paintings/ellipse.cpp, paintings/arrow.cpp (saveCpp): Added
support functions for saving drawing as C++ code snippet.
* dialogs/vasettingsdialog.cpp (VASettingsDialog): Added new
property dialog for Verilog-A files.
* textdoc.cpp (getModuleName): Added function to obtain
module/entity name of a text file (e.g. Verilog or VHDL).
(saveSettings): Saving additional settings for Verilog-A text
files.
* schematic_file.cpp (saveSymbolCpp): Added code to save C++
symbol drawing code into the dataset of a schematic.
(saveDocument): Usin above function to save C++ code of a symbol
drawing document associated with a Verilog-A file.
* schematic.cpp (adjustPortNumbers): Creating/updating Verilog-A
text file's default symbol when switching to symbol page.
2009-10-27 Stefan Jahn <stefan@lkcc.org>
* vafile.cpp (VerilogA_File_Info): Added new class parsing ports
and module name of a Verilog-A file.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1755 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* paintings/rectangle.cpp, paintings/portsymbol.cpp,
paintings/id_text.cpp, paintings/graphictext.cpp,
paintings/graphicline.cpp, paintings/ellipsearc.cpp,
paintings/ellipse.cpp, paintings/arrow.cpp (saveCpp): Added
support functions for saving drawing as C++ code snippet.
* dialogs/vasettingsdialog.cpp (VASettingsDialog): Added new
property dialog for Verilog-A files.
* textdoc.cpp (getModuleName): Added function to obtain
module/entity name of a text file (e.g. Verilog or VHDL).
(saveSettings): Saving additional settings for Verilog-A text
files.
* schematic_file.cpp (saveSymbolCpp): Added code to save C++
symbol drawing code into the dataset of a schematic.
(saveDocument): Usin above function to save C++ code of a symbol
drawing document associated with a Verilog-A file.
* schematic.cpp (adjustPortNumbers): Creating/updating Verilog-A
text file's default symbol when switching to symbol page.
2009-10-27 Stefan Jahn <stefan@lkcc.org>
* vafile.cpp (VerilogA_File_Info): Added new class parsing ports
and module name of a Verilog-A file.
* equation.cpp (verilogCode, vhdlCode): Added code for equations.
2009-05-04 Stefan Jahn <stefan@lkcc.org>
* schematic_file.cpp (createSubNetlistPlain): Allow equations to
be put into Verilog and VHDL netlists.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1719 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* equation.cpp (verilogCode, vhdlCode): Added code for equations.
2009-05-04 Stefan Jahn <stefan@lkcc.org>
* schematic_file.cpp (createSubNetlistPlain): Allow equations to
be put into Verilog and VHDL netlists.
* paintings/id_dialog.cpp (ID_Dialog): Added new 'Type' property
for subcircuit parameters.
* schematic_file.cpp (createSubNetlistPlain): Using new 'Type'
property for subcircuit parameters for passing them to generic
VHDL parameters.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1696 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* paintings/id_dialog.cpp (ID_Dialog): Added new 'Type' property
for subcircuit parameters.
* schematic_file.cpp (createSubNetlistPlain): Using new 'Type'
property for subcircuit parameters for passing them to generic
VHDL parameters.
* subcircuit.cpp (vhdlCode): Added subcircuit parameters in VHDL
using the generic map() feature.
* phototransistor.cpp (createSymbol): Fixed symbol painting.
2009-04-07 Stefan Jahn <stefan@lkcc.org>
* textdoc.cpp (createPopupMenu): Added "Document properties" to
the right click popup menu in text editor files.
* schematic_file.cpp (createSubNetlistPlain): Using generic()
definitions for subcircuit parameters in VHDL.
* qucs_ar.ts: Updated arabic translations. Thanks to Chabane!
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1686 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* subcircuit.cpp (vhdlCode): Added subcircuit parameters in VHDL
using the generic map() feature.
* phototransistor.cpp (createSymbol): Fixed symbol painting.
2009-04-07 Stefan Jahn <stefan@lkcc.org>
* textdoc.cpp (createPopupMenu): Added "Document properties" to
the right click popup menu in text editor files.
* schematic_file.cpp (createSubNetlistPlain): Using generic()
definitions for subcircuit parameters in VHDL.
* qucs_ar.ts: Updated arabic translations. Thanks to Chabane!
* schematic_file.cpp: Some code cleanup. Also fixed a problem
with subcircuits containing VHDL files: passing signal types up
also when more than one instance of the subcircuit is on the
schematic.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1641 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* schematic_file.cpp: Some code cleanup. Also fixed a problem
with subcircuits containing VHDL files: passing signal types up
also when more than one instance of the subcircuit is on the
schematic.
* schematic_file.cpp (createSubNetlistPlain): Adjusting type
specifiers of VHDL subcircuits according to arbitrary signal types
in VHDL files.
2009-03-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (loadFile): Extracting signal types and passing
them to port specifications.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1637 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* schematic_file.cpp (createSubNetlistPlain): Adjusting type
specifiers of VHDL subcircuits according to arbitrary signal types
in VHDL files.
2009-03-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (loadFile): Extracting signal types and passing
them to port specifications.
* schematic_file.cpp (prepareNetlist): Fixed bug occuring with
verilog-hdl subcircuits including delays (timescale must be set
previously).
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1489 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* schematic_file.cpp (giveNodeNames): Using QPtrListIterator for
iterating the DocComps list. This is because the current item of
the list itself may be modified during iteration in the
drawContents() method due to a repaint event.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1251 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* schematic_file.cpp (giveNodeNames): Using QPtrListIterator for
iterating the DocComps list. This is because the current item of
the list itself may be modified during iteration in the
drawContents() method due to a repaint event.
* dialogs/librarydialog.cpp (LibraryDialog): Added
"Select/Deselect All" buttons.
(slotNext): Reversed order of include files (important for VHDL
simulations).
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1240 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* dialogs/librarydialog.cpp (LibraryDialog): Added
"Select/Deselect All" buttons.
(slotNext): Reversed order of include files (important for VHDL
simulations).
* dialogs/librarydialog.cpp (slotNext): Library creation now
includes file handling. Separate subcircuit files (VHDL, Verilog,
Qucs-Subcircuit, SPICE) used by library elements are stored in an
extra sub-directory.
* schematic_file.cpp (giveNodeNames): Saving included files in a
different manner in the global list.
(createSubNetlistPlain): Allow subcircuit files to be stored in a
dedicated file. Used during library file creations.
* main.cpp (properAbsFileName, properFileName): Added two new
helper functions for file name mangling.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* qucslib.cpp (slotShowComponent): Allow also VHDL and Verilog
entries to define a model. Fixed drag'n'drop ability for digital
only models.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (getSubcircuitFile), verilogfile.cpp
(getSubcircuitFile), subcircuit.cpp (netlist), spicefile.cpp
(recreateSubNetlist): Using new file name mangling functions.
* libcomp.cpp (loadSection): Additionally loading the file include
references.
(createSubNetlist): Also put file includes into the netlist
stream.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1239 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* dialogs/librarydialog.cpp (slotNext): Library creation now
includes file handling. Separate subcircuit files (VHDL, Verilog,
Qucs-Subcircuit, SPICE) used by library elements are stored in an
extra sub-directory.
* schematic_file.cpp (giveNodeNames): Saving included files in a
different manner in the global list.
(createSubNetlistPlain): Allow subcircuit files to be stored in a
dedicated file. Used during library file creations.
* main.cpp (properAbsFileName, properFileName): Added two new
helper functions for file name mangling.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* qucslib.cpp (slotShowComponent): Allow also VHDL and Verilog
entries to define a model. Fixed drag'n'drop ability for digital
only models.
2007-05-10 Stefan Jahn <stefan@lkcc.org>
* vhdlfile.cpp (getSubcircuitFile), verilogfile.cpp
(getSubcircuitFile), subcircuit.cpp (netlist), spicefile.cpp
(recreateSubNetlist): Using new file name mangling functions.
* libcomp.cpp (loadSection): Additionally loading the file include
references.
(createSubNetlist): Also put file includes into the netlist
stream.
* qucs_uk.ts, qtgeneric_uk.ts: Updated Ukrainian translations.
Thanks to Hse?
* schematic_file.cpp (giveNodeNames): Allow library component to
emit analog as well as digital netlist code.
2007-05-09 Stefan Jahn <stefan@lkcc.org>
* libcomp.cpp: Enabled library component to emit analog as well as
digital netlist code.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1238 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* qucs_uk.ts, qtgeneric_uk.ts: Updated Ukrainian translations.
Thanks to Hse?
* schematic_file.cpp (giveNodeNames): Allow library component to
emit analog as well as digital netlist code.
2007-05-09 Stefan Jahn <stefan@lkcc.org>
* libcomp.cpp: Enabled library component to emit analog as well as
digital netlist code.
* dialogs/librarydialog.cpp (slotNext): Beside analog models now
also verilog and vhdl models are saved.
* schematic_file.cpp (giveNodeNames): Using new file component
netlist creators.
2007-05-08 Stefan Jahn <stefan@lkcc.org>
* verilogfile.cpp, vhdlfile.cpp, spicefile.cpp (createSubNetlist):
File components can now create the netlist parts on their own.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1237 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* dialogs/librarydialog.cpp (slotNext): Beside analog models now
also verilog and vhdl models are saved.
* schematic_file.cpp (giveNodeNames): Using new file component
netlist creators.
2007-05-08 Stefan Jahn <stefan@lkcc.org>
* verilogfile.cpp, vhdlfile.cpp, spicefile.cpp (createSubNetlist):
File components can now create the netlist parts on their own.
* textdoc.cpp (TextDoc): Using mono-spaced font in text
editor.
* schematic_file.cpp (giveNodeNames): Fixed loading of
Verilog files during VHDL run and vice versa.
* qucs.cpp (initContentListView): Added verilog files in
content tab.
2007-03-31 Stefan Jahn <stefan@lkcc.org>
* docs/qucsveri.1: Added manpage for the qucsveri wrapper
script for digital simulations.
2007-03-31 Stefan Jahn <stefan@lkcc.org>
* verilogfile.h: Added new component. Can handle external
verilog files. Can be used as subcircuit.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1167 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* textdoc.cpp (TextDoc): Using mono-spaced font in text
editor.
* schematic_file.cpp (giveNodeNames): Fixed loading of
Verilog files during VHDL run and vice versa.
* qucs.cpp (initContentListView): Added verilog files in
content tab.
2007-03-31 Stefan Jahn <stefan@lkcc.org>
* docs/qucsveri.1: Added manpage for the qucsveri wrapper
script for digital simulations.
2007-03-31 Stefan Jahn <stefan@lkcc.org>
* verilogfile.h: Added new component. Can handle external
verilog files. Can be used as subcircuit.
* schematic_file.cpp (createNetlist): Fixed a bug in
determining the simulation time of digital simulations
occurring when there are other disabled simulations
placed on the schematic.
(createSubNetlist): Implemented subcircuit modules for
Verilog simulations.
2007-03-28 Stefan Jahn <stefan@lkcc.org>
* d_flipflop.cpp (verilogCode): Fixed Verilog code of
D-flipflop. Is working now, can be used as template for
other flipflops.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1160 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* schematic_file.cpp (createNetlist): Fixed a bug in
determining the simulation time of digital simulations
occurring when there are other disabled simulations
placed on the schematic.
(createSubNetlist): Implemented subcircuit modules for
Verilog simulations.
2007-03-28 Stefan Jahn <stefan@lkcc.org>
* d_flipflop.cpp (verilogCode): Fixed Verilog code of
D-flipflop. Is working now, can be used as template for
other flipflops.
* qucsveri: New digital simulation wrapper for Icarus
verilog added.
* schematic_file.cpp (prepareNetlist): Started to implement
Verilog HDL interface.
2007-03-26 Stefan Jahn <stefan@lkcc.org>
* digi_sim.cpp (Digi_Sim): Can select between VHDL and Verilog
netlist format.
* component.cpp (get_Verilog_Code): Gate components and digital
sources now working with Verilog HDL.
git-svn-id: https://qucs.svn.sourceforge.net/svnroot/qucs/trunk@1157 b5b04e8c-4942-46c9-ab4f-83783d557d1c
* qucsveri: New digital simulation wrapper for Icarus
verilog added.
* schematic_file.cpp (prepareNetlist): Started to implement
Verilog HDL interface.
2007-03-26 Stefan Jahn <stefan@lkcc.org>
* digi_sim.cpp (Digi_Sim): Can select between VHDL and Verilog
netlist format.
* component.cpp (get_Verilog_Code): Gate components and digital
sources now working with Verilog HDL.
