dsm
af687e2ba7
windows specific macros generelized.
2024-07-04 10:42:54 +03:00
Vadim Kuznetsov
6ac212a1be
Recursively collect SPICE libraries on top of the netlist
2024-06-19 19:15:22 +03:00
Andrey Kalmykov
f00c6ef8c3
Add feature: saving symbol to file
...
"Schematic" object already can edit symbols, this commit makes
it able to save and load them.
Implementation is actually quite ugly in terms of code beauty
and industry standards, it's very "hacky". It consists of two
parts:
1. Teach "Save" and "Open" dialogs to deal with "*.sym" files
2. Modify "Schematic" object and some other parts of codebase
so that when a schematic is saved and the filename ends with
"*.sym", then only symbol parts are saved. And vice versa:
when a file with a name ending in "*.sym" is opened, then
skip the path for usual schematic, and load only symbol parts.
The "symbol file" is actually a stripped "schematic file" — no
properties, no components, etc.
2024-04-13 19:16:17 +03:00
Andrey Kalmykov
1577e73cc9
Set ~/QucsWorkspace as default workspace path
...
This commit
1. changes ~/.qucs to ~/QucsWorkspace
2. assignes more descriptive name to config property which holds
this path
2024-04-07 20:44:42 +03:00
Linfeng He
bfa2a00e1d
Add support for '_props.json' generation from osdi file.
...
Signed-off-by: Linfeng He <akirt@outlook.com>
2024-03-08 00:42:37 +08:00
Vadim Kuznetsov
1520c03290
Fixed crash if s2p contains noise data
2024-02-10 14:13:40 +03:00
Vadim Kuznetsov
87629ebb82
Merge pull request #528 from ra3xdh/fix_crashes
...
Fix crashes
2024-02-04 20:14:26 +03:00
Vadim Kuznetsov
0dea56cc90
Fixed crash on empty line
2024-02-04 16:23:07 +03:00
dwarning
e08bd10e0f
more precise parameter parsing for Verilog-A files
2024-02-04 12:26:46 +01:00
Vadim Kuznetsov
8ba88aa2b2
Added YLIN device support (Xyce) #452
2024-01-12 16:37:49 +03:00
ThomasZecha
e74b2d380e
Fix all build warnings/issues
...
-Unconditional re-build of flex/bison parser by fixing wrong dependencies
-Removed unused code causing compiler warnings
-Removed unused function variables
-Refactor switch-case statements to prevent compiler warnings
Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
2023-12-18 13:47:26 +01:00
Vadim Kuznetsov
a2d5119e37
Show error message from S2Spice
2023-10-07 11:23:01 +03:00
Vadim Kuznetsov
ef21e5eb6d
Simulation of S2P files works
2023-10-06 17:45:50 +03:00
Krasilnikov Sergey
ea517237a2
combine 2 xyce option
2023-06-05 23:52:53 +03:00
Radvall
2529cb89d5
Add isDigitalCircuit method to check if the circuit is digital. Add condition for digital circuit in slotSimulate
2023-05-15 21:49:25 +03:00
Krasilnikov Sergey
b70e615020
replace foreach macro
2023-01-15 01:17:09 +03:00
Vadim Kuznetsov
8a09b45939
Generate _props.json file without ADMS
2022-12-29 18:08:14 +03:00
luz paz
10c1ee639c
Fix various typos (including documenation)
...
Found via `codespell -q 3 -S *.ts,./qucs/ChangeLog -L ba,coul,inout,leaded,nd,numer,ro`
2022-07-05 07:08:28 -04:00
Vadim Kuznetsov
b697cc068b
Fix more naming conflicts
2022-02-20 16:25:39 +01:00
Vadim Kuznetsov
9aa8865d02
Everything compiles and qucs_s application runs
2022-02-14 15:37:11 +01:00
Vadim Kuznetzov
a1c36cf6bb
Fixed admsXml invocation when creating symbols
2016-11-05 18:35:01 +03:00
Vadim Kuznetzov
4a2e93b12f
Fixed after merge of spic4qucs_current
2016-11-05 17:44:57 +03:00
Vadim Kuznetzov
e6548302a7
Fixed double .subckt addition in nested Subcircuits
2016-10-09 10:34:03 +03:00
Vadim Kuznetzov
3bf80e3d50
Fixed conflicts after merging branch spice4qucs_current
2016-05-15 10:09:41 +03:00
Vadim Kuznetzov
97b944f3d2
Removed bools forwarding at AbstractSpiceKernel::createSubNetlsit()
2016-04-05 09:26:11 +03:00
Vadim Kuznetzov
0cd5c23279
Resolved conflicts after merging master
2016-01-31 18:32:42 +03:00
Vadim Kuznetzov
096ae088b6
Removed 'bools' forwarding in Schematic class
2016-01-08 15:53:29 +03:00
Vadim Kuznetzov
436b2217dc
Added checker for subcircuits
2015-11-11 11:34:17 +03:00
Vadim Kuznetzov
1b4d3b247b
Fix for Xyce
2015-11-11 11:32:45 +03:00
Vadim Kuznetzov
e84a0199c0
Reverted QPlainTextEdit and corrected Crystal example
2015-11-11 11:32:45 +03:00
Vadim Kuznetzov
de643622fe
Added spice_netlist() for SpiceFile
2015-11-11 11:32:37 +03:00
Vadim Kuznetzov
2a63568807
Backport to schematic_file.cpp to avoid conflicts
2015-11-11 11:32:36 +03:00
Vadim Kuznetzov
a1ce537b2a
Fixed charge equation errors in EDD and values normalization
2015-11-11 11:32:35 +03:00
Vadim Kuznetzov
8b98e34a53
Subcircuit support implemented for Ngspice and Xyce
2015-11-11 11:32:35 +03:00
Vadim Kuznetzov
570bbbccfb
Added Xyce libcomp support
2015-11-11 11:32:33 +03:00
Vadim Kuznetzov
4700d7d747
Refactoring
2015-11-11 11:32:33 +03:00
Vadim Kuznetzov
6a908fc86f
Refactoring
2015-11-11 11:32:33 +03:00
Vadim Kuznetzov
b1fe8a3f0b
Add library components support
2015-11-11 11:32:33 +03:00
Vadim Kuznetzov
581fea212e
NgSpice functionality moved from schematic_file.cpp to ngspicesimdialog.cpp
2015-11-11 11:28:57 +03:00
Vadim Kuznetzov
30c2c30f52
Added ngspice execution and printing results from labeled nodes
2015-11-11 11:28:56 +03:00
Vadim Kuznetzov
ee5571f932
Added named nodes to spice sim results output
2015-11-11 11:28:56 +03:00
Vadim Kuznetzov
66dc186048
Added results writing for spice simulation
2015-11-11 11:28:56 +03:00
Vadim Kuznetzov
7a37a04598
Prepared for demonstation
2015-11-11 11:28:56 +03:00
Vadim Kuznetzov
954e5e9969
Corrected first line comment for spice circuits
2015-11-11 11:28:56 +03:00
Vadim Kuznetzov
13c3da654d
Added isProbe property and spice_netlist() for Vrect
2015-11-11 11:28:55 +03:00
Vadim Kuznetzov
00e07e3b43
Added printing node voltages
2015-11-11 11:28:55 +03:00
Vadim Kuznetzov
2e550318cb
Implemented labeled wires determination
2015-11-11 11:28:55 +03:00
Vadim Kuznetzov
5e069464d7
Added Mega (10e6) conversion and corrected log sweep points calculation
2015-11-11 11:28:55 +03:00
Vadim Kuznetzov
714922f39e
Added isSimulation property analysis while generating spice netlist
2015-11-11 11:28:55 +03:00
Vadim Kuznetzov
018db5a72a
The first attempt to auto-create spice netlist
2015-11-11 11:28:54 +03:00
