Merge pull request #1278 from wawuwo/fix-1273-crash-in-one-two-wires

Fix crash when coordinates of wire ends are in wrong order

Fix #1273

.github/workflows/cmake.yml

@@ -1,46 +0,0 @@
-name: CMake Linux Qt5
-
-on:
-  push:
-    branches: [ "master", "current", "release/*" ]
-    paths: [ "**.cpp", "**.h", "**/CMakeLists.txt" ]
-  pull_request:
-    branches: [ "master", "current", "release/*" ]
-    paths: [ "**.cpp", "**.h", "**/CMakeLists.txt" ]
-
-env:
-  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
-  BUILD_TYPE: Release
-
-jobs:
-
-  
-          
-  build:
-    # The CMake configure and build commands are platform agnostic and should work equally well on Windows or Mac.
-    # You can convert this to a matrix build if you need cross-platform coverage.
-    # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix
-    runs-on: ubuntu-latest
-    
-    steps:
-    - uses: actions/checkout@v3
-
-    - name: InstallQt5
-      run: |
-          sudo apt-get update
-          sudo apt-get install -y qtbase5-dev qttools5-dev qtscript5-dev libqt5svg5-dev flex bison
-    - name: Configure CMake
-      # Configure CMake in a 'build' subdirectory. `CMAKE_BUILD_TYPE` is only required if you are using a single-configuration generator such as make.
-      # See https://cmake.org/cmake/help/latest/variable/CMAKE_BUILD_TYPE.html?highlight=cmake_build_type
-      run: cmake -B ${{github.workspace}}/build -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}}
-
-    - name: Build
-      # Build your program with the given configuration
-      run: cmake --build ${{github.workspace}}/build -j`nproc` --config ${{env.BUILD_TYPE}}
-
-    #- name: Test
-    #  working-directory: ${{github.workspace}}/build
-      # Execute tests defined by the CMake configuration.  
-      # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail
-      # run: ctest -C ${{env.BUILD_TYPE}}
-      

.github/workflows/deploy.yml

@@ -3,6 +3,8 @@ name: deploy
 on:
   push:
     branches: [ "master", "current", "release/*" ]
+    tags:
+        - '[0-9]+.[0-9]+.[0-9]+*'
   pull_request:
     branches: [ "master", "current", "release/*" ]
   workflow_dispatch:
@@ -12,15 +14,17 @@ env:
   EXECUTABLE_NAME: "qucs-s"
   PUBLISHER_NAME: "The Qucs-S Team"
   BUILD_TYPE: Release
-  QT_VERSION: 6.7.2
-  QUCS_MACOS_BIN: build/qucs/qucs-s.app/Contents/MacOS/bin
-  QUCS_MACOS_RESOURCES: build/qucs/qucs-s.app/Contents/MacOS/share/qucs-s
+  QT_VERSION: 6.8.2
+  QUCS_MACOS_BIN: ${{github.workspace}}/build/qucs/qucs-s.app/Contents/MacOS/bin
+  QUCS_MACOS_RESOURCES: ${{github.workspace}}/build/qucs/qucs-s.app/Contents/MacOS/share/qucs-s
+  NGSPICE_URL: https://downloads.sourceforge.net/project/ngspice/ng-spice-rework/44.2/ngspice-44.2_64.7z
   
 jobs:
   setup:
     runs-on: ubuntu-latest
     outputs:
       version: ${{ steps.read_version.outputs.version }}
+      short_hash: ${{ steps.read_version.outputs.short_hash }}
     steps:
     - name: Checkout repository
       uses: actions/checkout@v4
@@ -28,13 +32,28 @@ jobs:
     - name: Read version from file
       id: read_version
       run: |
-        VERSION=$(cat VERSION)
+        if [ "${{ github.ref_type }}" == "tag" ]; then
+          VERSION=${{ github.ref_name }}
+          SHORT_HASH=""
+        else 
+          MAJOR_MINOR=$(cut -d. -f1-2 VERSION)
+          VERSION="${MAJOR_MINOR}.99"
+          # Get the short hash of the current commit
+          COMMIT_HASH=$(echo ${{ github.sha }} | cut -c1-7)
+          SHORT_HASH="-$COMMIT_HASH"
+        fi
+        
         echo "VERSION=$VERSION" >> $GITHUB_ENV
         echo "version=$VERSION" >> $GITHUB_OUTPUT
         
-    - name: Print version 
-      run: echo "Qucs-S version is ${{ env.VERSION }}"
-
+        echo "SHORT_HASH=$SHORT_HASH" >> $GITHUB_ENV
+        echo "short_hash=$SHORT_HASH" >> $GITHUB_OUTPUT
+        
+    - name: Print version and hash
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
+      
   build-linux-appimage-qt6:
     runs-on: ubuntu-22.04
     needs: setup
@@ -44,53 +63,80 @@ jobs:
         submodules: recursive
 
     - name: Set version environment variable
-      run: echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
+      run: |
+        echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
+        echo "SHORT_HASH=${{ needs.setup.outputs.short_hash }}" >> $GITHUB_ENV
 
-    - name: Print version
-      run: echo "Qucs-S version is ${{ env.VERSION }}"
+    - name: Print version and hash
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
 
     - name: Install Dependencies
       run: |
           sudo apt-get update
-          sudo apt-get install -y qt6-base-dev qt6-tools-dev qt6-tools-dev-tools libglx-dev linguist-qt6 qt6-l10n-tools libqt6svg6-dev libgl1-mesa-dev
-          sudo apt-get install -y flex bison gperf dos2unix
-    - name: Configure CMake
-      # Configure CMake in a 'build' subdirectory. `CMAKE_BUILD_TYPE` is only required if you are using a single-configuration generator such as make.
-      # See https://cmake.org/cmake/help/latest/variable/CMAKE_BUILD_TYPE.html?highlight=cmake_build_type
-      run: cmake -B ${{github.workspace}}/build -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -DCMAKE_INSTALL_PREFIX=/usr -DWITH_QT6=ON
+          sudo apt-get install -y libglx-dev libgl1-mesa-dev flex bison gperf dos2unix flex bison gperf dos2unix cups libcups2-dev
+          sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-12 100 --slave /usr/bin/g++ g++ /usr/bin/g++-12
 
-    - name: Build
+    - name: 'Install Qt6'
+      uses: jurplel/install-qt-action@v4
+      with:
+        version: ${{env.QT_VERSION}}
+        host: 'linux'
+        target: 'desktop'
+        cache: true
+        arch: 'linux_gcc_64'
+        install-deps: 'true'
+        modules: 'qtcharts'
+
+
+    - name: '⚙️ Install CMake'
+      uses: lukka/get-cmake@latest
+
+    - name: 'Configure CMake'
+      run: |
+          cmake -B ${{github.workspace}}/build -G 'Ninja' \
+                -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} \
+                -DCMAKE_INSTALL_PREFIX=${{github.workspace}}/AppDir/usr \
+                -DWITH_QT6=ON \
+                -DCI_VERSION="${{env.VERSION}}"
+
+    - name: 'Build'
       # Build your program with the given configuration
       run: |
           cmake --build ${{github.workspace}}/build -j`nproc` --config ${{env.BUILD_TYPE}}
-          make -C ${{github.workspace}}/build install DESTDIR=${{github.workspace}}/AppDir
+          cmake --build ${{github.workspace}}/build --target install
 
       
-    - name: Install linuxdeploy
+    - name: 'Install linuxdeploy'
       run: |
-          wget https://github.com/linuxdeploy/linuxdeploy/releases/download/continuous/linuxdeploy-x86_64.AppImage
-          wget https://github.com/linuxdeploy/linuxdeploy-plugin-qt/releases/download/continuous/linuxdeploy-plugin-qt-x86_64.AppImage
+          wget -q --tries=3 --wait=5 \
+                https://github.com/linuxdeploy/linuxdeploy/releases/download/continuous/linuxdeploy-x86_64.AppImage
+          wget -q --tries=3 --wait=5 \
+                https://github.com/linuxdeploy/linuxdeploy-plugin-qt/releases/download/continuous/linuxdeploy-plugin-qt-x86_64.AppImage
           sudo apt-get install fuse libfuse2
           chmod +x linuxdeploy-x86_64.AppImage
           chmod +x linuxdeploy-plugin-qt-x86_64.AppImage
     
     - name: 'Create AppImage'
       run: |
-             export QMAKE=/usr/bin/qmake6
-             ./linuxdeploy-x86_64.AppImage --appdir ${{github.workspace}}/AppDir --desktop-file=${{github.workspace}}/AppDir/usr/share/applications/qucs-s.desktop --icon-file=${{github.workspace}}/AppDir/usr/share/icons/hicolor/256x256/apps/qucs-s.png --plugin=qt --output appimage
-             rm linuxdeploy-x86_64.AppImage
-             rm linuxdeploy-plugin-qt-x86_64.AppImage
-             mv *.AppImage ${{ env.APP_NAME }}-${{env.VERSION}}-linux-x86_64.AppImage
+          ./linuxdeploy-x86_64.AppImage --appdir ${{github.workspace}}/AppDir \
+                                        --desktop-file=${{github.workspace}}/AppDir/usr/share/applications/qucs-s.desktop \
+                                        --icon-file=${{github.workspace}}/AppDir/usr/share/icons/hicolor/256x256/apps/qucs-s.png \
+                                        --plugin=qt --output appimage
+          rm linuxdeploy-x86_64.AppImage
+          rm linuxdeploy-plugin-qt-x86_64.AppImage
+          mv *.AppImage ${{ env.APP_NAME }}-${{env.VERSION}}${{env.SHORT_HASH}}-linux-x86_64.AppImage
 
     - name: 'Upload artifact: AppImage'
       uses: actions/upload-artifact@v4
       with:
-          name: ${{ env.APP_NAME }}-${{env.VERSION}}-linux-x86_64
-          path: ${{ env.APP_NAME }}-${{env.VERSION}}-linux-x86_64.AppImage
-                
+          name: ${{ env.APP_NAME }}-${{env.VERSION}}${{env.SHORT_HASH}}-linux-x86_64
+          path: ${{ env.APP_NAME }}-${{env.VERSION}}${{env.SHORT_HASH}}-linux-x86_64.AppImage
+              
  
   build-mac-intel:
-    runs-on: macos-12
+    runs-on: macos-13
     needs: setup
     strategy:
       fail-fast: false
@@ -100,10 +146,14 @@ jobs:
         xcode-version: latest-stable
         
     - name: Set version environment variable
-      run: echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
+      run: |
+        echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
+        echo "SHORT_HASH=${{ needs.setup.outputs.short_hash }}" >> $GITHUB_ENV
 
-    - name: Print version
-      run: echo "Qucs-S version is ${{ env.VERSION }}"
+    - name: Print version and hash
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
       
     - uses: actions/checkout@v4
       with:
@@ -112,104 +162,13 @@ jobs:
     - name: 'Install Qt6'
       uses: jurplel/install-qt-action@v4
       with:
-        version: ${{env.QT_VERSION}}
-        host: 'mac'
-        target: 'desktop'
-        cache: true
-        arch: 'clang_64'
-        install-deps: 'true'
-       
-    - name: 'Install Dependencies'
-      shell: bash
-      run: |
-          brew install gperf dos2unix bison flex ninja graphicsmagick
-          echo 'export PATH="$(brew --prefix bison)/bin:$PATH"' >> /Users/runner/.bashrc
-          export LDFLAGS="-L$(brew --prefix bison)/lib"
-          source ~/.bashrc
-          brew link bison --force
-
-          
-    - name: 'Configure CMake'
-      run: |
-        qt-cmake -B ${{github.workspace}}/build  -G 'Ninja' \
-                  -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -DWITH_QT6=1
-
-    - name: 'Build Qucs-s'
-      run: |
-        cmake --build ${{github.workspace}}/build --parallel --config=${{env.BUILD_TYPE}}
-    
-    #- name: Install
-    #  run: | 
-    #    cd build
-    #    make install DESTDIR=./deploy
-    #    cd ..
-        
-    - name: 'Package App Bundle'
-      run: |
-        mkdir -p ${{env.QUCS_MACOS_BIN}}
-        mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/examples
-        mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/library
-        mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/symbols
-        cp -pR ./build/qucs-activefilter/qucs-sactivefilter.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-attenuator/qucs-sattenuator.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-filter/qucs-sfilter.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-powercombining/qucs-spowercombining.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-transcalc/qucs-strans.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucsator_rf/src/qucsator_rf ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucsator_rf/src/converter/qucsconv_rf ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./examples/* ${{env.QUCS_MACOS_RESOURCES}}/examples
-        cp -pR ./library/*.lib ${{env.QUCS_MACOS_RESOURCES}}/library
-        cp -pR ./library/*.blacklist ${{env.QUCS_MACOS_RESOURCES}}/library
-        cp -pR ./library/symbols/* ${{env.QUCS_MACOS_RESOURCES}}/symbols
-        macdeployqt ./build/qucs/qucs-s.app
-        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sactivefilter.app
-        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sattenuator.app
-        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sfilter.app
-        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-spowercombining.app
-        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-strans.app
-        strip ${{env.QUCS_MACOS_BIN}}/qucsator_rf
-        strip ${{env.QUCS_MACOS_BIN}}/qucsconv_rf 
-        codesign --force --deep --sign - ./build/qucs/qucs-s.app
-        npm install --global create-dmg
-        create-dmg ./build/qucs/qucs-s.app ./build/qucs/ || true
-        cp -pR ./build/qucs/qucs-*.dmg ./${{ env.APP_NAME }}-${{env.VERSION}}-macOS-x86_64.dmg
-
-    - name: 'Upload build artifacts'
-      uses: actions/upload-artifact@v4
-      with:
-        name: ${{ env.APP_NAME }}-${{env.VERSION}}-macOS-x86_64
-        path: ${{ env.APP_NAME }}-${{env.VERSION}}-macOS-x86_64.dmg
-
-      
-  build-mac-arm:
-    runs-on: macos-latest
-    needs: setup
-    strategy:
-      fail-fast: false
-    steps:
-    - uses: maxim-lobanov/setup-xcode@v1
-      with:
-        xcode-version: latest-stable
-    
-    - name: Set version environment variable
-      run: echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
-
-    - name: Print version
-      run: echo "Qucs-S version is ${{ env.VERSION }}"
-          
-    - uses: actions/checkout@v4
-      with:
-        submodules: recursive
-
-    - name: 'Install Qt6'
-      uses: jurplel/install-qt-action@v4
-      with:
-        version: ${{env.QT_VERSION}}
+        version: '6.2.4'
         host: 'mac'
         target: 'desktop'
         cache: true
         arch: 'clang_64'
         install-deps: 'true'
+        modules: 'qtcharts'
        
     - name: 'Install Dependencies'
       shell: bash
@@ -219,22 +178,18 @@ jobs:
           export LDFLAGS="-L$(brew --prefix bison)/lib"
           source ~/.bashrc
           brew link bison --force
-
-          
+         
     - name: 'Configure CMake'
       run: |
-        qt-cmake -B ${{github.workspace}}/build  -G 'Ninja' \
-                  -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -DWITH_QT6=1
+        cmake -B ${{github.workspace}}/build  -G 'Ninja' \
+              -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -DWITH_QT6=1 \
+              -DCMAKE_OSX_DEPLOYMENT_TARGET=10.14 \
+              -DCMAKE_OSX_ARCHITECTURES="x86_64" \
+              -DCI_VERSION="${{env.VERSION}}"
 
     - name: 'Build Qucs-s'
       run: |
         cmake --build ${{github.workspace}}/build --parallel --config=${{env.BUILD_TYPE}}
-    
-    #- name: Install
-    #  run: | 
-    #    cd build
-    #    make install DESTDIR=./deploy
-    #    cd ..
         
     - name: 'Package App Bundle'
       run: |
@@ -242,44 +197,251 @@ jobs:
         mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/examples
         mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/library
         mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/symbols
-        cp -pR ./build/qucs-activefilter/qucs-sactivefilter.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-attenuator/qucs-sattenuator.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-filter/qucs-sfilter.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-powercombining/qucs-spowercombining.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucs-transcalc/qucs-strans.app ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucsator_rf/src/qucsator_rf ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./build/qucsator_rf/src/converter/qucsconv_rf ${{env.QUCS_MACOS_BIN}}
-        cp -pR ./examples/* ${{env.QUCS_MACOS_RESOURCES}}/examples
-        cp -pR ./library/*.lib ${{env.QUCS_MACOS_RESOURCES}}/library
-        cp -pR ./library/*.blacklist ${{env.QUCS_MACOS_RESOURCES}}/library
-        cp -pR ./library/symbols/* ${{env.QUCS_MACOS_RESOURCES}}/symbols
-        macdeployqt ./build/qucs/qucs-s.app
+        cp -pR ${{github.workspace}}/build/qucs-activefilter/qucs-sactivefilter.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-attenuator/qucs-sattenuator.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-filter/qucs-sfilter.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-powercombining/qucs-spowercombining.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-s-spar-viewer/qucs-sspar-viewer.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-transcalc/qucs-strans.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucsator_rf/src/qucsator_rf ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucsator_rf/src/converter/qucsconv_rf ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/examples/* ${{env.QUCS_MACOS_RESOURCES}}/examples
+        cp -pR ${{github.workspace}}/library/*.lib ${{env.QUCS_MACOS_RESOURCES}}/library
+        cp -pR ${{github.workspace}}/library/*.blacklist ${{env.QUCS_MACOS_RESOURCES}}/library
+        cp -pR ${{github.workspace}}/library/symbols/* ${{env.QUCS_MACOS_RESOURCES}}/symbols
+        macdeployqt ${{github.workspace}}/build/qucs/qucs-s.app
         macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sactivefilter.app
         macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sattenuator.app
         macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sfilter.app
         macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-spowercombining.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sspar-viewer.app
         macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-strans.app
         strip ${{env.QUCS_MACOS_BIN}}/qucsator_rf
-        strip ${{env.QUCS_MACOS_BIN}}/qucsconv_rf
-        codesign --force --deep --sign - ./build/qucs/qucs-s.app
+        strip ${{env.QUCS_MACOS_BIN}}/qucsconv_rf 
+        codesign --force --deep --sign - ${{github.workspace}}/build/qucs/qucs-s.app
         npm install --global create-dmg
-        create-dmg ./build/qucs/qucs-s.app ./build/qucs/ || true
-        cp -pR ./build/qucs/qucs-*.dmg ./${{ env.APP_NAME }}-${{env.VERSION}}-macOS-arm64.dmg
+        create-dmg ${{github.workspace}}/build/qucs/qucs-s.app ${{github.workspace}}/build/qucs/ || true
+        cp -pR ${{github.workspace}}/build/qucs/qucs-*.dmg ${{github.workspace}}/${{ env.APP_NAME }}-${{env.VERSION}}-macOSX-x86_64.dmg
+
+    - name: 'Upload build artifacts'
+      uses: actions/upload-artifact@v4
+      with:
+        name: ${{ env.APP_NAME }}-${{env.VERSION}}-macOSX-x86_64
+        path: ${{ env.APP_NAME }}-${{env.VERSION}}-macOSX-x86_64.dmg
+        
+
+  build-mac-universal:
+    runs-on: macos-15
+    needs: setup
+    strategy:
+      fail-fast: false
+    steps:
+    - uses: maxim-lobanov/setup-xcode@v1
+      with:
+        xcode-version: latest-stable
+    
+    - name: Set version environment variable
+      run: |
+        echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
+        echo "SHORT_HASH=${{ needs.setup.outputs.short_hash }}" >> $GITHUB_ENV
+
+    - name: Print version and hash
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
+          
+    - uses: actions/checkout@v4
+      with:
+        submodules: recursive
+
+    - name: 'Install Qt6'
+      uses: jurplel/install-qt-action@v4
+      with:
+        version: ${{env.QT_VERSION}}
+        host: 'mac'
+        target: 'desktop'
+        cache: true
+        arch: 'clang_64'
+        install-deps: 'true'
+        modules: 'qtcharts'
+        
+    - name: 'Install Dependencies'
+      shell: bash
+      run: |
+        brew install gperf dos2unix bison flex ninja graphicsmagick imagemagick
+        echo 'export PATH="$(brew --prefix bison)/bin:$PATH"' >> /Users/runner/.bashrc
+        export LDFLAGS="-L$(brew --prefix bison)/lib"
+        source ~/.bashrc
+        brew link bison --force
+
+          
+    - name: 'Configure CMake'
+      run: |
+        cmake -B ${{github.workspace}}/build  -G 'Ninja' \
+              -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -DWITH_QT6=1 \
+              -DCMAKE_OSX_DEPLOYMENT_TARGET=12.0 \
+              -DCMAKE_OSX_ARCHITECTURES="arm64;x86_64" \
+              -DCI_VERSION="${{env.VERSION}}"
+
+    - name: 'Build Qucs-s'
+      run: |
+        cmake --build ${{github.workspace}}/build --parallel --config=${{env.BUILD_TYPE}}
+        
+    - name: 'Package App Bundle'
+      run: |
+        mkdir -p ${{env.QUCS_MACOS_BIN}}
+        mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/examples
+        mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/library
+        mkdir -p ${{env.QUCS_MACOS_RESOURCES}}/symbols
+        cp -pR ${{github.workspace}}/build/qucs-activefilter/qucs-sactivefilter.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-attenuator/qucs-sattenuator.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-filter/qucs-sfilter.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-powercombining/qucs-spowercombining.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-s-spar-viewer/qucs-sspar-viewer.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucs-transcalc/qucs-strans.app ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucsator_rf/src/qucsator_rf ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/build/qucsator_rf/src/converter/qucsconv_rf ${{env.QUCS_MACOS_BIN}}
+        cp -pR ${{github.workspace}}/examples/* ${{env.QUCS_MACOS_RESOURCES}}/examples
+        cp -pR ${{github.workspace}}/library/*.lib ${{env.QUCS_MACOS_RESOURCES}}/library
+        cp -pR ${{github.workspace}}/library/*.blacklist ${{env.QUCS_MACOS_RESOURCES}}/library
+        cp -pR ${{github.workspace}}/library/symbols/* ${{env.QUCS_MACOS_RESOURCES}}/symbols
+        macdeployqt ${{github.workspace}}/build/qucs/qucs-s.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sactivefilter.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sattenuator.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sfilter.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-spowercombining.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-sspar-viewer.app
+        macdeployqt ${{env.QUCS_MACOS_BIN}}/qucs-strans.app
+        strip ${{env.QUCS_MACOS_BIN}}/qucsator_rf
+        strip ${{env.QUCS_MACOS_BIN}}/qucsconv_rf 
+        codesign --force --deep --sign - ${{github.workspace}}/build/qucs/qucs-s.app
+        npm install --global create-dmg
+        create-dmg ${{github.workspace}}/build/qucs/qucs-s.app ${{github.workspace}}/build/qucs/ || true
+        cp -pR ${{github.workspace}}/build/qucs/qucs-*.dmg ${{github.workspace}}/${{ env.APP_NAME }}-${{env.VERSION}}-macOS.dmg
     
     - name: 'Upload build artifacts'
       uses: actions/upload-artifact@v4
       with:
-        name: ${{ env.APP_NAME }}-${{env.VERSION}}-macOS-arm64
-        path: ${{ env.APP_NAME }}-${{env.VERSION}}-macOS-arm64.dmg
-      
-  build-windows:
-    runs-on: windows-2022
+        name: ${{ env.APP_NAME }}-${{env.VERSION}}-macOS
+        path: ${{ env.APP_NAME }}-${{env.VERSION}}-macOS.dmg
+
+  build-windows-msvc:
+    runs-on: windows-latest
+    needs: setup
+    strategy:
+      fail-fast: false
+    defaults:
+      run:
+        shell: pwsh
+    steps:  
+    - name: Disable autocrlf in Git
+      run: |
+        git config --global core.autocrlf false
+        git config --global core.eol lf
+
+    - name: Set version environment variable
+      run: |
+        echo "VERSION=${{ needs.setup.outputs.version }}" | Out-File -FilePath $env:GITHUB_ENV -Encoding utf8 -Append
+        echo "SHORT_HASH=${{ needs.setup.outputs.short_hash }}" | Out-File -FilePath $env:GITHUB_ENV -Encoding utf8 -Append
+
+    - name: Print version and hash
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
+
+    - name: Checkout repository
+      uses: actions/checkout@v4
+    
+    - name: 'Install Qt6'
+      uses: jurplel/install-qt-action@v4
+      with:
+        version: ${{env.QT_VERSION}}
+        host: 'windows'
+        target: 'desktop'
+        cache: true
+        arch: 'win64_msvc2022_64'
+        install-deps: 'true'
+        modules: 'qtcharts'
+
+    - name: '⚙️ Install CMake'
+      uses: lukka/get-cmake@latest
+
+    - name: '🛠 Setup MSVC Development Environment'
+      uses: TheMrMilchmann/setup-msvc-dev@v3
+      with:
+        arch: x64
+      
+    - name: 'Configure CMake'
+      run: |
+        cmake -B ${{github.workspace}}\build -G 'Ninja' -DWITH_QT6=1  `
+              -DCMAKE_INSTALL_PREFIX=${{github.workspace}}\build\qucs-suite  `
+              -DCMAKE_CXX_COMPILER=cl -DCMAKE_C_COMPILER=cl  `
+              -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}}   `
+              -DCI_VERSION="${{env.VERSION}}"
+
+    - name: 'Build Qucs-s'
+      run: |
+        cmake --build ${{github.workspace}}\build --parallel --config=${{env.BUILD_TYPE}}
+          
+    - name: 'Cmake install'
+      run: |
+        cmake --build ${{github.workspace}}\build --target install
+    
+    - name: 'Deploy Qt6 dependencies'
+      run: |
+        $qucs_bin_dir = "${{github.workspace}}\build\qucs-suite\bin"
+        $executables = @(
+          "qucs-s.exe", "qucs-sactivefilter.exe", "qucs-sattenuator.exe",
+          "qucs-sfilter.exe", "qucs-spowercombining.exe", "qucs-strans.exe",
+          "qucs-sspar-viewer.exe"
+        )
+
+        $executables | ForEach-Object { windeployqt "$qucs_bin_dir\$_"  --no-translations --no-opengl-sw --no-system-d3d-compiler --no-network --no-compiler-runtime }
+
+    - name: 'Add ngspice to release'
+      run: |
+        $qucs_dir = "${{github.workspace}}\build\qucs-suite"
+        curl -sL --retry 3 --retry-delay 5 -o ngspice.7z ${{ env.NGSPICE_URL }}
+        7z.exe x ngspice.7z -ongspice
+        New-Item -ItemType Directory -Path "$qucs_dir\lib\ngspice" -Force
+        Copy-Item -Recurse -Force ngspice\Spice64\bin\ $qucs_dir
+        Copy-Item -Recurse -Force ngspice\Spice64\lib\ $qucs_dir
+        Copy-Item -Recurse -Force ngspice\Spice64\share\ $qucs_dir
+            
+    - name: 'Create zip archive for release'
+      run: |
+        $qucs_dir = "${{github.workspace}}\build\qucs-suite"
+        New-Item -ItemType Directory -Path "$qucs_dir\misc" -Force
+        Copy-Item -Recurse -Force "contrib\InnoSetup\misc" "$qucs_dir"
+        cd $qucs_dir
+        $zipName = "${env:APP_NAME}-${env:VERSION}${env:SHORT_HASH}-MSVC-x64.zip"
+        Compress-Archive -Path ./bin, ./share, ./lib, ./misc -DestinationPath "${{github.workspace}}\$zipName"
+        cd ${{github.workspace}}
+    
+    - name: Compile .ISS to .EXE Installer
+      uses: Minionguyjpro/Inno-Setup-Action@v1.2.5
+      with:
+        path: contrib/InnoSetup/qucs.iss
+        options: /Qp /O"${{github.workspace}}" /DAPPNAME=${{ env.APP_NAME }} /DRELEASE="${{ env.VERSION }}${{ env.SHORT_HASH }}-MSVC"
+
+    - name: Upload build artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-MSVC-x64
+        path: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-MSVC-x64.zip
+    
+    - name: Upload exe artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-MSVC-setup
+        path: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-MSVC-setup.exe
+      
+  build-windows:
+    runs-on: windows-2022
+    continue-on-error: true
     needs: setup
     strategy:
       fail-fast: false
-      matrix:
-        environment:
-          - ucrt64
     defaults:
       run:
         shell: msys2 {0}
@@ -294,10 +456,13 @@ jobs:
       shell: pwsh
       run: |
         echo "VERSION=${{ needs.setup.outputs.version }}" | Out-File -FilePath $env:GITHUB_ENV -Encoding utf8 -Append
+        echo "SHORT_HASH=${{ needs.setup.outputs.short_hash }}" | Out-File -FilePath $env:GITHUB_ENV -Encoding utf8 -Append
 
-    - name: Print version
+    - name: Print version and hash
       shell: pwsh
-      run: echo "Qucs-S version is ${{ env.VERSION }}"
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
 
     - name: Checkout repository
       uses: actions/checkout@v4
@@ -307,129 +472,174 @@ jobs:
     - name: Set up MSYS2 environment
       uses: msys2/setup-msys2@v2
       with:
-        msystem: ${{ matrix.environment }}
+        msystem: ucrt64
         cache: true
         update: true
-        install: >-
-          bison 
-          flex
-          dos2unix
-          curl
-          zip
-          unzip
-        pacboy: >-
-          cmake:p 
-          gcc:p 
-          qt6-base:p 
-          qt6-tools:p 
-          qt6-svg:p 
-          make:p 
-          ninja:p
-          python:p 
-          gperf:p
-          github-cli:p
+        install: bison flex dos2unix curl zip p7zip
+        pacboy: cmake:p gcc:p qt6-base:p qt6-tools:p qt6-svg:p make:p ninja:p python:p gperf:p github-cli:p qt6-charts:p
+
 
     - name: Build project with CMake
       run: |
-        cmake.exe -B build/ -G "MinGW Makefiles" -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} -DWITH_QT6=ON
-        cmake.exe --build build/ -j$(nproc) --config ${{env.BUILD_TYPE}}
+        cmake.exe -B build/ -G 'Ninja' \
+                  -DCMAKE_BUILD_TYPE=${{env.BUILD_TYPE}} \
+                  -DCMAKE_INSTALL_PREFIX=build/qucs-suite  \
+                  -DWITH_QT6=ON \
+                  -DCI_VERSION="${{env.VERSION}}"
+        cmake.exe --build build/ --parallel --config ${{env.BUILD_TYPE}}
 
     - name: Make install
       run: |
-        cd build/ && mingw32-make.exe install DESTDIR=./ -j$(nproc)
-        cp -rf 'Program Files (x86)/qucs-suite' ./
-        cd ..
+        cmake --build build/ --target install
         strip build/qucs-suite/bin/*.exe 
 
     - name: Deploy Qt6 dependencies
       run: |
-        windeployqt-qt6.exe build/qucs-suite/bin/qucs-s.exe  --svg --no-translations 
-        windeployqt-qt6.exe build/qucs-suite/bin/qucs-sactivefilter.exe  --no-translations 
-        windeployqt-qt6.exe build/qucs-suite/bin/qucs-sattenuator.exe  --no-translations 
-        windeployqt-qt6.exe build/qucs-suite/bin/qucs-sfilter.exe  --no-translations 
-        windeployqt-qt6.exe build/qucs-suite/bin/qucs-spowercombining.exe  --no-translations 
-        windeployqt-qt6.exe build/qucs-suite/bin/qucs-strans.exe  --no-translations
+        deploy_tool="windeployqt-qt6.exe"
+        bin_dir="build/qucs-suite/bin"
+        options="--svg --no-translations --no-system-d3d-compiler --no-network"
+        
+        executables=(
+          "qucs-s.exe" "qucs-sactivefilter.exe" "qucs-sattenuator.exe"
+          "qucs-sfilter.exe" "qucs-spowercombining.exe" "qucs-strans.exe"
+          "qucs-sspar-viewer.exe"
+        )
 
+        for exe in "${executables[@]}"; do
+          $deploy_tool "$bin_dir/$exe" $options
+        done
+          
     - name: Copy non-Qt DLLs to bin directory
       run: |
         shopt -s extglob
-        FILES=$(ldd build/qucs-suite/bin/qucs-s.exe | awk '($3 ~ /\/${{ matrix.environment }}\/bin\//) {print $3}')
+        FILES=$(ldd build/qucs-suite/bin/qucs-s.exe | awk '($3 ~ /\/ucrt64\/bin\//) {print $3}')
         for file in $FILES; do
           if [[ $(basename "$file") != Qt6* ]]; then
             cp -r "$file" build/qucs-suite/bin
           fi
         done
+        
+    - name: Add ngspice to release
+      run: |
+        curl -sL --retry 3 --retry-delay 5 -o ngspice.7z ${{ env.NGSPICE_URL }}
+        7z x ngspice.7z -ongspice
+        mkdir -p build/qucs-suite/lib/ngspice
+        cp -rf ngspice/Spice64/bin/ build/qucs-suite
+        cp -rf ngspice/Spice64/lib/ build/qucs-suite
+        cp -rf ngspice/Spice64/share/ build/qucs-suite
             
     - name: Create zip archive for release
       run: |
+        mkdir -p build/qucs-suite/misc
+        cp -rf contrib/InnoSetup/misc build/qucs-suite/
         cd build/qucs-suite
-        zip -r ../../${{ env.APP_NAME }}-${{ env.VERSION }}-win64.zip ./bin ./share
+        zip -r ../../${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-win64.zip ./bin ./share ./lib ./misc
         cd ../..
+
+    - name: Compile .ISS to .EXE Installer
+      uses: Minionguyjpro/Inno-Setup-Action@v1.2.5
+      with:
+        path: contrib/InnoSetup/qucs.iss
+        options: /Qp /O"${{github.workspace}}" /DAPPNAME=${{ env.APP_NAME }} /DRELEASE="${{ env.VERSION }}${{ env.SHORT_HASH }}"
         
     - name: Upload build artifacts
       uses: actions/upload-artifact@v4
       with:
-        name: ${{ env.APP_NAME }}-${{ env.VERSION }}-win64
-        path: ${{ env.APP_NAME }}-${{ env.VERSION }}-win64.zip
+        name: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-win64
+        path: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-win64.zip
+
+    - name: Upload exe artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-setup
+        path: ${{ env.APP_NAME }}-${{ env.VERSION }}${{ env.SHORT_HASH }}-setup.exe
 
   create-release:
     runs-on: ubuntu-latest
-    if: github.event_name == 'push'
-    needs:
-     - setup
-     - build-linux-appimage-qt6
-     - build-mac-intel
-     - build-mac-arm
-     - build-windows
+    if: github.event_name != 'pull_request'
+    needs: [setup, build-linux-appimage-qt6, build-mac-intel, build-mac-universal, build-windows]
     steps:
     - name: Checkout repository
       uses: actions/checkout@v4
 
+    - name: Set version environment variable
+      run: |
+        echo "VERSION=${{ needs.setup.outputs.version }}" >> $GITHUB_ENV
+        echo "SHORT_HASH=${{ needs.setup.outputs.short_hash }}" >> $GITHUB_ENV
+
+    - name: Print version and hash
+      run: |
+        echo "Qucs-S version is ${{ env.VERSION }}"
+        echo "Qucs-S short hash is ${{ env.SHORT_HASH }}"
+
     - name: Download build artifacts
       uses: actions/download-artifact@v4
       with:
         path: ~/artifacts
+        merge-multiple: true
 
     - name: Calculate SHA-256 checksums
       run: |
         cd ~/artifacts
         > hashes.sha256
-        for file in $(find . -type f \( -name "*.zip" -o -name "*.dmg" -o -name "*.AppImage" \)); do
+        for file in $(find . -type f \( -name "*-setup.exe" ! -name "*-MSVC-setup.exe" -o -name "*-win64.zip" -o -name "*.dmg" -o -name "*.AppImage" \)); do
           filename=$(basename "$file")
           sha256sum "$file" | awk -v fname="$filename" '{print $1 " *" fname}' >> hashes.sha256
         done
         cd ..
+        tree ~/artifacts
 
-    - name: Check if continuous_build release exists
+    - name: Setup Release Information
       run: |
-        if gh release view continuous_build --repo $GITHUB_REPOSITORY &> /dev/null; then
-          gh release delete continuous_build --repo $GITHUB_REPOSITORY --cleanup-tag  --yes
+        if [ "${{github.ref_type}}" == "tag" ]; then
+          echo "PRERELEASE=" >> $GITHUB_ENV
+          echo "RELEASE_NAME=Qucs-S ${{ github.ref_name }}" >> $GITHUB_ENV
+          echo "TAG_NAME=${{ github.ref_name }}" >> $GITHUB_ENV
+          echo "RELEASE_NOTES=--generate-notes" >> $GITHUB_ENV
+        else
+          echo "PRERELEASE=-p" >> $GITHUB_ENV
+          echo "RELEASE_NAME=Continuous Build" >> $GITHUB_ENV
+          echo "TAG_NAME=continuous_build" >> $GITHUB_ENV
+          echo "RELEASE_NOTES=--notes \"Automated release for commit ${{ github.sha }}\"" >> $GITHUB_ENV
         fi
-      env:
-        GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-    
+          
     - name: Create GitHub Release
-      continue-on-error: true
+      continue-on-error: false
       run: |
-        # Find existing zip and dmg files
-        zip_files=$(find ~/artifacts -name "*.zip" -print0 | xargs -0 echo)
+        # Find existing artifact files
+        hash_files=$(find ~/artifacts -name "*.sha256" -print0 | xargs -0 echo)
+        exe_files=$(find ~/artifacts -name "*-setup.exe" ! -name "*-MSVC-setup.exe" -print0 | xargs -0 echo)
+        zip_files=$(find ~/artifacts -name "*-win64.zip" -print0 | xargs -0 echo)
         dmg_files=$(find ~/artifacts -name "*.dmg" -print0 | xargs -0 echo)
         appimage_files=$(find ~/artifacts -name "*.AppImage" -print0 | xargs -0 echo)
+
+        # Check existing release and delete if it's exist
+        if gh release view ${{ env.TAG_NAME }} --repo $GITHUB_REPOSITORY &> /dev/null; then
+          if [ "${{ env.TAG_NAME }}" == "continuous_build" ]; then
+            gh release delete ${{ env.TAG_NAME }} --repo $GITHUB_REPOSITORY --cleanup-tag  --yes
+          else
+            gh release delete ${{ env.TAG_NAME }} --repo $GITHUB_REPOSITORY
+          fi
+          echo "${{ env.TAG_NAME }} deleted!"
+        fi
         
-        # Create release only if there are files to upload
-        if [ -n "$zip_files" ] || [ -n "$dmg_files" ] || [ -n "$appimage_files" ]; then
-          gh release create continuous_build \
-            $zip_files \
-            $dmg_files \
-            $appimage_files \
-            ~/artifacts/hashes.sha256 \
-            -p \
-            --repo $GITHUB_REPOSITORY \
-            --title "Continuous build" \
-            --notes "Automated release for commit ${{ github.sha }}"
+        if [ -n "$exe_files" ] && [ -n "$zip_files" ] && [ -n "$dmg_files" ] && [ -n "$appimage_files" ]; then
+          gh release create ${{ env.TAG_NAME }} \
+                            $exe_files \
+                            $zip_files \
+                            $dmg_files \
+                            $appimage_files \
+                            $hash_files \
+                            ${{ env.PRERELEASE }} \
+                            --repo $GITHUB_REPOSITORY \
+                            --title "${{ env.RELEASE_NAME }}" \
+                            ${{ env.RELEASE_NOTES }}
+
+            echo "${{ env.TAG_NAME }} release created!"
         else
           echo "No artifacts to upload."
+          exit 1
         fi
-
+        
       env:
         GH_TOKEN: ${{ secrets.GITHUB_TOKEN }}

.gitignore

@@ -56,3 +56,7 @@ __pycache__
 .vscode/launch.json
 .vscode/settings.json
 .vscode/tasks.json
+/cmake-build-debug/
+.cache/
+/qt/
+build-qucs-s-spar-viewer-Desktop-Debug/

CMakeLists.txt

@@ -15,7 +15,14 @@ endif()
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 
 file (STRINGS "${qucs-suite_SOURCE_DIR}/VERSION" QUCS_VERSION)
-message(STATUS "Configuring Qucs: VERSION ${QUCS_VERSION}")
+
+if(DEFINED CI_VERSION)
+    set(PROJECT_VERSION "${CI_VERSION}")
+else()
+    set(PROJECT_VERSION "${QUCS_VERSION}")
+endif()
+
+message(STATUS "Configuring Qucs: VERSION ${PROJECT_VERSION}")
 
 set(GIT "")
 if(EXISTS ${CMAKE_SOURCE_DIR}/.git )
@@ -32,13 +39,10 @@ endif()
 
 message(STATUS "${PROJECT_NAME} ${CMAKE_INSTALL_PREFIX} ${qucs-suite_BINARY_DIR}" )
 
-if(WITH_QT6)
-    set(QT_VERSION_MAJOR 6)
-else()
-    set(QT_VERSION_MAJOR 5)
-endif()
-find_package(Qt${QT_VERSION_MAJOR} REQUIRED COMPONENTS Core Gui Widgets LinguistTools)
-message(STATUS "QT Major Version: " ${QT_VERSION_MAJOR})
+find_package(Qt6 REQUIRED COMPONENTS Core Gui Widgets LinguistTools)
+set(QT_VERSION ${Qt6Core_VERSION})
+
+message(STATUS "Qt Version: " ${QT_VERSION})
 
 add_definitions(${QT_DEFINITIONS})
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
@@ -56,6 +60,7 @@ add_subdirectory( qucs-filter )
 add_subdirectory( library )
 add_subdirectory( qucs-transcalc )
 add_subdirectory( qucs-powercombining )
+add_subdirectory( qucs-s-spar-viewer )
 #add_subdirectory( examples )
 if(EXISTS ${CMAKE_SOURCE_DIR}/qucsator_rf/CMakeLists.txt)
     add_subdirectory(qucsator_rf)
@@ -70,6 +75,8 @@ add_subdirectory( translations )
 
 install(DIRECTORY "examples" DESTINATION "share/${QUCS_NAME}")
 
+install(FILES contrib/io.github.ra3xdh.qucs_s.metainfo.xml DESTINATION ${CMAKE_INSTALL_PREFIX}/share/metainfo)
+
 #
 # Custom uninstall target
 #

NEWS.md

@@ -1,3 +1,165 @@
+# Qucs-S 25.1.1
+
+## Bugfixes and general improvemnt
+
+* Add UIC option for FFT analysis #1261
+* Improve wire editing #1253
+* Fix crash when deleting shorted devices #1254
+* Fix removing labels #1255
+
+## Localization
+
+* Russian translation update #1246
+
+## Packaging
+
+* Update Gentoo ebuidl #1252
+
+## Known issues
+
+* The .OPTIONS and .FUNC devices not working properly. Use the *INCLUDE SCRIPT* instead. See #1260
+
+# Qucs-S 25.1.0
+
+## New features
+
+* Component properties dialog redesign #1054
+* CDL netlist export #1165
+* Implemented plotting XSPICE digital nodes #1138
+* Add individual CLI oparameters setting for each simulator #1152
+* Add .CSPARAM virtual device #1136
+* Add Qt aplication style selection #1118
+* Add default graph line thickness setting #1066
+* Add setting for grid visibility  #1065
+* Allow parameter passing for SPICE file device #1197
+* S-parameter files viewer improvements #1133
+* Added background when renderign DC bias labels #1121
+* Added possibility to create libraries from SpiceLibraryDevice components #944 #1210
+* Added two new wire forms #1232
+
+## Bugfixes and general improvemnt
+
+* CI improvement #1103 #1091 #1086
+* Fixed graph renderign performance #984
+* Fixed SPICE models processing bugs #861 #1055 #1090 #1142
+* Default shorted resistance changed from 0 Ohms to 1/GMIN #1116
+* Fixed diagram memory leak #1139
+* Added offset parameter for AC current source #1218
+* Fixed schematic editing issues #1159 #1134
+
+## Component library
+
+This release contains a massive library extention:
+
+* Added libraries for 74HC, 74LV, CD4000 digital ICs for analog mode #1034 #1160
+* Added XSPICE generic logic gates library for analog mode #1199
+* Added XSPICE digital auxillary devices #1193
+* Added Laser diode library #942
+* Added generic triac device in Thyristor.lib #924
+* Added vaccum tubes extended library #846 #1216
+* Added neon bulb model #846 #1216
+* Added MOC3063/MOC3062 optocouple models #846 #1216
+* Added Analog ICs and dual gate MOSFET libraries #1229
+* Added RC with parasitics library #1240
+
+## Packaging
+
+* Qt5 build deprecated; switch to Qt6 by default #938
+* Windows package improvements #1123
+
+## Localization
+
+* Update Turkish translation #1094
+
+
+# Qucs-S 24.4.1
+
+## Bugfixes
+
+* Improved diagrams rendering speed #1042
+* Fixed hardcoded version in LC Cauer filter #1039
+* Fixed pulsed current source issues #1059
+* Fixed show exit status if Ngspice crashes #1001
+
+## Localization
+
+* Russian translation update #1038
+
+## Packaging
+
+* Prepare for Flatpak package #51
+
+# Qucs-S 24.4.0
+
+## New features
+
+* Implemnted touchstone (S2P) files viewer tool #936
+* VC resistor made available for SPICE and ADMS-independent #959
+
+## Library update
+
+* Added SPICE_Tline library containing transmission lines for Ngspice #896
+
+## Bugfixes
+
+* Don't resolve paths to relaive if document is not saved and not belong to project #951
+* Allow variables for potentiometer and diode device properties #1021 #1013
+* Fixed simulation properties editing #968
+* Fixed disbale simulation for XYCE #965
+* Fixed running simulation in CLI mode #962
+* Fixed memory leaks #960
+* Fixed BJTsub and diode devices #983
+* Fixed Schottky diode symbol appearence #1027
+* Fixed crash if no simulator found on the first start #979
+* Fixed artifacts when selecting elliptic arc #987
+* Fixed text rendiering for Qt6.8.0 #1002
+
+## QucsatorRF
+
+* QucsatorRF updated to v1.0.3. See the release notes. 
+
+# Qucs-S 24.3.2
+
+## Bugfixes
+
+* Fixed editing of File-type properties #948
+* Implemented @model[param] syntax recognition for Parameter sweep #948
+
+# Qucs-S 24.3.1
+
+## Packaging
+
+* Stable release packages are now generated autmatically using Github CI #871
+
+## QucsatorRF
+
+* QucsatorRF updated to v1.0.2; See the release notes
+
+## Bugfixes and general improvements
+
+* Improved temperature sweep using unified devices #925
+* Fixed library manger always substitute absoute path #923
+* Fixed stars/circles/arrows plots rendering #892
+* Fixed library devices symbol text rendering #873
+* Fixed touchstones files export from GUI #910
+* Fixed mathicng circuit tool issues #905
+* Implemented SPICE entry for DC block and DC feed #889
+* Fixed Octave start #883
+* Fixed right scroll issue #884
+* Fixed wires selection issue #875
+* Fixed decimal separators processing in attenuator tool #864
+* Fixed shortcut conflict #930
+* Schematic version check checks only major version #931
+
+## Libraries
+
+* Update Optocoupler.lib #846
+
+## Localization
+
+* Updated Russian translation #885
+
+
 # Qucs-S 24.3.0
 
 ## New features

README.md

@@ -31,23 +31,30 @@ Use CMake to build Qucs-S. Install all necessary dependencies: GCC, Qt, Flex, Bi
 
 ### Dependencies
 
-#### Ubuntu
+Qucs-S requires Qt6 libraries including QtCharts, CMake, flex, bison, gperf, and dos2unix as compile time
+dependencies. Install these packages using the package manager of your distribution before compiling Qucs-S.
+Ngspice is not required at compile time, but it is required as runtime dependency to run the simulation.
+
+Here are some examples for the popular Linux distributions.
+
+#### Ubuntu or Debian
 
 ~~~
-sudo apt-get install ngspice build-essential git cmake qtbase5-dev qttools5-dev libqt5svg5-dev flex bison gperf dos2unix
+sudo apt-get install ngspice build-essential git cmake flex bison gperf dos2unix
+sudo apt-get install qt6-base-dev qt6-tools-dev qt6-tools-dev-tools libglx-dev linguist-qt6 
+sudo apt-get install qt6-l10n-tools libqt6svg6-dev libgl1-mesa-dev qt6-charts-dev libqt6opengl6-dev
 ~~~
 
-#### OpenSUSE Tumbleweed
+#### Fedora
 
 ~~~
-sudo zypper install ngspice git cmake libqt5-qtbase-devel libqt5-qttools-devel libqt5-qtsvg-devel flex bison gperf dos2unix
+sudo dnf install gcc-c++ cmake git flex bison gperf dos2unix ngspice
+sudo dnf install qt6-qtbase-devel cmake qt6-qtsvg-devel qt6-qttools-devel qt6-qtcharts-devel 
 ~~~
 
 ### Compiling
 
-#### Qt5
-
-Then clone this git repository and execute in the top directory:
+After installing the dependecies, clone this git repository and execute in the top directory:
 
 ~~~
 git submodule init
@@ -59,19 +66,16 @@ make
 make install
 ~~~
 
-Where `/your_install_prefix/` is desired installation directory. Substitute any
-desire path (for example `$HOME/qucs-s`) here. You may omit this option and
-installation steps. Default installation directory will be `/usr/local` if
+Since the v25.1.0 the Qucs-S will be configured with Qt6 by default. Substutute the  `/your_install_prefix/` 
+as desired installation directory. Substitute any desire path (for example `$HOME/qucs-s`) here. 
+You may omit this option and installation steps. Default installation directory will be `/usr/local` if
 `CMAKE_INSTALL_PREFIX` is not defined.
 
-#### Qt6
+### Qt5/Qt6 support
 
-Since v1.0.1 Qucs-S supports build with Qt6. Set the `WITH_QT6` flag to tell CMake use the Qt6. 
-For example use the following command sequence for Ubuntu-22.04
+Qt5 support has been dropped since v25.1.0. Only Qt6 libraries are supported. Set the `WITH_QT6=ON` 
+cmake flag if compiling the Qucs-S versions before v25.1.0
 
-~~~
-cmake .. -DWITH_QT6=ON -DCMAKE_INSTALL_PREFIX=/your_install_prefix/
-~~~ 
 
 ### Running
 

VERSION

@@ -1 +1 @@
-24.3.0
+25.1.1

contrib/InnoSetup/misc/docsite.url

@@ -0,0 +1,2 @@
+[InternetShortcut]
+URL=https://qucs-s-help.readthedocs.io/

contrib/InnoSetup/misc/gpl.rtf

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+\hich\af1\dbch\af13\loch\f1 GNU GENERAL PUBLIC LICENSE
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+\hich\af1\dbch\af13\loch\f1 Version 2, June 1991 
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+Copyright (C) 1989, 1991 Free Software Foundati\hich\af1\dbch\af13\loch\f1 on, Inc. 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA Everyone is permitted to copy and distribute verbatim \hich\af1\dbch\af13\loch\f1 
+copies of this license document, but changing it is not allowed\hich\af1\dbch\af13\loch\f1 .\hich\af1\dbch\af13\loch\f1  
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+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
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+oundation software is covered by the GNU Library General Public License instead.) \hich\af1\dbch\af13\loch\f1 You can apply it to your programs, too. 
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+\par }\pard\plain \ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0 \fs24\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
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+\par }\pard\plain \s15\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\outlinelevel1\rin0\lin0\itap0\pararsid6645146 \b\fs20\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {
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+\loch\af3\dbch\af13\hich\f3 \'b7}{\f3\fs20\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \tab }{\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 
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+ parties under the terms of this License. 
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+\hich\af1\dbch\af13\loch\f1 c) If the modified progra\hich\af1\dbch\af13\loch\f1 
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+But when you distribute the same sections as part of a whole which is a work based on the Program, the \hich\af1\dbch\af13\loch\f1 
+distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. 
+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 Thus, it is not the intent of this section to claim rights or con\hich\af1\dbch\af13\loch\f1 
+test your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. 
+\par \hich\af1\dbch\af13\loch\f1 In addition, mere aggregation of another work not based on the Program with t\hich\af1\dbch\af13\loch\f1 
+he Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. 
+\par \hich\af1\dbch\af13\loch\f1 3. You may copy and distribute the Program (or a work based on it, under Section 2) in object c\hich\af1\dbch\af13\loch\f1 
+ode or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: 
+\par }\pard\plain \ql \fi-360\li720\ri0\sb100\sa100\nowidctlpar\tx720\faauto\rin0\lin720\itap0 \fs24\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\f3\fs20\lang1031\langfe2052\langnp1031\insrsid6645146 
+\loch\af3\dbch\af13\hich\f3 \'b7}{\f3\fs20\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \tab }{\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 
+a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, 
+\par }\pard \ql \fi-360\li720\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin720\itap0 {\f3\fs20\lang1031\langfe2052\langnp1031\insrsid6645146 \loch\af3\dbch\af13\hich\f3 \'b7}{\f3\fs20\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \tab }{
+\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 b) Accompany it with a written offer, valid for \hich\af1\dbch\af13\loch\f1 
+at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above
+\hich\af1\dbch\af13\loch\f1  \hich\af1\dbch\af13\loch\f1 on a medium customarily \hich\af1\dbch\af13\loch\f1 used for software interchange; or, 
+\par }{\f3\fs20\lang1031\langfe2052\langnp1031\insrsid6645146 \loch\af3\dbch\af13\hich\f3 \'b7}{\f3\fs20\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \tab }{\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 c) Accompany it with the information you received as to the offer to distribute corresponding source code. \hich\af1\dbch\af13\loch\f1 (This alternative is allowed only for noncommercial distribution and only if you receiv
+\hich\af1\dbch\af13\loch\f1 ed the program in object code or executable form with such an offer, in accord with Subsection b above.) 
+\par }\pard \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 {\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 The source code for a work means the preferred form of the work for making modifications to it. 
+\hich\af1\dbch\af13\loch\f1 For an executable work, complete source code means all\hich\af1\dbch\af13\loch\f1 
+ the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. \hich\af1\dbch\af13\loch\f1 
+However, as a special exception, the source code distributed need not include any\hich\af1\dbch\af13\loch\f1 
+thing that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. 
+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 If distribution of \hich\af1\dbch\af13\loch\f1 
+executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to cop
+\hich\af1\dbch\af13\loch\f1 y\hich\af1\dbch\af13\loch\f1  the source along with the object code. 
+\par \hich\af1\dbch\af13\loch\f1 4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. \hich\af1\dbch\af13\loch\f1 
+Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will autom\hich\af1\dbch\af13\loch\f1 atically terminate your rights under this License. \hich\af1\dbch\af13\loch\f1 
+However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. 
+\par \hich\af1\dbch\af13\loch\f1 5. You are not required to acce\hich\af1\dbch\af13\loch\f1 pt this License, since you have not signed it. \hich\af1\dbch\af13\loch\f1 
+However, nothing else grants you permission to modify or distribute the Program or its derivative works. \hich\af1\dbch\af13\loch\f1 These actions are prohibited by law if you do not accept this License. \hich\af1\dbch\af13\loch\f1 
+Therefore, by modifying or distri\hich\af1\dbch\af13\loch\f1 
+buting the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. 
+\par \hich\af1\dbch\af13\loch\f1 6. Each time you redistribute the Progr\hich\af1\dbch\af13\loch\f1 
+am (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. \hich\af1\dbch\af13\loch\f1 
+You may not impose any further restrictions on the recipients'\hich\af1\dbch\af13\loch\f1  exercise of the rights granted herein. \hich\af1\dbch\af13\loch\f1 You are not responsible for enforcing compliance by third parties to this License. 
+\par \hich\af1\dbch\af13\loch\f1 7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issu\hich\af1\dbch\af13\loch\f1 
+es), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. \hich\af1\dbch\af13\loch\f1 
+If you cannot distribute so as to satisfy simultaneously your ob\hich\af1\dbch\af13\loch\f1 ligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. \hich\af1\dbch\af13\loch\f1 
+For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies \hich\af1\dbch\af13\loch\f1 
+directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. 
+\par \hich\af1\dbch\af13\loch\f1 If any portion of this section is held invalid or unenforceable under any particular circumstan\hich\af1\dbch\af13\loch\f1 
+ce, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. 
+\par \hich\af1\dbch\af13\loch\f1 It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity o\hich\af1\dbch\af13\loch\f1 
+f any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. \hich\af1\dbch\af13\loch\f1 
+Many people have made generous contributions to the wide range of software distribu\hich\af1\dbch\af13\loch\f1 
+ted through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. 
+\par \hich\af1\dbch\af13\loch\f1 This section is intended\hich\af1\dbch\af13\loch\f1  to make thoroughly clear what is believed to be a consequence of the rest of this License. 
+\par \hich\af1\dbch\af13\loch\f1 8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder w\hich\af1\dbch\af13\loch\f1 
+ho places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. \hich\af1\dbch\af13\loch\f1 
+In such case, this License incorporates the limitat\hich\af1\dbch\af13\loch\f1 ion as if written in the body of this License. 
+\par \hich\af1\dbch\af13\loch\f1 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. \hich\af1\dbch\af13\loch\f1 
+Such new versions will be similar in spirit to the present version, but may differ in d\hich\af1\dbch\af13\loch\f1 etail to address new problems or concerns. 
+\par \hich\af1\dbch\af13\loch\f1 Each version is given a distinguishing version number. \hich\af1\dbch\af13\loch\f1 
+If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditi\hich\af1\dbch\af13\loch\f1 ons either of that version or of any later version 
+\hich\af1\dbch\af13\loch\f1 published by the Free Software Foundation. \hich\af1\dbch\af13\loch\f1 If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 
+\par \hich\af1\dbch\af13\loch\f1 10. If you wish to i\hich\af1\dbch\af13\loch\f1 ncorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. \hich\af1\dbch\af13\loch\f1 
+For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we so\hich\af1\dbch\af13\loch\f1 metimes make exceptions for this. \hich\af1\dbch\af13\loch\f1 
+Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. 
+\par \hich\af1\dbch\af13\loch\f1 NO WARRANTY 
+\par \hich\af1\dbch\af13\loch\f1 11. BECAUSE THE PROGRAM IS LICE\hich\af1\dbch\af13\loch\f1 NSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. \hich\af1\dbch\af13\loch\f1 
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRES\hich\af1\dbch\af13\loch\f1 
+SED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. \hich\af1\dbch\af13\loch\f1 THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. 
+\hich\af1\dbch\af13\loch\f1 SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE \hich\af1\dbch\af13\loch\f1 COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 
+\par \hich\af1\dbch\af13\loch\f1 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO 
+\hich\af1\dbch\af13\loch\f1 
+YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PA
+\hich\af1\dbch\af13\loch\f1 R\hich\af1\dbch\af13\loch\f1 TIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+\par }\pard\plain \s15\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\outlinelevel1\rin0\lin0\itap0\pararsid6645146 \b\fs20\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang1031\langfe2052\langnp1031\insrsid6645146 
+\hich\af1\dbch\af13\loch\f1 END OF TERMS AND C\hich\af1\dbch\af13\loch\f1 ONDIT\hich\af1\dbch\af13\loch\f1 IONS }{\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\par }\pard\plain \s18\ql \li0\ri0\nowidctlpar\faauto\outlinelevel1\rin0\lin0\itap0\pararsid6645146 \b\fs20\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 How to Apply These Terms t\hich\af1\dbch\af13\loch\f1 o Your New Programs}{\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 If you develop a new p\hich\af1\dbch\af13\loch\f1 
+rogram, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. 
+\par \hich\af1\dbch\af13\loch\f1 To do so, attach the following notices to the program. \hich\af1\dbch\af13\loch\f1 It is s\hich\af1\dbch\af13\loch\f1 
+afest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. 
+\par }\pard\plain \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 \fs24\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 
+one line to give the program's name and an\hich\af1\dbch\af13\loch\f1  idea of what it does. \hich\af1\dbch\af13\loch\f1 
+Copyright (C) yyyy name of author This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License
+\hich\af1\dbch\af13\loch\f1 , or (at your option) any later version. \hich\af1\dbch\af13\loch\f1 
+This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \hich\af1\dbch\af13\loch\f1 See the GNU General Public License 
+\hich\af1\dbch\af13\loch\f1 for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 
+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 Also add information on how to contact you by electronic and paper mail. 
+\par \hich\af1\dbch\af13\loch\f1 If the program is interactive, make it output a short notice like this when it starts in an interactive mode: 
+\par }\pard\plain \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 \fs24\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 
+Gnomovision version 69, Copyright (C) year name of author Gnomovision c\hich\af1\dbch\af13\loch\f1 omes with ABSOLUTELY NO WARRANTY; for details type `show w'. \hich\af1\dbch\af13\loch\f1 
+This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. 
+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 The hypothetical commands `show w' and `show c' should show the appropriate par\hich\af1\dbch\af13\loch\f1 ts of the General Public License. \hich\af1\dbch\af13\loch\f1 
+Of course, the commands you use may be called something other than `show w' and `show c' ; they could even be mouse-clicks or menu items--whatever suits your program. 
+\par \hich\af1\dbch\af13\loch\f1 You should also get your employer (if you work as a pr\hich\af1\dbch\af13\loch\f1 ogrammer) or your school, if any, to sign a "copyright disclaimer" for the program, if necess\hich\af1\dbch\af13\loch\f1 ary. 
+\hich\af1\dbch\af13\loch\f1 Here is a sample; alter the nam\hich\af1\dbch\af13\loch\f1 es: 
+\par }\pard\plain \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 \fs24\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\cs17\fs16\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 \hich\af1\dbch\af13\loch\f1 
+Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) wri\hich\af1\dbch\af13\loch\f1 tten by James Hacker. signature of Ty Coon , 1 April 1989 Ty Coon, President of Vice 
+\par }\pard\plain \s16\ql \li0\ri0\sb100\sa100\nowidctlpar\faauto\rin0\lin0\itap0\pararsid6645146 \fs16\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\hich\af1\dbch\af13\loch\f1 This General Public License does not permit incorporating your program into proprietary programs. \hich\af1\dbch\af13\loch\f1 If your program is a subroutine library, you may consider it more useful\hich\af1\dbch\af13\loch\f1 
+ to permit linking proprietary applications with the library. \hich\af1\dbch\af13\loch\f1 If this is what you want to do, use the GNU Lesser General Public License instead of this License.
+\par }\pard\plain \ql \li0\ri0\nowidctlpar\faauto\rin0\lin0\itap0 \fs24\lang1033\langfe2052\loch\af1\hich\af1\dbch\af13\cgrid\langnp1033\langfenp2052 {\fs20\lang2057\langfe2052\langnp2057\insrsid6645146\charrsid6645146 
+\par }}

contrib/InnoSetup/misc/mingw.url

@@ -0,0 +1,2 @@
+[InternetShortcut]
+URL=http://mingw-w64.sourceforge.net/

contrib/InnoSetup/misc/website.url

@@ -0,0 +1,2 @@
+[InternetShortcut]
+URL=https://ra3xdh.github.io/

contrib/InnoSetup/qucs.iss

@@ -0,0 +1,82 @@
+; Qucs-S Inno Setup script file
+; Refactored for improved readability and maintainability
+;
+; Copyright (C) 2005-2011 Stefan Jahn <stefan@lkcc.org>
+; Copyright (C) 2014-2016 Guilherme Brondani Torri <guitorri@gmail.com>
+;
+; This is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2, or (at your option)
+; any later version.
+;
+; This software is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this package; see the file COPYING.  If not, write to
+; the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
+; Boston, MA 02110-1301, USA.
+
+#ifndef RELEASE
+  #define RELEASE "24.3.0"
+#endif
+
+#ifndef APPNAME
+  #define APPNAME "Qucs-S"
+#endif
+
+#define URL "https://ra3xdh.github.io/"
+#define TREE "..\..\build\qucs-suite\"
+
+[Setup]
+AppName={#APPNAME}
+AppVersion={#RELEASE}
+AppPublisher=The Qucs-S Team
+AppPublisherURL={#URL}
+AppSupportURL={#URL}
+AppUpdatesURL={#URL}
+DefaultDirName={pf}\Qucs-S
+DefaultGroupName=Qucs-S
+AllowNoIcons=yes
+LicenseFile={#TREE}\misc\gpl.rtf
+OutputBaseFilename={#APPNAME}-{#RELEASE}-setup
+Compression=lzma2/max
+SolidCompression=yes
+ChangesEnvironment=yes
+UsePreviousAppDir=yes
+WizardStyle=modern
+SetupIconFile={#TREE}\misc\qucs.ico
+Uninstallable=yes
+ArchitecturesInstallIn64BitMode=x64compatible
+
+[Tasks]
+Name: "desktopicon"; Description: "{cm:CreateDesktopIcon}"; GroupDescription: "{cm:AdditionalIcons}"; Flags: unchecked
+
+[Files]
+Source: "{#TREE}\bin\*"; DestDir: "{app}\bin"; Flags: ignoreversion recursesubdirs createallsubdirs
+Source: "{#TREE}\misc\*"; DestDir: "{app}\misc"; Flags: ignoreversion recursesubdirs createallsubdirs
+Source: "{#TREE}\lib\*"; DestDir: "{app}\lib"; Flags: ignoreversion recursesubdirs createallsubdirs
+Source: "{#TREE}\share\*"; DestDir: "{app}\share"; Flags: ignoreversion recursesubdirs createallsubdirs
+
+[Icons]
+Name: "{group}\Qucs-S Simulator"; Filename: "{app}\bin\qucs-s.exe"; IconFilename: "{app}\misc\qucs.ico"; WorkingDir: "{app}\bin"
+Name: "{group}\Visit the Qucs Web Site"; Filename: "{app}\misc\website.url"
+Name: "{group}\Technical Online Documentation"; Filename: "{app}\misc\docsite.url"
+Name: "{group}\{cm:UninstallProgram,Qucs}"; Filename: "{uninstallexe}"
+Name: "{userdesktop}\Qucs-S"; Filename: "{app}\bin\qucs-s.exe"; IconFilename: "{app}\misc\qucs.ico"; WorkingDir: "{app}\bin"; Tasks: desktopicon
+
+[Code]
+procedure CurStepChanged(CurStep: TSetupStep);
+var
+  ResultCode: Integer;
+  Uninstall: String;
+begin
+  if (CurStep = ssInstall) then begin
+    if RegQueryStringValue(HKLM, 'SOFTWARE\Microsoft\Windows\CurrentVersion\Uninstall\{#APPNAME}_is1', 'UninstallString', Uninstall) then begin
+      MsgBox('An existing version of {#APPNAME} was detected. It will now be removed before installing the new version.', mbInformation, MB_OK);
+      Exec(RemoveQuotes(Uninstall), ' /SILENT', '', SW_SHOWNORMAL, ewWaitUntilTerminated, ResultCode);
+    end;
+  end;
+end;

contrib/gentoo/README.md

@@ -0,0 +1,25 @@
+qucs_s
+===============
+
+Gentoo overlay with ebuild for Qucs-S package
+
+To use, follow https://wiki.gentoo.org/wiki/Creating_an_ebuild_repository
+and copy content of this folder to new repository
+
+===============
+TODO list:
+
+to Science project (sci-electronics)
+
+docs examples test USE flags ?
+lib as separate package ? with meta like kicad-meta ?
+qucsatorrf - separate ebuild ?
+
+qucs - qucsator ebuild
+gnucsator - gnucap based - ebuild
+
+openvaf - ebuild ?
+
+xyce ebuild ?
+spiceopus ebuild ?
+

contrib/gentoo/metadata/layout.conf

@@ -0,0 +1 @@
+masters = gentoo

contrib/gentoo/profiles/repo_name

@@ -0,0 +1 @@
+qucs_s

contrib/gentoo/sci-electronics/qucs_s/Manifest

@@ -0,0 +1,6 @@
+DIST qucs-s-24.4.1.tar.gz 4659723 BLAKE2B aeb2b3613f8ea2aeaeabfe3aa18fc0aca70bd7acecd862aac81cbc53e5c5ef671db7c76ebcaaf9ec4e15a2d1bf2fbc373f18d96e67fd228e683a412b87102f5d SHA512 ef96395c9932e4f90f718d1515a1f8550650005c5ba263580d911ae827bf22c63c7b8d6bac0f46f35bb4946ee17f587f424c60d0bf0fb53602383b8d375a3e19
+DIST qucs-s-25.1.0.tar.gz 4690986 BLAKE2B 285d475bd61e1fb807d8d25edb9b437fb8aa43c590257ce02bec61ac0cd09c3c62b116262372113bf1d319f68837a17bbcb2b5c528a0d561f5ffb5c7b10ab08c SHA512 3ce980491685974dae9cea5d2758d6b227dde0e427152001520f1b46bcd0a4841c27ddd1256a9f3a1bb2742f039271bf0f45d1ab8986864f2168af17f414a815
+EBUILD qucs_s-24.4.1.ebuild 1341 BLAKE2B 60c34a9e9448d1c62c42809621ab238398b8cd3a986999d36082ff286a1d1cc6add75e83b85d2d75dc2294c8804d1c734bec474bb5f11fe8c3086f30cd9dd8e3 SHA512 43cf52a729500785db06aa645089e01fc8f8cdde2794139740e9312da8e5b76cdb17551485c7294f0b94e5bb443c61778b15b96878289360eeb9d4ec831b5a9f
+EBUILD qucs_s-25.1.0.ebuild 1325 BLAKE2B 9469756e62eeb2a97736d19648223d6ad73dd638f4352bf61564a5afcd34be9e96b311c56c57b687ec7619a6298ac2123307297dc7db36239b7e2b31f3c92c4d SHA512 e0c0bbee39f6085c2f6f7a6451ae821c5bd2b06befb3407085124ff8196fbe05375720ddab882f8c923abde4f696414b98e147c91f87adfbdb23af80c4896907
+EBUILD qucs_s-9999.ebuild 1325 BLAKE2B 9469756e62eeb2a97736d19648223d6ad73dd638f4352bf61564a5afcd34be9e96b311c56c57b687ec7619a6298ac2123307297dc7db36239b7e2b31f3c92c4d SHA512 e0c0bbee39f6085c2f6f7a6451ae821c5bd2b06befb3407085124ff8196fbe05375720ddab882f8c923abde4f696414b98e147c91f87adfbdb23af80c4896907
+MISC metadata.xml 5020 BLAKE2B e4a4aea13d1b47cfc598fb9849c5e8adeb6f0b420bc006fed43ff8ff8294de0aabadfb2c8490b5cb9c9ee4b3bf8733f27f25e0a8249c09965f3d3b3573ae9205 SHA512 bb4c2d6f2e7b65a65e491883d48239ea0567a0dcd88c23e86af8ce635be6216ceeb9401c51cd8acc2bbcdbf8937821925242b9fe34cd92157282a12733084ae0

contrib/gentoo/sci-electronics/qucs_s/metadata.xml

@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
+<pkgmetadata>
+	<maintainer type="person">
+		<name>Vadim Kuznetsov</name>
+		<email>ra3xdh@gmail.com</email>
+	</maintainer>
+	<maintainer type="project">
+		<name>Proxy Maintainers</name>
+		<email>proxy-maint@gentoo.org</email>
+	</maintainer>
+	<longdescription lang="en">
+	Qucs-S is a circuit simulation program based on Qucs circuit simulator. The "S" letter indicates SPICE.
+	The purpose of the Qucs-S project is to use free circuit simulation kernels (Ngspice, Qucsator, Xyce)
+	with the unified GUI based on Qt6 toolkit. It merges the power of SPICE and the simplicity of the Qucs GUI.
+	Qucs-S is not a simulator by itself, but it requires to use an external simulation backend with it.
+	Qucs-S allows to use the following open-source simulation kernels:
+
+	<pkg>sci-electronics/ngspice</pkg> is recommended to use.
+	Ngspice is powerful mixed-level/mixed-signal circuit simulator.	The most of industrial SPICE models
+	are compatible with Ngspice. It has an excellent simulation performance and powerful postprocessor.
+	Google Skywater 130nm PDK supports Ngspice.
+	
+	XYCE is a new SPICE-compatible circuit simulator written by Sandia from the scratch. It supports
+	basic SPICE simulation types and has an advanced RF simulation features such as Harmonic balance simulation.
+    
+	QucsatorRF for RF and microwave circuits design. It provides advanced models for such devices microstrip
+	lines and waveguides. QucsatorRF is not SPICE compatible. The general purpose circuits simulation is
+	also possible but not recommended.
+	
+	SpiceOpus is developed by the Faculty of Electrical Engineering of the Ljubljana University. It based on
+	the SPICE-3f5 code
+	</longdescription>
+	<longdescription lang="ru">
+	Qucs-S - это кроссплатформенная программа с открытым исходным кодом для аналогового моделирования
+	электронных схем с графическим интерфейсом, написанная на С++ на базе библиотек Qt6.
+	
+	Qucs-S основан как форк проекта Qucs, а буква "S" обозначает SPICE - стандарт де-факто в аналоговом
+	моделировании. Он объединяет мощь разных SPICE-симуляторов с универсальным и простым в использовании
+	интерфейсом Qucs.
+	
+	Qucs-S не моделирует схему сам по себе, а использует внешний симулятор:
+
+	<pkg>sci-electronics/ngspice</pkg> - рекомендуется как наиболее распространённый симулятор
+	с открытым исходным кодом. Большая часть доступных SPICE-моделей компонентов совместима с Ngspice.
+	У него отличная скорость работы, а также мощный и гибкий постпроцессор обработки результатов.
+	Как один из примеров, Google Skywater 130nm PDK, библиотека компонентов для разработки микросхем
+	от Google, включает модели для Ngspice.
+
+	QucsatorRF - предназначен для радиочастотного моделирования. Несовместим с SPICE-моделями, зато имеет
+	продвинутые модели для микрополосковых линий и волноводов. Также способен моделировать обычные схемы,
+	но это не рекомендуется.
+	Не требует отдельной установки, поскольку входит в комплект Qucs-S.
+	
+	XYCE - новый SPICE-симулятор, написаный с руля, от Sandia National Laboratories. Поддерживает
+	как стандартные типы моделей SPICE, так и продвинутые функции для радиочастотного моделирования,
+	к примеру метод гармонического баланса.
+    	
+	SpiceOpus - бесплатный симулятор с закрытым исходным кодом от инженерного факультета университета Любляны.
+	Основан на оигинальном коде SPICE-3f5 с различными улучшениями и расширениями.
+	</longdescription>
+	<upstream>
+		<maintainer status="active">
+			<name>Vadim Kuznetsov</name>
+			<email>ra3xdh@gmail.com</email>
+		</maintainer>
+		<changelog>https://github.com/ra3xdh/qucs_s/releases</changelog>
+		<doc lang="en">https://ra3xdh.github.io/pdf/qucs_s_tutorial.pdf</doc>
+		<bugs-to>mailto:ra3xdh@gmail.com</bugs-to>
+		<remote-id type="github">ra3xdh/qucs_s</remote-id>
+	</upstream>
+</pkgmetadata>

contrib/gentoo/sci-electronics/qucs_s/qucs_s-24.4.1.ebuild

@@ -0,0 +1,65 @@
+# Copyright 1999-2025 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=8
+
+inherit cmake-multilib optfeature xdg
+
+DESCRIPTION="Quite universal circuit simulator with SPICE"
+HOMEPAGE="https://github.com/ra3xdh/qucs_s"
+
+MY_PN="qucs-s"
+MY_P=${MY_PN}-${PV}
+
+if [[ ${PV} == 9999 ]]; then
+	EGIT_REPO_URI="https://github.com/ra3xdh/${PN}.git"
+	inherit git-r3
+else
+	SRC_URI="https://github.com/ra3xdh/${PN}/releases/download/${PV}/${MY_P}.tar.gz"
+	KEYWORDS="~amd64 ~x86"
+fi
+
+LICENSE="GPL-2"
+SLOT="0"
+
+DEPEND="
+	dev-qt/qtbase:6[gui,widgets]
+	dev-qt/qtsvg:6
+"
+RDEPEND="${DEPEND}"
+BDEPEND="
+	dev-qt/qttools:6[linguist]
+	sys-devel/flex
+	sys-devel/bison
+	dev-util/gperf
+	app-text/dos2unix
+"
+
+S="${WORKDIR}/${MY_P}"
+
+DOCS="${S}/AUTHORS ${S}/ChangeLog ${S}/debian/changelog ${S}/CONTRIBUTING.md ${S}/NEWS.md ${S}/NEWS_qucs ${S}/README.md ${S}/README_qucs ${S}/THANKS ${S}/TODO"
+
+multilib_src_configure() {
+        local mycmakeargs=(
+		-DWITH_QT6=ON
+		-DCMAKE_INSTALL_PREFIX=/usr                
+        )
+        cmake_src_configure
+}
+
+pkg_preinst() {
+	xdg_pkg_preinst
+}
+
+pkg_postinst() {
+	optfeature "Result postprocessing in Octave" sci-mathematics/octave
+
+	optfeature_header "Install optonal simulator backends:"
+	optfeature "Ngspice" sci-electronics/ngspice
+
+	xdg_pkg_postinst
+}
+
+pkg_postrm() {
+	xdg_pkg_postrm
+}

contrib/gentoo/sci-electronics/qucs_s/qucs_s-25.1.0.ebuild

@@ -0,0 +1,64 @@
+# Copyright 1999-2025 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=8
+
+inherit cmake-multilib optfeature xdg
+
+DESCRIPTION="Quite universal circuit simulator with SPICE"
+HOMEPAGE="https://github.com/ra3xdh/qucs_s"
+
+MY_PN="qucs-s"
+MY_P=${MY_PN}-${PV}
+
+if [[ ${PV} == 9999 ]]; then
+	EGIT_REPO_URI="https://github.com/ra3xdh/${PN}.git"
+	inherit git-r3
+else
+	SRC_URI="https://github.com/ra3xdh/${PN}/releases/download/${PV}/${MY_P}.tar.gz"
+	KEYWORDS="~amd64 ~x86"
+fi
+
+LICENSE="GPL-2"
+SLOT="0"
+
+DEPEND="
+	dev-qt/qtbase:6[gui,widgets]
+	dev-qt/qtsvg:6
+"
+RDEPEND="${DEPEND}"
+BDEPEND="
+	dev-qt/qttools:6[linguist]
+	sys-devel/flex
+	sys-devel/bison
+	dev-util/gperf
+	app-text/dos2unix
+"
+
+S="${WORKDIR}/${MY_P}"
+
+DOCS="${S}/AUTHORS ${S}/ChangeLog ${S}/debian/changelog ${S}/CONTRIBUTING.md ${S}/NEWS.md ${S}/NEWS_qucs ${S}/README.md ${S}/README_qucs ${S}/THANKS ${S}/TODO"
+
+multilib_src_configure() {
+        local mycmakeargs=(
+		-DCMAKE_INSTALL_PREFIX=/usr                
+        )
+        cmake_src_configure
+}
+
+pkg_preinst() {
+	xdg_pkg_preinst
+}
+
+pkg_postinst() {
+	optfeature "Result postprocessing in Octave" sci-mathematics/octave
+
+	optfeature_header "Install optonal simulator backends:"
+	optfeature "Ngspice" sci-electronics/ngspice
+
+	xdg_pkg_postinst
+}
+
+pkg_postrm() {
+	xdg_pkg_postrm
+}

contrib/gentoo/sci-electronics/qucs_s/qucs_s-9999.ebuild

@@ -0,0 +1,64 @@
+# Copyright 1999-2025 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=8
+
+inherit cmake-multilib optfeature xdg
+
+DESCRIPTION="Quite universal circuit simulator with SPICE"
+HOMEPAGE="https://github.com/ra3xdh/qucs_s"
+
+MY_PN="qucs-s"
+MY_P=${MY_PN}-${PV}
+
+if [[ ${PV} == 9999 ]]; then
+	EGIT_REPO_URI="https://github.com/ra3xdh/${PN}.git"
+	inherit git-r3
+else
+	SRC_URI="https://github.com/ra3xdh/${PN}/releases/download/${PV}/${MY_P}.tar.gz"
+	KEYWORDS="~amd64 ~x86"
+fi
+
+LICENSE="GPL-2"
+SLOT="0"
+
+DEPEND="
+	dev-qt/qtbase:6[gui,widgets]
+	dev-qt/qtsvg:6
+"
+RDEPEND="${DEPEND}"
+BDEPEND="
+	dev-qt/qttools:6[linguist]
+	sys-devel/flex
+	sys-devel/bison
+	dev-util/gperf
+	app-text/dos2unix
+"
+
+S="${WORKDIR}/${MY_P}"
+
+DOCS="${S}/AUTHORS ${S}/ChangeLog ${S}/debian/changelog ${S}/CONTRIBUTING.md ${S}/NEWS.md ${S}/NEWS_qucs ${S}/README.md ${S}/README_qucs ${S}/THANKS ${S}/TODO"
+
+multilib_src_configure() {
+        local mycmakeargs=(
+		-DCMAKE_INSTALL_PREFIX=/usr                
+        )
+        cmake_src_configure
+}
+
+pkg_preinst() {
+	xdg_pkg_preinst
+}
+
+pkg_postinst() {
+	optfeature "Result postprocessing in Octave" sci-mathematics/octave
+
+	optfeature_header "Install optonal simulator backends:"
+	optfeature "Ngspice" sci-electronics/ngspice
+
+	xdg_pkg_postinst
+}
+
+pkg_postrm() {
+	xdg_pkg_postrm
+}

contrib/io.github.ra3xdh.qucs_s.metainfo.xml

@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<component type="desktop-application">
+  <id>io.github.ra3xdh.qucs_s</id>
+
+  <metadata_license>CC0-1.0</metadata_license>
+  <project_license>GPL-2.0-or-later</project_license>
+
+  <name>Qucs-S</name>
+  <summary>Quite universal circuit simulator with SPICE</summary>
+
+  <developer id="io.github.ra3xdh">
+    <name>Vadim Kuznetsov</name>
+  </developer>
+
+  <description>
+    <p>
+      Qucs-S provides a fancy graphical user interface for a number of popular circuit simulation engines. Qucs-S contains instruments for schematic capture, visualization and provides differents passive and active components including device library.
+    </p>
+  </description>
+
+  <launchable type="desktop-id">qucs-s.desktop</launchable>
+
+  <content_rating type="oars-1.1" />
+
+  <url type="bugtracker">https://github.com/ra3xdh/qucs_s/issues</url>
+  <url type="homepage">https://ra3xdh.github.io</url>
+  <url type="donation">https://boosty.to/qucs_s</url>
+  <url type="vcs-browser">https://github.com/ra3xdh/qucs_s</url>
+
+  <screenshots>
+    <screenshot type="default">
+      <image>https://ra3xdh.github.io/ne5532.png</image>
+      <caption>NE5532 amplifier using SPICE model</caption>
+    </screenshot>
+  </screenshots>
+
+  <releases>
+    <release version="25.1.1" date="2025-03-14">
+      <url type="details">https://github.com/ra3xdh/qucs_s/releases/tag/25.1.1</url>
+    </release>
+    <release version="25.1.0" date="2025-02-20">
+      <url type="details">https://github.com/ra3xdh/qucs_s/releases/tag/25.1.0</url>
+    </release>
+    <release version="24.4.1" date="2024-11-14">
+      <url type="details">https://github.com/ra3xdh/qucs_s/releases/tag/24.4.1</url>
+    </release>
+    <release version="24.4.0" date="2024-10-31">
+      <url type="details">https://github.com/ra3xdh/qucs_s/releases/tag/24.4.0</url>
+    </release>
+  </releases>
+</component>

contrib/translate_with_deepl.py

@@ -0,0 +1,48 @@
+import os
+import xml.etree.ElementTree as ET
+import deepl  # Import DeepL API
+
+# Set up DeepL API key
+token = 'your_deepL_api_key'  # Replace with your DeepL API key
+translator = deepl.Translator(token)
+
+# select target lang
+def translate_text(text, source_lang="EN", target_lang="XX"):
+    """
+    Translates text using DeepL API.
+    """
+    try:
+        # Call DeepL API for translation
+        result = translator.translate_text(text, source_lang=source_lang, target_lang=target_lang)
+        return result.text
+    except Exception as e:
+        print(f"Error translating text: {e}")
+        return text  # Return the original text in case of an error
+
+def process_ts_file(input_file, output_file):
+    """
+    Processes a .ts XML file to translate `unfinished` entries.
+    """
+    tree = ET.parse(input_file)
+    root = tree.getroot()
+
+    for context in root.findall("context"):
+        for message in context.findall("message"):
+            source = message.find("source")
+            translation = message.find("translation")
+            if translation is not None and translation.get("type") == "unfinished":
+                if source is not None:
+                    source_text = source.text
+                    # Translate the source text
+                    translated_text = translate_text(source_text)
+                    print(f"Translating: {source_text} -> {translated_text}")
+                    translation.text = translated_text
+                    translation.attrib.pop("type", None)  # Remove 'unfinished' attribute
+
+    # Save the updated file
+    tree.write(output_file, encoding="utf-8", xml_declaration=True)
+
+# Example usage
+input_ts_file = "qucs_xx.ts"  # Replace with your input file path
+output_ts_file = "qucs_xx_translated.ts"  # Replace with your desired output file path
+process_ts_file(input_ts_file, output_ts_file)

examples/ngspice/BJT_TEMPER_swp.sch

@@ -0,0 +1,51 @@
+<Qucs Schematic 24.3.99>
+<Properties>
+  <View=-226,-121,1120,618,1.04201,0,0>
+  <Grid=10,10,1>
+  <DataSet=BJT_TEMPER_swp.dat>
+  <DataDisplay=BJT_TEMPER_swp.dpl>
+  <OpenDisplay=0>
+  <Script=BJT_TEMPER_swp.m>
+  <RunScript=0>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
+<Symbol>
+</Symbol>
+<Components>
+  <R R2 1 160 150 15 -26 0 1 "1k" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <IProbe Pr1 1 240 100 -14 -56 1 2>
+  <.DC DC1 1 70 380 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
+  <R R1 1 90 150 -74 -20 0 1 "300k" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <.SW SW1 1 250 380 0 64 0 0 "DC1" 1 "lin" 1 "TEMP" 1 "-40" 1 "85" 1 "200" 1>
+  <GND * 1 160 270 0 0 0 0>
+  <Vdc V1 1 300 140 18 -26 0 1 "12 V" 1>
+  <GND * 1 300 180 0 0 0 0>
+  <_BJT Q2N2222A_1 1 160 230 15 -30 0 0 "npn" 0 "8.11e-14" 0 "1" 0 "1" 0 "0.5" 0 "0.225" 0 "113" 0 "24" 0 "1.06e-11" 0 "2" 0 "0" 0 "2" 0 "205" 1 "4" 0 "0" 0 "0" 0 "0.137" 0 "0.343" 0 "1.37" 0 "2.95e-11" 0 "0.75" 0 "0.33" 0 "1.52e-11" 0 "0.75" 0 "0.33" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "3.97e-10" 0 "0" 0 "0" 0 "0" 0 "8.5e-08" 0 "TEMPER" 1 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.5" 0 "3" 0 "1.11" 0 "26.85" 1 "1" 0 "no" 1>
+</Components>
+<Wires>
+  <160 100 160 120 "" 0 0 0 "">
+  <160 180 160 200 "" 0 0 0 "">
+  <90 100 160 100 "" 0 0 0 "">
+  <90 100 90 120 "" 0 0 0 "">
+  <90 230 130 230 "" 0 0 0 "">
+  <90 180 90 230 "" 0 0 0 "">
+  <160 100 210 100 "" 0 0 0 "">
+  <160 260 160 270 "" 0 0 0 "">
+  <270 100 300 100 "" 0 0 0 "">
+  <300 100 300 110 "" 0 0 0 "">
+  <300 170 300 180 "" 0 0 0 "">
+  <160 200 160 200 "Vce" 180 170 0 "">
+</Wires>
+<Diagrams>
+  <Rect 430 387 387 297 3 #c0c0c0 1 00 1 -40 20 84.3719 0 0 2 10 0 0 0.002 0.01 315 0 225 1 0 0 "" "" "">
+	<"ngspice/sw1.v(vce)" #0000ff 0 3 0 0 0>
+	<"ngspice/sw1.i(pr1)" #ff0000 0 3 0 0 1>
+  </Rect>
+</Diagrams>
+<Paintings>
+  <Text 40 -80 12 #082dff 0 "ra3xdh:\nThe TEMPER represents a global temperature in Ngspice. \nBut the DC sweep requires TEMP as the parameter to sweep. \nThese variable names are a bit ambiguous. \nHere is an example of the temperature sweep.\n\n">
+</Paintings>

examples/ngspice/BJT_T_swp.sch

@@ -0,0 +1,52 @@
+<Qucs Schematic 24.3.99>
+<Properties>
+  <View=-257,-171,1108,578,1.02807,0,0>
+  <Grid=10,10,1>
+  <DataSet=BJT_T_swp.dat>
+  <DataDisplay=BJT_T_swp.dpl>
+  <OpenDisplay=0>
+  <Script=BJT_T_swp.m>
+  <RunScript=0>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
+<Symbol>
+</Symbol>
+<Components>
+  <R R2 1 170 130 16 -21 0 1 "1k" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <IProbe Pr1 1 240 80 -12 -57 1 2>
+  <R R1 1 100 130 -76 -20 0 1 "300k" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <Vdc V1 1 310 120 18 -26 0 1 "12 V" 1>
+  <GND * 1 310 160 0 0 0 0>
+  <GND * 1 170 250 0 0 0 0>
+  <.DC DC1 1 70 340 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
+  <.SW SW1 1 240 340 0 64 0 0 "DC1" 1 "lin" 1 "TEMP" 1 "-40" 1 "85" 1 "200" 1>
+  <_BJT X2N2222A_1 1 170 210 15 -20 0 0 "npn" 0 "14.34f" 0 "1" 0 "1" 0 "0.2847" 0 "0" 0 "74.03" 0 "0" 0 "14.34f" 0 "1.307" 0 "0" 0 "2" 0 "255.9" 1 "6.092" 0 "0" 0 "0" 0 "1" 0 "0" 0 "10" 0 "22.01p" 0 "0.75" 0 "0.377" 0 "7.306p" 0 "0.75" 0 "0.3416" 0 "1" 0 "0" 0 "0.75" 0 "0" 0 "0.5" 0 "411.1p" 0 "3" 0 "0" 0 "0.6V" 0 "46.91n" 0 "26.85" 1 "0" 0 "1" 0 "1" 0 "0" 0 "1" 0 "1" 0 "0" 0 "1.5" 0 "3" 0 "1.11" 0 "26.85" 1 "1" 0 "yes" 1>
+</Components>
+<Wires>
+  <170 80 170 100 "" 0 0 0 "">
+  <170 80 210 80 "" 0 0 0 "">
+  <100 80 170 80 "" 0 0 0 "">
+  <100 80 100 100 "" 0 0 0 "">
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+  <310 80 310 90 "" 0 0 0 "">
+  <310 150 310 160 "" 0 0 0 "">
+  <170 240 170 250 "" 0 0 0 "">
+  <170 160 170 180 "" 0 0 0 "">
+  <100 160 100 210 "" 0 0 0 "">
+  <100 210 140 210 "" 0 0 0 "">
+  <170 180 170 180 "Vce" 190 150 0 "">
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+<Diagrams>
+  <Rect 440 357 387 297 3 #c0c0c0 1 00 1 -40 20 84.3719 0 0 2 10 0 0 0.002 0.01 315 0 225 1 0 0 "" "" "">
+	<"ngspice/sw1.v(vce)" #0000ff 0 3 0 0 0>
+	<"ngspice/sw1.i(pr1)" #ff0000 0 3 0 0 1>
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+</Diagrams>
+<Paintings>
+  <Text 50 -100 12 #082dff 0 "ra3xdh:\nI have added the property UseGlobTemp=yes/no \nThe default is yes. If set to yes it uses global temperature. \nOtherwise the device uses temperature defined in Temp. \nThe temperature sweep will be possible for device using default parameters.">
+  <Text 50 -130 12 #000000 0 "https://github.com/ra3xdh/qucs_s/pull/925">
+</Paintings>

examples/qucsator/BJT_T_swp_qucs.sch

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+<Qucs Schematic 24.3.99>
+<Properties>
+  <View=-167,-51,979,578,1.22452,0,0>
+  <Grid=10,10,1>
+  <DataSet=BJT_T_swp_qucs.dat>
+  <DataDisplay=BJT_T_swp_qucs.dpl>
+  <OpenDisplay=0>
+  <Script=BJT_T_swp_qucs.m>
+  <RunScript=0>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
+<Symbol>
+</Symbol>
+<Components>
+  <.DC DC1 1 40 340 0 38 0 0 "26.85" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "no" 0 "150" 0 "no" 0 "none" 0 "CroutLU" 0>
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+  <R R2 1 140 140 15 -26 0 1 "1k" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
+  <IProbe Pr1 1 220 90 -12 -58 1 2>
+  <GND * 1 140 260 0 0 0 0>
+  <Vdc V1 1 280 140 18 -26 0 1 "12 V" 1>
+  <GND * 1 280 180 0 0 0 0>
+  <R R1 1 70 140 -77 -21 0 1 "300k" 1 "26.85" 0 "0.0" 0 "0.0" 0 "26.85" 0 "european" 0>
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+</Components>
+<Wires>
+  <140 90 140 110 "" 0 0 0 "">
+  <140 90 190 90 "" 0 0 0 "">
+  <140 170 140 190 "" 0 0 0 "">
+  <140 250 140 260 "" 0 0 0 "">
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+  <280 90 280 110 "" 0 0 0 "">
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+  <70 90 140 90 "" 0 0 0 "">
+  <70 90 70 110 "" 0 0 0 "">
+  <70 220 110 220 "" 0 0 0 "">
+  <70 170 70 220 "" 0 0 0 "">
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+<Diagrams>
+  <Rect 430 377 387 297 3 #c0c0c0 1 00 1 -40 20 85 0 0 2 10 0 0 0.002 0.01 315 0 225 1 0 0 "" "" "">
+	<"Vce.V" #0000ff 0 3 0 0 0>
+	<"Pr1.I" #ff0000 0 3 0 0 1>
+  </Rect>
+</Diagrams>
+<Paintings>
+  <Text 20 -10 12 #082dff 0 "Temp Sweep Qucsator">
+</Paintings>

examples/templates_ngspice/PwrAmpTHD.sch

@@ -0,0 +1,194 @@
+<Qucs Schematic 24.4.1>
+<Properties>
+  <View=2,-136,1511,748,1.0431,0,0>
+  <Grid=10,10,1>
+  <DataSet=PwrAmpTHD.dat>
+  <DataDisplay=PwrAmpTHD.dpl>
+  <OpenDisplay=0>
+  <Script=PwrAmpTHD.m>
+  <RunScript=0>
+  <showFrame=0>
+  <FrameText0=Title>
+  <FrameText1=Drawn By:>
+  <FrameText2=Date:>
+  <FrameText3=Revision:>
+</Properties>
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+</Symbol>
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+  <SpicePar SpicePar1 1 1250 -40 -27 18 0 0 "vin=600m" 1>
+  <.CUSTOMSIM CUSTOM1 1 1230 30 0 40 0 0 "\ncompose vin start=100m stop=1 step=100m\nlet n=length(vin)\nlet thd=vector(n)\nlet out_rms=vector(n)\n\nset nfreqs=20\n\nlet i=0\nrepeat $&n\n  let vin_i=vin[i]\n  alterparam vin=$&vin_i\n  reset\n\n  tran 10u 10m\n  fourier 1k v(out)\n  meas tran orms_i rms out\n  let out_rms[i]=orms_i\n\n  let j=2\n  let sum_i=0\n  let f=i+1\n  while j < $nfreqs\n    let sum_i=sum_i+fourier{$&f}1[1][j]^2\n    let j=j+1\n  end\n  let thd_i=100*sqrt(sum_i)/fourier{$&f}1[1][1]\n  let thd[i]=thd_i\n\n  destroy $curplot\n  let i=i+1\nend\n\nsetscale out_rms\n\ndestroy all\nreset" 0 "thd;vin" 0 "" 0>
+  <S4Q_V V1 1 100 230 19 5 1 3 "sin(0 {vin} 1k)" 1 "" 0 "" 0 "" 0 "" 0>
+</Components>
+<Wires>
+  <370 440 550 440 "" 0 0 0 "">
+  <370 200 550 200 "" 0 0 0 "">
+  <580 170 580 200 "" 0 0 0 "">
+  <370 260 470 260 "" 0 0 0 "">
+  <370 380 460 380 "" 0 0 0 "">
+  <580 440 580 470 "" 0 0 0 "">
+  <580 470 620 470 "" 0 0 0 "">
+  <580 170 620 170 "" 0 0 0 "">
+  <370 500 370 630 "" 0 0 0 "">
+  <250 690 310 690 "" 0 0 0 "">
+  <190 690 250 690 "" 0 0 0 "">
+  <370 690 620 690 "" 0 0 0 "">
+  <370 630 620 630 "" 0 0 0 "">
+  <710 -50 710 -20 "" 0 0 0 "">
+  <710 -50 820 -50 "" 0 0 0 "">
+  <710 40 790 40 "" 0 0 0 "">
+  <710 40 710 70 "" 0 0 0 "">
+  <820 10 940 10 "" 0 0 0 "">
+  <820 -50 1030 -50 "" 0 0 0 "">
+  <1030 -50 1030 -20 "" 0 0 0 "">
+  <370 10 370 140 "" 0 0 0 "">
+  <250 -50 310 -50 "" 0 0 0 "">
+  <190 -50 250 -50 "" 0 0 0 "">
+  <370 -50 620 -50 "" 0 0 0 "">
+  <370 10 620 10 "" 0 0 0 "">
+  <620 10 680 10 "" 0 0 0 "">
+  <620 -50 710 -50 "" 0 0 0 "">
+  <470 260 580 260 "" 0 0 0 "">
+  <470 260 470 510 "" 0 0 0 "">
+  <620 470 940 470 "" 0 0 0 "">
+  <1030 660 1030 690 "" 0 0 0 "">
+  <1030 470 1030 600 "" 0 0 0 "">
+  <1030 440 1030 470 "" 0 0 0 "">
+  <620 170 940 170 "" 0 0 0 "">
+  <1030 40 1030 170 "" 0 0 0 "">
+  <1030 170 1030 200 "" 0 0 0 "">
+  <1030 300 1030 320 "" 0 0 0 "">
+  <1030 200 1030 240 "" 0 0 0 "">
+  <1030 400 1030 440 "" 0 0 0 "">
+  <940 300 940 340 "" 0 0 0 "">
+  <940 200 970 200 "" 0 0 0 "">
+  <940 200 940 240 "" 0 0 0 "">
+  <940 170 970 170 "" 0 0 0 "">
+  <940 170 940 200 "" 0 0 0 "">
+  <940 440 970 440 "" 0 0 0 "">
+  <940 400 940 440 "" 0 0 0 "">
+  <940 470 970 470 "" 0 0 0 "">
+  <940 440 940 470 "" 0 0 0 "">
+  <460 380 580 380 "" 0 0 0 "">
+  <1030 320 1030 340 "" 0 0 0 "">
+  <1030 320 1110 320 "" 0 0 0 "">
+  <1030 690 1140 690 "" 0 0 0 "">
+  <1030 -50 1140 -50 "" 0 0 0 "">
+  <160 320 250 320 "" 0 0 0 "">
+  <250 260 310 260 "" 0 0 0 "">
+  <310 170 310 200 "" 0 0 0 "">
+  <310 170 340 170 "" 0 0 0 "">
+  <250 380 310 380 "" 0 0 0 "">
+  <310 440 310 470 "" 0 0 0 "">
+  <310 470 340 470 "" 0 0 0 "">
+  <620 690 710 690 "" 0 0 0 "">
+  <820 630 940 630 "" 0 0 0 "">
+  <820 690 1030 690 "" 0 0 0 "">
+  <620 630 680 630 "" 0 0 0 "">
+  <710 660 710 690 "" 0 0 0 "">
+  <710 600 790 600 "" 0 0 0 "">
+  <710 690 820 690 "" 0 0 0 "">
+  <710 570 710 600 "" 0 0 0 "">
+  <460 130 460 380 "" 0 0 0 "">
+  <310 130 460 130 "" 0 0 0 "">
+  <310 -50 310 130 "" 0 0 0 "">
+  <550 130 550 140 "" 0 0 0 "">
+  <460 130 550 130 "" 0 0 0 "">
+  <310 510 310 690 "" 0 0 0 "">
+  <310 510 470 510 "" 0 0 0 "">
+  <550 500 550 510 "" 0 0 0 "">
+  <470 510 550 510 "" 0 0 0 "">
+  <1110 260 1110 320 "" 0 0 0 "">
+  <100 260 100 320 "" 0 0 0 "">
+  <1110 320 1110 320 "out" 1070 290 0 "">
+  <100 320 100 320 "in" 70 300 0 "">
+</Wires>
+<Diagrams>
+  <Rect 1230 270 240 160 3 #c0c0c0 1 00 1 1.08481 2 10.7141 1 -0.0601316 0.5 0.68536 1 -1 1 1 315 0 225 1 0 0 "" "" "">
+	<"ngspice/thd" #0000ff 2 3 0 0 0>
+  </Rect>
+  <Tab 1230 525 154 205 3 #c0c0c0 1 00 1 0 1 1 1 0 1 1 1 0 1 1 315 0 225 1 0 0 "" "" "">
+	<"ngspice/thd" #0000ff 0 3 1 0 0>
+	<"ngspice/vin" #0000ff 0 3 1 0 0>
+  </Tab>
+</Diagrams>
+<Paintings>
+  <Text 540 -90 20 #000000 0 "Musical Fidelity A1">
+</Paintings>

examples/xyce/XyceDigital/testCombLogic1.sch

@@ -1,6 +1,6 @@
-<Qucs Schematic 0.0.24>
+<Qucs Schematic 24.3.99>
 <Properties>
-  <View=-336,-305,1160,1375,1,0,0>
+  <View=-1174,-325,1966,1397,0.754031,360,104>
   <Grid=10,10,1>
   <DataSet=testCombLogic1.dat>
   <DataDisplay=testCombLogic1.dpl>
@@ -16,31 +16,22 @@
 <Symbol>
 </Symbol>
 <Components>
-  <GND * 1 790 290 0 0 0 0>
-  <R_SPICE R1 1 790 260 15 -26 0 1 "47k" 1 "" 0 "" 0 "" 0 "" 0>
-  <SpiceModel SpiceModel1 1 -130 -160 -29 17 0 0 ".model DMOD DIG ( RLOAD=1000 CLOAD=1e-12 DELAY=20e-9 CLO=1e-12 CHI=1e-12" 1 "+  S0RLO=5 S0RHI=5 S0TSW=5e-9 S0VLO=-1 S0VHI=0.16 S1RLO=200 S1RHI=5 S1TSW=5e-9 " 1 "+  S1VLO=0.52 S1VHI=1 )" 1 "" 0 "Line_5=" 0>
-  <.TR TR1 1 700 -70 0 84 0 0 "lin" 1 "0" 1 "1 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
-  <SpLib X7 1 0 180 -170 -15 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "LOGIC1" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X9 1 100 140 -310 -113 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX4" 1 "auto" 1 "PulseFreq=1000 ScaleFactor=5" 1>
-  <SpLib X10 1 100 270 -313 142 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX4" 1 "auto" 1 "PulseFreq=5000 ScaleFactor=5" 1>
-  <SpLib X8 1 0 310 -171 -15 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "LOGIC1" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X5 1 260 200 -159 -176 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X6 1 260 330 -108 32 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X1 1 440 180 -141 -157 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "AND4" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X2 1 440 310 -63 65 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "AND4" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X3 1 590 260 -85 -235 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "OR2" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X4 1 730 290 -131 -12 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1>
+  <.TR TR1 1 700 -70 0 64 0 0 "lin" 1 "0" 1 "1 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
+  <SpLib X9 1 100 140 -310 -113 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX4" 1 "auto" 1 "PulseFreq=1000 ScaleFactor=5" 1 "" 0>
+  <SpLib X10 1 100 270 -313 142 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX4" 1 "auto" 1 "PulseFreq=5000 ScaleFactor=5" 1 "" 0>
+  <SpLib X3 1 590 260 -85 -235 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "OR2" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X7 1 10 200 -170 -15 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "LOGIC1" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X8 1 10 330 -171 -15 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "LOGIC1" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X6 1 250 300 -92 40 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X5 1 250 170 -139 -141 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X2 1 450 300 -63 65 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "AND4" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X1 1 450 170 -111 -150 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "AND4" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X4 1 700 230 -84 24 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <GND * 1 800 320 0 0 0 0>
+  <R_SPICE R1 1 800 280 15 -26 0 1 "47k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
+  <SpiceModel SpiceModel1 1 -160 -120 -29 17 0 0 ".model DMOD DIG ( RLOAD=1000 CLOAD=1e-12 DELAY=20e-9 CLO=1e-12 CHI=1e-12" 1 "+  S0RLO=5 S0RHI=5 S0TSW=5e-9 S0VLO=-1 S0VHI=0.16 S1RLO=200 S1RHI=5 S1TSW=5e-9 " 1 "+  S1VLO=0.52 S1VHI=1 )" 1 "" 0 "Line_5=" 0>
 </Components>
 <Wires>
-  <320 200 380 200 "nD3" 320 180 25 "">
-  <320 180 380 180 "nD2" 320 160 21 "">
-  <320 160 380 160 "nD1" 320 140 20 "">
-  <320 140 380 140 "nD0" 320 120 21 "">
-  <320 330 380 330 "nD7" 330 310 38 "">
-  <320 310 380 310 "nD6" 330 290 35 "">
-  <320 290 380 290 "nD5" 330 270 32 "">
-  <320 270 380 270 "nD4" 330 250 33 "">
-  <630 230 670 230 "" 0 0 0 "">
   <500 240 500 300 "" 0 0 0 "">
   <500 240 550 240 "" 0 0 0 "">
   <500 170 500 220 "" 0 0 0 "">
@@ -53,17 +44,29 @@
   <140 310 200 310 "nA6" 170 290 34 "">
   <140 290 200 290 "nA5" 170 270 33 "">
   <140 270 200 270 "nA4" 170 250 35 "">
-  <790 230 790 230 "nAout" 780 190 0 "">
+  <320 330 400 330 "nD7" 330 310 38 "">
+  <320 310 400 310 "nD6" 330 290 35 "">
+  <320 290 400 290 "nD5" 330 270 32 "">
+  <320 270 400 270 "nD4" 330 250 33 "">
+  <320 200 400 200 "nD3" 320 180 25 "">
+  <320 180 400 180 "nD2" 320 160 21 "">
+  <320 160 400 160 "nD1" 320 140 20 "">
+  <320 140 400 140 "nD0" 320 120 21 "">
+  <630 230 650 230 "" 0 0 0 "">
+  <800 230 800 250 "" 0 0 0 "">
+  <770 230 800 230 "" 0 0 0 "">
+  <800 310 800 320 "" 0 0 0 "">
   <630 230 630 230 "nDout" 630 190 0 "">
-  <500 300 500 300 "nDI2" 510 310 0 "">
-  <500 170 500 170 "nDI1" 490 120 0 "">
-  <200 200 200 200 "nA3" 160 180 0 "">
-  <200 180 200 180 "nA2" 160 160 0 "">
-  <200 160 200 160 "nA1" 160 140 0 "">
   <200 140 200 140 "nA0" 160 120 0 "">
+  <200 160 200 160 "nA1" 160 140 0 "">
+  <200 180 200 180 "nA2" 160 160 0 "">
+  <200 200 200 200 "nA3" 160 180 0 "">
+  <500 300 500 300 "nDI2" 510 310 0 "">
+  <500 170 500 170 "nDI1" 510 130 0 "">
+  <800 230 800 230 "nAout" 790 190 0 "">
 </Wires>
 <Diagrams>
-  <Time -190 839 1248 350 3 #c0c0c0 1 00 1 1678 1 15 1 0 1 1 1 0 1 2006 315 0 225 "" "" "">
+  <Time -190 839 1248 350 3 #c0c0c0 1 00 1 1678 1 15 1 0 1 1 1 0 1 2006 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NA0)" #0000ff 0 3 0 0 0>
 	<"xyce/tran.V(NA1)" #ff0000 0 3 0 0 0>
 	<"xyce/tran.V(NA2)" #ff00ff 0 3 0 0 0>
@@ -77,10 +80,10 @@
 	<"xyce/tran.V(NDOUT)" #ff00ff 0 3 0 0 0>
 	<"xyce/tran.V(NAOUT)" #00ff00 0 3 0 0 0>
   </Time>
-  <Rect -200 982 1248 82 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect -200 982 1248 82 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NDOUT)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect -200 1146 1249 86 3 #c0c0c0 1 00 1 0 0.0002 0.001 1 -0.522068 2 5.23788 1 -1 1 1 315 0 225 "" "" "">
+  <Rect -200 1146 1249 86 3 #c0c0c0 1 00 1 0 0.0002 0.001 1 -0.522068 2 5.23788 1 -1 1 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NAOUT)" #0000ff 2 3 0 0 0>
   </Rect>
 </Diagrams>

examples/xyce/XyceDigital/testCombLogic2.sch

@@ -1,6 +1,6 @@
-<Qucs Schematic 0.0.24>
+<Qucs Schematic 24.3.99>
 <Properties>
-  <View=15,45,1520,1455,1,0,0>
+  <View=-564,25,2087,1477,1.1909,992,71>
   <Grid=10,10,1>
   <DataSet=testCombLogic2.dat>
   <DataDisplay=testCombLogic2.dpl>
@@ -16,40 +16,49 @@
 <Symbol>
 </Symbol>
 <Components>
-  <GND * 1 1190 410 0 0 0 0>
-  <R_SPICE R1 1 1190 380 15 -26 0 1 "47k" 1 "" 0 "" 0 "" 0 "" 0>
-  <.TR TR1 1 1230 470 0 77 0 0 "lin" 1 "0" 1 "55us" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
-  <SpLib X33 1 580 310 -380 -58 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX2" 1 "auto" 1 "PulseFreq=25k ScaleFactor=5" 1>
-  <SpLib X32 1 580 350 -377 -1 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX8" 1 "auto" 1 "PulseFreq=250k ScaleFactor=5" 1>
-  <SpLib X31 1 820 270 -367 -61 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "LOGIC0" 1 "auto" 1 "" 1>
-  <SpLib X30 1 850 320 -225 -138 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX2" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X29 1 850 360 -362 96 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X27 1 990 330 -272 133 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "MUX4TO1" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X28 1 1130 410 -198 52 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1>
+  <.TR TR1 1 1230 470 0 64 0 0 "lin" 1 "0" 1 "55us" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
+  <SpLib X33 1 580 310 -380 -58 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX2" 1 "auto" 1 "PulseFreq=25k ScaleFactor=5" 1 "" 0>
+  <SpLib X32 1 580 350 -377 -1 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX8" 1 "auto" 1 "PulseFreq=250k ScaleFactor=5" 1 "" 0>
   <SpiceModel SpiceModel1 1 130 540 -29 17 0 0 ".model DMOD DIG ( RLOAD=1000 CLOAD=1e-12 DELAY=20e-9 CLO=1e-12 CHI=1e-12" 1 "+  S0RLO=5 S0RHI=5 S0TSW=5e-9 S0VLO=-1 S0VHI=0.16 S1RLO=200 S1RHI=5 S1TSW=5e-9 " 1 "+  S1VLO=0.52 S1VHI=1 )" 1 "" 0 "Line_5=" 0>
+  <SpLib X27 1 1010 350 -78 110 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "MUX4TO1" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X31 1 830 270 -6 -107 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "LOGIC0" 1 "auto" 1 "" 1 "" 0>
+  <SpLib X30 1 840 320 -207 -115 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX2" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X29 1 840 380 -205 52 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <GND * 1 1260 430 0 0 0 0>
+  <R_SPICE R1 1 1260 390 15 -26 0 1 "47k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
+  <SpLib X28 1 1140 350 -67 -168 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
 </Components>
 <Wires>
-  <860 290 910 290 "" 0 0 0 "">
-  <620 410 790 410 "" 0 0 0 "">
-  <620 390 790 390 "" 0 0 0 "">
-  <620 370 790 370 "" 0 0 0 "">
-  <620 350 790 350 "" 0 0 0 "">
+  <930 270 930 290 "" 0 0 0 "">
+  <860 270 930 270 "" 0 0 0 "">
+  <910 330 930 330 "" 0 0 0 "">
   <620 330 790 330 "nAG1" 640 310 28 "">
+  <910 310 930 310 "" 0 0 0 "">
   <620 310 790 310 "nAG0" 640 290 28 "">
-  <1190 350 1190 350 "nAZ" 1190 300 0 "">
-  <1070 350 1070 350 "nDZ" 1080 290 0 "">
+  <910 410 930 410 "" 0 0 0 "">
+  <620 410 790 410 "" 0 0 0 "">
+  <910 390 930 390 "" 0 0 0 "">
+  <620 390 790 390 "" 0 0 0 "">
+  <910 370 930 370 "" 0 0 0 "">
+  <620 370 790 370 "" 0 0 0 "">
+  <910 350 930 350 "" 0 0 0 "">
+  <620 350 790 350 "" 0 0 0 "">
+  <1260 420 1260 430 "" 0 0 0 "">
+  <1260 350 1260 360 "" 0 0 0 "">
+  <1210 350 1260 350 "nAZ" 1260 310 36 "">
+  <1070 350 1090 350 "nDZ" 1090 310 12 "">
 </Wires>
 <Diagrams>
-  <Rect 130 740 1262 61 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.5 5 5.5 1 -1 2 1 315 0 225 "" "V(nAG0)" "">
+  <Rect 130 740 1262 61 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.5 5 5.5 1 -1 2 1 315 0 225 1 0 0 "" "V(nAG0)" "">
 	<"xyce/tran.V(NAG0)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 130 845 1267 49 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.5 5 5.5 1 -1 2 1 315 0 225 "" "V(nAG1)" "">
+  <Rect 130 845 1267 49 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.5 5 5.5 1 -1 2 1 315 0 225 1 0 0 "" "V(nAG1)" "">
 	<"xyce/tran.V(NAG1)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 130 1280 1270 161 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.495288 2 6 1 -1 1 1 315 0 225 "" "V(nAZ)" "">
+  <Rect 130 1280 1270 161 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.495288 2 6 1 -1 1 1 315 0 225 1 0 0 "" "V(nAZ)" "">
 	<"xyce/tran.V(NAZ)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 120 1050 1283 149 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.0990787 0.5 1.08911 1 -1 1 1 315 0 225 "" "V(nDZ)" "">
+  <Rect 120 1050 1283 149 3 #c0c0c0 1 00 1 0 0.0001 0.0006 1 -0.0990787 0.5 1.08911 1 -1 1 1 315 0 225 1 0 0 "" "V(nDZ)" "">
 	<"xyce/tran.V(NDZ)" #0000ff 2 3 0 0 0>
   </Rect>
 </Diagrams>

examples/xyce/XyceDigital/testNAND2.sch

@@ -1,6 +1,6 @@
-<Qucs Schematic 0.0.24>
+<Qucs Schematic 24.3.99>
 <Properties>
-  <View=25,-110,1580,1715,1,0,0>
+  <View=-881,-113,2464,1738,0.943747,638,0>
   <Grid=10,10,1>
   <DataSet=testNAND2.dat>
   <DataDisplay=testNAND2.dpl>
@@ -16,28 +16,31 @@
 <Symbol>
 </Symbol>
 <Components>
-  <GND * 1 740 280 0 0 0 0>
-  <SpiceModel SpiceModel1 1 220 290 -29 17 0 0 ".model DMOD DIG ( RLOAD=1000 CLOAD=1e-12 DELAY=20e-9 CLO=1e-12 CHI=1e-12" 1 "+  S0RLO=5 S0RHI=5 S0TSW=5e-9 S0VLO=-1 S0VHI=0.16 S1RLO=200 S1RHI=5 S1TSW=5e-9 " 1 "+  S1VLO=0.52 S1VHI=1 )" 1 "" 0 "Line_5=" 0>
-  <R_SPICE R1 1 740 250 15 -26 0 1 "47k" 1 "" 0 "" 0 "" 0 "" 0>
-  <.TR TR1 1 1230 110 0 79 0 0 "lin" 1 "0" 1 "0.2 ms" 1 "101" 1 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
-  <SpLib X7 1 230 210 -83 -134 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX2" 1 "auto" 1 "PulseFreq=1e4 ScaleFactor=5" 1>
-  <SpLib X6 1 390 220 109 -144 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX2" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X5 1 520 220 164 -137 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "NAND2" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X8 1 680 280 185 -198 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1>
+  <SpLib X7 1 230 210 -177 -141 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX2" 1 "auto" 1 "PulseFreq=1e4 ScaleFactor=5" 1 "" 0>
+  <SpLib X6 1 380 220 -24 -154 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX2" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X8 1 670 220 53 -146 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X5 1 530 220 15 -149 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "NAND2" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <GND * 1 760 300 0 0 0 0>
+  <R_SPICE R1 1 760 260 15 -26 0 1 "47k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 1>
+  <SpiceModel SpiceModel1 1 180 310 -29 17 0 0 ".model DMOD DIG ( RLOAD=1000 CLOAD=1e-12 DELAY=20e-9 CLO=1e-12 CHI=1e-12" 1 "+  S0RLO=5 S0RHI=5 S0TSW=5e-9 S0VLO=-1 S0VHI=0.16 S1RLO=200 S1RHI=5 S1TSW=5e-9 " 1 "+  S1VLO=0.52 S1VHI=1 )" 1 "" 0 "Line_5=" 0>
+  <.TR TR1 1 1000 120 0 64 0 0 "lin" 1 "0" 1 "0.2 ms" 1 "101" 1 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
 </Components>
 <Wires>
-  <580 220 620 220 "" 0 0 0 "">
-  <450 230 480 230 "" 0 0 0 "">
   <270 230 330 230 "nA1" 290 240 21 "">
-  <450 210 480 210 "" 0 0 0 "">
   <270 210 330 210 "nA0" 290 170 22 "">
-  <740 220 740 220 "nAout" 660 270 0 "">
-  <580 220 580 220 "nDout" 560 240 0 "">
-  <480 230 480 230 "nD1" 438 240 0 "">
-  <480 210 480 210 "nD0" 428 170 0 "">
+  <570 220 620 220 "" 0 0 0 "">
+  <450 230 490 230 "" 0 0 0 "">
+  <450 210 490 210 "" 0 0 0 "">
+  <760 220 760 230 "" 0 0 0 "">
+  <740 220 760 220 "" 0 0 0 "">
+  <760 290 760 300 "" 0 0 0 "">
+  <740 220 740 220 "nAout" 770 180 0 "">
+  <490 210 490 210 "nD0" 438 170 0 "">
+  <490 230 490 230 "nD1" 448 240 0 "">
+  <570 220 570 220 "nDout" 580 240 0 "">
 </Wires>
 <Diagrams>
-  <Time 200 658 1191 218 3 #c0c0c0 1 00 1 454 1 14 1 0 1 1 1 0 1 468 315 0 225 "" "" "">
+  <Time 200 658 1191 218 3 #c0c0c0 1 00 1 454 1 14 1 0 1 1 1 0 1 468 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NA0)" #0000ff 0 3 0 0 0>
 	<"xyce/tran.V(NA1)" #ff0000 0 3 0 0 0>
 	<"xyce/tran.V(ND0)" #ff00ff 0 3 0 0 0>
@@ -45,22 +48,22 @@
 	<"xyce/tran.V(NDOUT)" #00ffff 0 3 0 0 0>
 	<"xyce/tran.V(NAOUT)" #ffff00 0 3 0 0 0>
   </Time>
-  <Rect 200 764 1192 51 3 #c0c0c0 1 00 1 0 5e-06 5e-05 1 -2 5 7 1 -1 2 1 315 0 225 "" "" "">
+  <Rect 200 764 1192 51 3 #c0c0c0 1 00 1 0 5e-06 5e-05 1 -2 5 7 1 -1 2 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NA0)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 210 890 1181 63 3 #c0c0c0 1 00 1 0 2e-06 5e-05 1 -5e+07 2e+08 6e+08 1 -1 1 1 315 0 225 "" "" "">
+  <Rect 210 890 1181 63 3 #c0c0c0 1 00 1 0 2e-06 5e-05 1 -5e+07 2e+08 6e+08 1 -1 1 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NA1)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 210 1029 1186 79 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 210 1029 1186 79 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(ND0)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 210 1173 1185 93 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 210 1173 1185 93 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(ND1)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 210 1340 1189 110 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 210 1340 1189 110 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NDOUT)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 210 1511 1189 101 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 210 1511 1189 101 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NAOUT)" #0000ff 2 3 0 0 0>
   </Rect>
 </Diagrams>

examples/xyce/XyceDigital/testPATGENX1.sch

@@ -1,6 +1,6 @@
-<Qucs Schematic 0.0.24>
+<Qucs Schematic 24.3.99>
 <Properties>
-  <View=-40,-110,1866,1040,1,0,0>
+  <View=-541,-130,1632,1061,1.45277,613,243>
   <Grid=10,10,1>
   <DataSet=testPATGENX1.dat>
   <DataDisplay=testPATGENX1.dpl>
@@ -16,29 +16,30 @@
 <Symbol>
 </Symbol>
 <Components>
-  <GND * 1 550 270 0 0 0 0>
-  <R_SPICE R1 1 550 230 15 -26 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0>
-  <.TR TR1 1 750 100 0 77 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
-  <SpLib X4 1 80 200 -97 -148 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX1" 1 "auto" 1 "PulseFreq=1k ScaleFactor=5" 1>
-  <SpLib X5 1 210 260 -58 -30 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGE" 1 "auto" 1 "ScaleFactor=5" 1>
-  <SpLib X6 1 420 260 -34 -207 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1>
+  <SpLib X4 1 80 200 -191 16 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX1" 1 "auto" 1 "PulseFreq=1k ScaleFactor=5" 1 "" 0>
+  <SpLib X5 1 230 200 -59 19 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGE" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <SpLib X6 1 410 200 -20 -116 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "D2ABRIDGE" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <GND * 1 530 290 0 0 0 0>
+  <R_SPICE R1 1 530 250 15 -26 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
+  <.TR TR1 1 690 110 0 64 0 0 "lin" 1 "0" 1 "5 ms" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
 </Components>
 <Wires>
-  <270 200 360 200 "" 0 0 0 "">
-  <480 200 550 200 "" 0 0 0 "">
-  <550 260 550 270 "" 0 0 0 "">
-  <120 200 150 200 "nApulseIN" 110 150 14 "">
-  <550 200 550 200 "nApulseOUT" 580 170 0 "">
-  <270 200 270 200 "nDpulse" 300 150 0 "">
+  <300 200 360 200 "" 0 0 0 "">
+  <110 200 180 200 "nApulseIN" 110 150 24 "">
+  <480 200 530 200 "" 0 0 0 "">
+  <530 200 530 220 "" 0 0 0 "">
+  <530 280 530 290 "" 0 0 0 "">
+  <300 200 300 200 "nDpulse" 310 170 0 "">
+  <530 200 530 200 "nApulseOUT" 540 170 0 "">
 </Wires>
 <Diagrams>
-  <Rect 160 449 766 79 3 #c0c0c0 1 00 1 -1 0.2 1 1 -1 0.5 1 1 -1 0.5 1 315 0 225 "" "" "">
+  <Rect 160 449 766 79 3 #c0c0c0 1 00 1 -1 0.2 1 1 -1 0.5 1 1 -1 0.5 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NAPULSEIN)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 160 619 764 89 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 160 619 764 89 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NDPULSE)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 150 821 768 88 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 150 821 768 88 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NAPULSEOUT)" #0000ff 2 3 0 0 0>
   </Rect>
 </Diagrams>

examples/xyce/XyceDigital/testPATGENX4.sch

@@ -1,6 +1,6 @@
-<Qucs Schematic 0.0.24>
+<Qucs Schematic 24.3.99>
 <Properties>
-  <View=-87,10,1480,1380,1,0,288>
+  <View=-566,-10,2008,1401,1.22626,587,65>
   <Grid=10,10,1>
   <DataSet=testPATGENX4.dat>
   <DataDisplay=testPATGENX4.dpl>
@@ -16,52 +16,56 @@
 <Symbol>
 </Symbol>
 <Components>
-  <.TR TR1 1 1070 230 0 77 0 0 "lin" 1 "0" 1 "0.2m" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
-  <SpLib X1 1 140 160 -112 96 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX8" 1 "auto" 1 "PulseFreq=10000.0 ScaleFactor=5" 1>
-  <SpLib X2 1 340 170 20 88 0 0 "C:/Program Files (x86)/Qucs-S/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1>
+  <.TR TR1 1 1070 230 0 64 0 0 "lin" 1 "0" 1 "0.2m" 1 "101" 0 "Trapezoidal" 0 "2" 0 "1 ns" 0 "1e-16" 0 "150" 0 "0.001" 0 "1 pA" 0 "1 uV" 0 "26.85" 0 "1e-3" 0 "1e-6" 0 "1" 0 "CroutLU" 0 "no" 0 "yes" 0 "0" 0>
+  <SpLib X1 1 140 160 -182 77 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "PATGENX8" 1 "auto" 1 "PulseFreq=10000.0 ScaleFactor=5" 1 "" 0>
   <GND * 1 580 290 0 0 0 0>
   <GND * 1 660 290 0 0 0 0>
   <GND * 1 740 290 0 0 0 0>
   <GND * 1 820 290 0 0 0 0>
-  <R_SPICE R1 1 580 250 15 -26 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0>
-  <R_SPICE R2 1 660 250 15 -26 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0>
-  <R_SPICE R3 1 740 250 15 -26 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0>
-  <R_SPICE R4 1 820 250 15 -26 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0>
+  <SpLib X2 1 330 190 17 58 0 0 "C:/QUCS-S 24.3.0/share/qucs-s/library/XyceDigital.lib" 0 "A2DBRIDGEX4" 1 "auto" 1 "ScaleFactor=5" 1 "" 0>
+  <R_SPICE R1 1 580 250 15 -17 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
+  <R_SPICE R2 1 660 250 15 -17 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
+  <R_SPICE R3 1 740 250 15 -17 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
+  <R_SPICE R4 1 820 250 13 -19 0 1 "4.7k" 1 "" 0 "" 0 "" 0 "" 0 "2" 0 "R" 0>
 </Components>
 <Wires>
+  <580 280 580 290 "" 0 0 0 "">
+  <820 280 820 290 "" 0 0 0 "">
   <180 220 280 220 "" 0 0 0 "">
   <180 200 280 200 "nA2" 230 180 36 "">
   <180 180 280 180 "nA1" 230 160 20 "">
   <180 160 280 160 "" 0 0 0 "">
-  <580 280 580 290 "" 0 0 0 "">
+  <400 160 430 160 "" 0 0 0 "">
+  <400 180 430 180 "" 0 0 0 "">
+  <400 200 430 200 "" 0 0 0 "">
+  <400 220 430 220 "" 0 0 0 "">
   <660 280 660 290 "" 0 0 0 "">
-  <820 280 820 290 "" 0 0 0 "">
   <740 280 740 290 "" 0 0 0 "">
   <180 160 180 160 "nA0" 210 140 0 "">
   <180 220 180 220 "nA3" 210 200 0 "">
-  <400 160 400 160 "nD0" 430 130 0 "">
-  <400 180 400 180 "nD1" 430 150 0 "">
-  <400 200 400 200 "nD2" 430 170 0 "">
-  <400 220 400 220 "nD3" 430 190 0 "">
-  <580 220 580 220 "nD0" 610 190 0 "">
-  <660 220 660 220 "nD1" 690 190 0 "">
-  <820 220 820 220 "nD3" 850 190 0 "">
-  <740 220 740 220 "nD2" 770 190 0 "">
+  <430 160 430 160 "nD0" 460 130 0 "">
+  <430 180 430 180 "nD1" 460 150 0 "">
+  <430 200 430 200 "nD2" 460 170 0 "">
+  <430 220 430 220 "nD3" 460 190 0 "">
+  <580 220 580 220 "nD0" 590 190 0 "">
+  <660 220 660 220 "nD1" 670 190 0 "">
+  <740 220 740 220 "nD2" 750 190 0 "">
+  <820 220 820 220 "nD3" 830 190 0 "">
 </Wires>
 <Diagrams>
-  <Rect 130 579 1109 59 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 130 579 1109 59 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(ND1)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 130 452 1108 60 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 130 452 1108 60 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(ND0)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 130 699 1118 60 3 #c0c0c0 1 00 1 0 5e-05 0.001 0 0 1 1 1 -1 2 1 315 0 225 "" "" "">
+  <Rect 130 699 1118 60 3 #c0c0c0 1 00 1 0 5e-05 0.001 0 0 1 1 1 -1 2 1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(ND2)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Rect 130 818 1124 68 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" "">
+  <Rect 130 818 1124 68 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(ND3)" #0000ff 2 3 0 0 0>
   </Rect>
-  <Time 130 1143 1127 274 3 #c0c0c0 1 00 1 0 1 13 1 0 1 1 1 0 1 950 315 0 225 "" "" "">
+  <Time 130 1143 1127 274 3 #c0c0c0 1 00 1 0 1 13 1 0 1 1 1 0 1 950 315 0 225 1 0 0 "" "" "">
 	<"xyce/tran.V(NA0)" #0000ff 0 3 0 0 0>
 	<"xyce/tran.V(NA1)" #ff0000 0 3 0 0 0>
 	<"xyce/tran.V(NA2)" #ff00ff 0 3 0 0 0>

library/CMakeLists.txt

@@ -1,6 +1,7 @@
 
 SET(COMPLIBS
 555_timer.lib
+Analog.lib
 AudioIC.lib
 Bridges.lib
 BJT_Extended.lib
@@ -9,12 +10,20 @@ Crystal.lib
 Diodes.lib
 DiodesSchottky.lib
 Diodes_Extended.lib
+Digital_AUX.lib
+Digital_CD.lib
+Digital_HC.lib
+Digital_LV.lib
+Digital_XSPICE.lib
+DualGateMOSFET.lib
 GeDiodes.lib
 Ideal.lib
 JFETs.lib
 LEDs.lib
+LaserDiodes.lib
 Loudspeaker.lib
 MixerIC.lib
+Neon.lib
 MOSFETs.lib
 NMOSFETs.lib
 OpAmps.lib
@@ -23,14 +32,17 @@ PhotovoltaicRelay.lib
 PMOSFETs.lib
 PWM_Controller.lib
 Regulators.lib
+RC.lib
 Substrates.lib
 Transistors.lib
 Varistors.lib
 Z-Diodes.lib
 SpiceOpamp.lib
+SPICE_TLine.lib
 Thermistor.lib
 Thyristor.lib
 Transformers.lib
+TubesExtended.lib
 Xanalogue.lib
 XyceDigital.lib
 Xyce_Digital_TTL_Technology.lib
@@ -52,6 +64,9 @@ xyce.blacklist
 
 INSTALL( FILES ${COMPLIBS} ${BLACKLIST} DESTINATION share/${QUCS_NAME}/library )
 INSTALL( DIRECTORY "symbols" DESTINATION share/${QUCS_NAME}/ )
+INSTALL( DIRECTORY "TubesExtended" DESTINATION share/${QUCS_NAME}/library)
+INSTALL( DIRECTORY "Optocoupler" DESTINATION share/${QUCS_NAME}/library )
+INSTALL( DIRECTORY "DualGateMOSFET" DESTINATION share/${QUCS_NAME}/library )
 
 ADD_SUBDIRECTORY( XyceDigital)
 

library/Digital_LV.lib

@@ -0,0 +1,936 @@
+<Qucs Library 24.4.1 "Digital_LV">
+
+<Component 74LV00>
+  <Description>
+2-Input NAND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV00 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV00_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV00.cir.lst">
+  <Spice>
+* The timing parameters for all of these models were taken from the specifications for a 
+* 3.3V power supply and a 50pF capacitive load.
+
+* ----------------------------------------------------------- 74LV00A ------
+*  Quad 2-Input Positive-Nand Gates
+*
+*  TI PDF File
+*  bss    2/18/03
+*
+.SUBCKT 74LV00A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 nand(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV00 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV00 ugate (tplhTY=6.9ns tplhMX=11.4ns tphlTY=6.9ns tphlMX=11.4ns)
+
+.ENDS  74LV00A
+*
+
+.SUBCKT Digital_LV_74LV00  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV00A
+.ENDS
+  </Spice>
+  <Symbol>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <Line -10 20 0 -40 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV02>
+  <Description>
+2-Input NOR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV02 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV02_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV02.cir.lst">
+  <Spice>
+* ---------------------------------- 74LV02A ---------------------
+*  Quad 2-Input Nor Gates
+*
+*  TI PDF File
+*  bss    2/18/03
+*
+.SUBCKT 74LV02A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 nor(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV02 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV02 ugate (tplhTY=7.6ns tplhMX=11.4ns tphlTY=7.6ns tphlMX=11.4ns)
+
+.ENDS  74LV02A
+*
+
+.SUBCKT Digital_LV_74LV02  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV02A
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV04>
+  <Description>
+Inverter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV04 _net0 _net1
+Sub:X1 _net0 _net1 gnd Type="n74LV04_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV04.cir.lst">
+  <Spice>
+* -------------------------- 74LV04A --------------------------------
+*  Hex Inverters
+*
+*  TI PDF File
+*  bss    1/2/03
+*
+.SUBCKT 74LV04A  1A  1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 inv DPWR_3V DGND_3V
++     1A 1Y
++     DLY_LV04 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV04 ugate (tplhTY=7.3ns tplhMX=10.6ns tphlTY=7.3ns tphlMX=10.6ns)
+
+.ENDS  74LV04A
+*
+
+.SUBCKT Digital_LV_74LV04  gnd _net0 _net1 
+X1 _net0 _net1 74LV04A
+.ENDS
+  </Spice>
+  <Symbol>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
+    <Ellipse 10 -4 8 8 #000080 1 1 #000080 1 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <.ID 10 14 Y>
+    <.PortSym 30 0 2 180 P2>
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 1 0 P1>
+  </Symbol>
+</Component>
+
+<Component 74LV08>
+  <Description>
+2-Input AND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV08 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV08_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV08.cir.lst">
+  <Spice>
+* ---------------------------- 74LV08A ------------------------------
+*  Quad 2-Input AND Gate
+*
+*  TI PDF File
+*  bss    2/21/03
+*
+.SUBCKT 74LV08A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 and(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV08 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV08 ugate (tplhTY=7.5ns tplhMX=12.3ns tphlTY=7.5ns tphlMX=12.3ns)
+
+.ENDS  74LV08A
+*
+
+.SUBCKT Digital_LV_74LV08  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV08A
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line -10 20 0 -40 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV20>
+  <Description>
+4-Input NAND Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV20 _net0 _net1 _net2 _net3 _net4
+Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="n74LV20_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV20.cir.lst">
+  <Spice>
+* ----------------------------- 74LV20A -------------------------
+*  Dual 4-Input Nand Gate 
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV20A  1A 1B 1C 1D 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 nand(4) DPWR_3V DGND_3V
++     1A 1B 1C 1D 1Y
++     DLY_LV20 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV20 ugate (tplhTY=6.5ns tplhMX=10.1ns tphlTY=6.5ns tphlMX=10.1ns)
+
+.ENDS  74LV20A
+*
+
+.SUBCKT Digital_LV_74LV20  gnd _net0 _net1 _net2 _net3 _net4 
+X1 _net0 _net1 _net2 _net3 _net4 74LV20A
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <Line -10 40 0 -80 #000080 2 1>
+    <Ellipse 20 -4 8 8 #000080 1 1 #000080 1 1>
+    <EArc -20 -20 40 40 4320 2880 #000080 2 1>
+    <Line 0 20 -10 0 #000080 2 1>
+    <.PortSym -30 -30 1 0 P1>
+    <.PortSym -30 -10 2 0 P2>
+    <.PortSym -30 10 3 0 P3>
+    <.PortSym -30 30 4 0 P4>
+    <.PortSym 40 0 5 180 P5>
+    <.ID 20 14 Y>
+    <Line 28 0 12 0 #000080 2 1>
+    <Line 0 -20 -10 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV32>
+  <Description>
+2-Input OR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV32 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV32_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV32.cir.lst">
+  <Spice>
+* -------------------------- 74LV32A ----------------------------
+*  Quad 2-Input Or Gate
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV32A  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 or(2) DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV32 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV32 ugate (tplhTY=6.9ns tplhMX=11.4ns tphlTY=6.9ns tphlMX=11.4ns)
+
+.ENDS  74LV32A
+*
+
+.SUBCKT Digital_LV_74LV32  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV32A
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <Line -10 20 -5 0 #000080 2 1>
+    <Line -10 -20 -5 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV74>
+  <Description>
+D-Type Positive Edge Triggered Flip-Flop With Preset And Clear
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV74 _net0 _net1 _net2 _net3 _net4 _net5
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 gnd Type="n74LV74_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV74.cir.lst">
+  <Spice>
+* The timing parameters for all of these models were taken from the specifications for a 
+* 3.3V power supply and a 50pF capacitive load.
+*
+* -------------------------------------- 74LV74A ---------------------------
+*  Dual Positive Edge Triggered D-Type Flip-Flop
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV74A 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 DFF(1) DPWR_3V DGND_3V
++     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
++     DLY_LV74 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV74 ueff(tppcqlhty=9.2ns tppcqlhmx=15.8ns tppcqhlty=9.2ns tppcqhlmx=15.8ns
++							tpclkqlhty=10.2ns tpclkqlhmx=15.4ns tpclkqhlty=10.2ns tpclkqhlmx=15.4ns
++							twpclmn=6ns twclklmn=6ns twclkhmn=6ns tsudclkmn=6n tsupcclkhmn=5ns
++							thdclkmn=.5n)
+
+.ENDS 74LV74A
+*
+
+.SUBCKT Digital_LV_74LV74  gnd _net0 _net1 _net2 _net3 _net4 _net5 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 74LV74A
+.ENDS
+  </Spice>
+  <Symbol>
+    <Rectangle -30 -40 60 80 #000080 2 1 #c0c0c0 1 0>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 -20 20 0 #000080 2 1>
+    <Line 30 -20 20 0 #000080 2 1>
+    <Line 0 -40 0 -20 #000080 2 1>
+    <Ellipse -4 40 8 8 #000080 1 1 #000080 1 1>
+    <Line 30 20 20 0 #000080 2 1>
+    <Ellipse -4 -48 8 8 #000080 1 1 #000080 1 1>
+    <Line 14 11 12 0 #000080 2 1>
+    <Text 14 -31 12 #000080 0 "Q">
+    <Text 14 9 12 #000080 0 "Q">
+    <Text -28 -30 12 #000080 0 "D">
+    <Line -15 20 -15 -10 #000080 2 1>
+    <Line -30 30 15 -10 #000080 2 1>
+    <Line 0 61 0 -20 #000080 2 1>
+    <Text -6 -41 12 #000080 0 "C">
+    <Text -3 19 12 #000080 0 "P">
+    <.PortSym 0 60 1 0 P1>
+    <.ID 20 44 Y>
+    <.PortSym 0 -60 2 0 P2>
+    <.PortSym -50 -20 4 0 P4>
+    <.PortSym -50 20 3 0 P3>
+    <.PortSym 50 -20 5 180 P5>
+    <.PortSym 50 20 6 180 P6>
+  </Symbol>
+</Component>
+
+<Component 74LV86>
+  <Description>
+2-Input Exclusive-OR Gate
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV86 _net0 _net1 _net2
+Sub:X1 _net0 _net1 _net2 gnd Type="n74LV86_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV86.cir.lst">
+  <Spice>
+* ----------------------------------------------------------- 74LV86A ------
+*  Quad 2-Input Exclusive-Or Gate
+*
+*  TI PDF File
+*  bss    2/24/03
+*
+.SUBCKT 74LV86  1A 1B 1Y
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 xor DPWR_3V DGND_3V
++     1A 1B 1Y
++     DLY_LV86 IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+.model DLY_LV86 ugate (tplhTY=7.4ns tplhMX=14.5ns tphlTY=7.4ns tphlMX=14.5ns)
+
+.ENDS  74LV86
+*
+
+.SUBCKT Digital_LV_74LV86  gnd _net0 _net1 _net2 
+X1 _net0 _net1 _net2 74LV86
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 P1>
+    <.PortSym -30 10 2 0 P2>
+    <.PortSym 30 0 3 180 P3>
+    <.ID 10 14 Y>
+    <EArc -30 -20 40 40 4320 2880 #000080 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #000080 2 1>
+    <EArc -15 -20 10 40 4320 2880 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component 74LV138>
+  <Description>
+3-Line To 8-Line Decoder/Demultiplexer
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV138 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74LV138_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV138.cir.lst">
+  <Spice>
+*-----------------------------------------------------------74LV138A-----
+* 3-Line To 8-Line Decoder/Demultiplexer
+*
+*  TI PDF File
+*  bss    2/25/03
+
+.SUBCKT 74LV138A A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(6,8) DPWR_3V DGND_3V
++ A B C G1 G2ABAR G2BBAR
++ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
++ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++   ENAB = {G1 & ~G2ABAR & ~G2BBAR}
++   Y0O = {~(~A & ~B & ~C & ENAB)}
++   Y1O = {~(A & ~B & ~C & ENAB)}
++   Y2O = {~(~A & B & ~C & ENAB)}
++   Y3O = {~(A & B & ~C & ENAB)}
++   Y4O = {~(~A & ~B & C & ENAB)}
++   Y5O = {~(A & ~B & C & ENAB)}
++   Y6O = {~(~A & B & C & ENAB)}
++   Y7O = {~(A & B & C & ENAB)}
+
+U2 PINDLY(8,0,6) DPWR_3V DGND_3V
++ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
++ A B C G1 G2ABAR G2BBAR
++ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
++ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
++     ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
++     EN = {CHANGED(G1,0)}
++  PINDLY:
++     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
++       CASE(
++          EN & TRN_LH, DELAY(-1,10.6ns,16.3ns),
++          EN & TRN_HL, DELAY(-1,10.6ns,16.3ns),
++          ENBAR & TRN_LH, DELAY(-1,10ns,14.9ns),
++          ENBAR & TRN_HL, DELAY(-1,10ns,14.9ns),
++          IN & TRN_LH, DELAY(-1,10.3ns,15.8ns),
++          IN & TRN_HL, DELAY(-1,10.3ns,15.8ns),
++          DELAY(-1,11ns,17ns))}
+
+.ENDS 74LV138A
+*
+
+.SUBCKT Digital_LV_74LV138  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74LV138A
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line -50 0 20 0 #000080 2 1>
+    <.PortSym 50 0 7 180 Y0>
+    <.PortSym 50 20 8 180 Y1>
+    <.PortSym 50 40 9 180 Y2>
+    <.PortSym 50 60 10 180 Y3>
+    <.PortSym 50 80 11 180 Y4>
+    <.PortSym 50 100 12 180 Y5>
+    <.PortSym 50 120 13 180 Y6>
+    <.PortSym 50 140 14 180 Y7>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 40 20 0 #000080 2 1>
+    <.PortSym -50 20 2 0 B>
+    <.PortSym -50 0 1 0 A>
+    <.PortSym -50 40 3 0 C>
+    <Line -50 80 20 0 #000080 2 1>
+    <Line -50 100 20 0 #000080 2 1>
+    <Ellipse -31 96 -8 8 #000080 1 1 #000080 1 1>
+    <Line -50 120 20 0 #000080 2 1>
+    <Ellipse -31 116 -8 8 #000080 1 1 #000080 1 1>
+    <.PortSym -50 80 4 0 G1>
+    <.PortSym -50 100 5 0 G2AB>
+    <.PortSym -50 120 6 0 G2BB>
+    <Text -25 -11 12 #000080 0 "A">
+    <Text 6 29 12 #000080 0 "Y2">
+    <Text 6 49 12 #000080 0 "Y3">
+    <Text 6 129 12 #000080 0 "Y7">
+    <Text 6 9 12 #000080 0 "Y1">
+    <Text 6 89 12 #000080 0 "Y5">
+    <Text 6 -11 12 #000080 0 "Y0">
+    <Text 6 69 12 #000080 0 "Y4">
+    <Text 6 109 12 #000080 0 "Y6">
+    <Text -25 9 12 #000080 0 "B">
+    <Text -25 69 12 #000080 0 "G1">
+    <Text -25 89 12 #000080 0 "G2">
+    <Text -25 109 12 #000080 0 "G3">
+    <.ID -10 164 Y>
+    <Text -25 29 12 #000080 0 "C">
+  </Symbol>
+</Component>
+
+<Component 74LV164>
+  <Description>
+8-Bit Parallel-Out Serial Shift Register
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+.PARAM: vcc=5
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV164 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 gnd Type="n74LV164_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV164.cir.lst">
+  <Spice>
+* ----------------------------------------------------------- 74LV164 ------
+*  8-Bit Parallel-Out Serial Shift Register
+*
+*  TI PDF File
+*  bss    2/26/03
+*
+.SUBCKT 74LV164 A B CLRBAR CLK QA QB QC QD QE QF QG QH
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U74164 LOGICEXP (3,3) DPWR_3V DGND_3V
++        CLK A B
++        r0 s0 clkbar
++        D0_GATE IO_LV-A IO_LEVEL={IO_LEVEL}
++
++    LOGIC:
++      r0 = { (~(A & B)) }
++      s0 = { (~r0) }
++      clkbar = { (~CLK) }
+
+uf0  JKff(8)  DPWR_3V DGND_3V
++    $D_HI CLRBAR clkbar
++    s0 QA_O QB_O QC_O QD_O QE_O QF_O QG_O
++    r0 qabar qbbar qcbar qdbar qebar qfbar qgbar
++    QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
++    qabar qbbar qcbar qdbar qebar qfbar qgbar qhbar
++    D0_EFF IO_LV-A
+
+Udly PINDLY (8,0,2) DPWR_3V DGND_3V
++    QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O
++    CLRBAR CLK
++    QA QB QC QD QE QF QG QH
++    IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++
++    BOOLEAN:
++       CLOCK= { CHANGED(CLK,0) }
++       CLEAR= { CHANGED_HL(CLRBAR,0) }
++
++    PINDLY:
++       QA QB QC QD QE QF QG QH  = {
++                   CASE(
++                       CLEAR & TRN_HL, DELAY(-1,7.9ns,16.3ns),
++                       CLOCK, DELAY(-1,8.3ns,16.3ns),
++                       DELAY(-1,9ns,17ns)
++                       )
++                     }
+
+Ucnstr CONSTRAINT(4) DPWR_3V DGND_3V
++          CLRBAR CLK A B
++          IO_LV-A
++
++      FREQ:
++        NODE = CLK
++        MAXFREQ = 120MEG
++      WIDTH:
++        NODE = CLK
++        MIN_HI = 5ns
++			MIN_LO = 5ns
++      WIDTH:
++        NODE = CLRBAR
++        MIN_LO = 5ns
++      SETUP_HOLD:
++        CLOCK LH = CLK
++        DATA(2) = A B
++        SETUPTIME = 5ns
++        WHEN = { CLRBAR != '0 }
++      SETUP_HOLD:
++        DATA(1) = CLRBAR
++        CLOCK LH = CLK
++        SETUPTIME_HI = 2.5ns
+
+.ENDS 74LV164
+*
+
+.SUBCKT Digital_LV_74LV164  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 74LV164
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Line -50 0 20 0 #000080 2 1>
+    <Text -28 -10 12 #000080 0 "A">
+    <Rectangle -30 -20 60 180 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 10 12 #000080 0 "B">
+    <Text -28 50 12 #000080 0 "CLR">
+    <Ellipse -31 56 -8 8 #000080 1 1 #000080 1 1>
+    <Line -50 140 20 0 #000080 2 1>
+    <Line -15 140 -15 -10 #000080 2 1>
+    <Line -30 150 15 -10 #000080 2 1>
+    <.PortSym -50 60 3 0 CLRBAR>
+    <.ID -10 164 Y>
+    <.PortSym -50 0 1 0 A>
+    <.PortSym -50 20 2 0 B>
+    <.PortSym -50 140 4 0 CLK>
+    <.PortSym 50 0 5 180 QA>
+    <.PortSym 50 20 6 180 QB>
+    <.PortSym 50 40 7 180 QC>
+    <.PortSym 50 60 8 180 QD>
+    <.PortSym 50 80 9 180 QE>
+    <.PortSym 50 100 10 180 QF>
+    <.PortSym 50 120 11 180 QG>
+    <.PortSym 50 140 12 180 QH>
+  </Symbol>
+</Component>
+
+<Component 74LV4040>
+  <Description>
+12-Stage Binary Ripple Counter
+XSPICE Based Model
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:Digital_LV_74LV4040 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 gnd Type="n74LV4040_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "74LV4040.cir.lst">
+  <Spice>
+*
+*---------------------74LV4040A-----------------------
+* 12-Bit Asynchronous Binary Counter
+*
+*  TI PDF File
+*  bss    2/28/03
+
+.SUBCKT 74LV4040 CLR CLK QA QB QC QD QE QF QG QH QI QJ QK QL
++     optional: DPWR_3V=$G_DPWR_3V DGND_3V=$G_DGND_3V
++     params: MNTYMXDLY=0 IO_LEVEL=0
+
+U1 LOGICEXP(1,1) DPWR_3V DGND_3V
++ CLR
++ RESETBAR
++ D0_GATE IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ LOGIC:
++        RESETBAR = {~CLR}
+
+U2 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR CLK
++ $D_HI $D_HI Q_A $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U3 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_A
++ $D_HI $D_HI Q_B $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U4 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_B
++ $D_HI $D_HI Q_C $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U5 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_C
++ $D_HI $D_HI Q_D $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U6 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_D
++ $D_HI $D_HI Q_E $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U7 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_E
++ $D_HI $D_HI Q_F $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U8 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_F
++ $D_HI $D_HI Q_G $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U9 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_G
++ $D_HI $D_HI Q_H $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U10 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_H
++ $D_HI $D_HI Q_I $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U11 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_I
++ $D_HI $D_HI Q_J $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U12 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_J
++ $D_HI $D_HI Q_K $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U13 JKFF(1) DPWR_3V DGND_3V
++ $D_HI RESETBAR Q_K
++ $D_HI $D_HI Q_L $D_NC
++ D0_EFF IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+U14 PINDLY(12,0,2) DPWR_3V DGND_3V
++ Q_A Q_B Q_C Q_D Q_E Q_F Q_G Q_H Q_I Q_J Q_K Q_L
++ CLR CLK
++ QA QB QC QD QE QF QG QH QI QJ QK QL
++ IO_LV-A MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
++ BOOLEAN:
++          CLEAR = {CHANGED_LH(CLR,0)}
++          ACLK = {CHANGED_HL(CLK,0)}
++ PINDLY:
++          QA = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,7.5ns,15.4ns),
++              DELAY(-1,10ns,17ns))}
++          QB = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,8.7ns,19.8ns),
++              DELAY(-1,10ns,20ns))}
++          QC = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,9.9ns,24.2ns),
++              DELAY(-1,10ns,25ns))}
++          QD = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,11.1ns,28.6ns),
++              DELAY(-1,12ns,29ns))}
++          QE = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,12.3ns,33ns),
++              DELAY(-1,13ns,34ns))}
++          QF = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,13.5ns,37.4ns),
++              DELAY(-1,14ns,38ns))}
++          QG = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,14.7ns,41.8ns),
++              DELAY(-1,15ns,42ns))}
++          QH = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,15.9ns,46.2ns),
++              DELAY(-1,16ns,47ns))}
++          QI = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,17.1ns,50.6ns),
++              DELAY(-1,18ns,51ns))}
++          QJ = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,18.3ns,55ns),
++              DELAY(-1,19ns,56ns))}
++          QK = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,19.5ns,59.4ns),
++              DELAY(-1,20ns,60ns))}
++          QL = {
++            CASE(
++              CLEAR & TRN_HL, DELAY(-1,9ns,16.3ns),
++              ACLK, DELAY(-1,20.7ns,63.8ns),
++              DELAY(-1,21ns,64ns))}
+
+U15 CONSTRAINT(2) DPWR_3V DGND_3V
++ CLK CLR
++ IO_LV-A IO_LEVEL={IO_LEVEL}
++ SETUP_HOLD:
++             CLOCK HL = CLK
++             DATA(1) = CLR
++             SETUPTIME_LO = 5NS
++ WIDTH:
++             NODE = CLK
++             MIN_HI = 5NS
++             MIN_LO = 5NS
++ WIDTH:
++             NODE = CLR
++             MIN_HI = 5NS
++ FREQ:
++             NODE = CLK
++             MAXFREQ = 130MEG
+
+.ENDS 74LV4040
+*
+
+.SUBCKT Digital_LV_74LV4040  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 _net9 _net10 _net11 _net12 _net13 74LV4040
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 30 20 20 0 #000080 2 1>
+    <Text 4 9 12 #000080 0 "QB">
+    <Text 4 -11 12 #000080 0 "QA">
+    <Text 4 29 12 #000080 0 "QC">
+    <Text 4 49 12 #000080 0 "QD">
+    <Text 4 69 12 #000080 0 "QE">
+    <Rectangle -30 -20 60 260 #000080 2 1 #c0c0c0 1 0>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text 4 89 12 #000080 0 "QF">
+    <Text 4 109 12 #000080 0 "QG">
+    <Text 4 129 12 #000080 0 "QH">
+    <Line 30 60 20 0 #000080 2 1>
+    <Line 30 40 20 0 #000080 2 1>
+    <Line 30 100 20 0 #000080 2 1>
+    <Line 30 80 20 0 #000080 2 1>
+    <Line 30 140 20 0 #000080 2 1>
+    <Line 30 120 20 0 #000080 2 1>
+    <Line 30 160 20 0 #000080 2 1>
+    <Line 30 180 20 0 #000080 2 1>
+    <Line 30 200 20 0 #000080 2 1>
+    <Line 30 220 20 0 #000080 2 1>
+    <.PortSym 50 0 3 180 QA>
+    <.PortSym 50 20 4 180 QB>
+    <.PortSym 50 40 5 180 QC>
+    <.PortSym 50 60 6 180 QD>
+    <.PortSym 50 80 7 180 QE>
+    <.PortSym 50 100 8 180 QF>
+    <.PortSym 50 120 9 180 QG>
+    <.PortSym 50 140 10 180 QH>
+    <.PortSym 50 160 11 180 QI>
+    <.PortSym 50 180 12 180 QJ>
+    <Text 4 149 12 #000080 0 "QI">
+    <Text 4 169 12 #000080 0 "QJ">
+    <Text 4 189 12 #000080 0 "QK">
+    <Text 4 209 12 #000080 0 "QL">
+    <.ID -10 244 Y>
+    <.PortSym 50 200 13 180 QK>
+    <.PortSym 50 220 14 180 QL>
+    <.PortSym -50 0 2 0 CLK>
+    <Line -50 0 20 0 #000080 2 1>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 60 20 0 #000080 2 1>
+    <Text -28 50 12 #000080 0 "CLR">
+    <.PortSym -50 60 1 0 CLR>
+  </Symbol>
+</Component>

library/Digital_XSPICE.lib

@@ -0,0 +1,988 @@
+<Qucs Library 24.4.1 "Digital_XSPICE">
+
+<Component d_AND2>
+  <Description>
+2-Input AND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_AND2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net2 _net1 gnd Type="d_and2_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_and2.cir.lst">
+  <Spice>
+**** XSPICE digital 2-Input AND ****
+*
+.subckt d_and2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B] Y and1
+.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_and2X
+
+.SUBCKT Digital_XSPICE_d_AND2  gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net2 _net1 d_and2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 0 -40 #0000ff 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <.PortSym -30 10 2 0 B>
+    <.PortSym 30 0 3 180 Y>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <.PortSym -30 -10 1 0 A>
+  </Symbol>
+</Component>
+
+<Component d_AND3>
+  <Description>
+3-Input AND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_AND3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_and3_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_and3.cir.lst">
+  <Spice>
+**** XSPICE digital 3-Input AND ****
+*
+.subckt d_and3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C] Y and1
+.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_and3X
+
+.SUBCKT Digital_XSPICE_d_AND3  gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 d_and3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 0 -40 #0000ff 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <.PortSym -30 -10 1 0 A>
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 2 0 B>
+    <.PortSym -30 10 3 0 C>
+    <.PortSym 30 0 4 180 Y>
+  </Symbol>
+</Component>
+
+<Component d_AND4>
+  <Description>
+4-Input AND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_AND4 _net0 _net1 _net2 _net3 _net4 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="d_and4_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_and4.cir.lst">
+  <Spice>
+**** XSPICE digital 4-Input AND ****
+*
+.subckt d_and4X A B C D Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C D] Y and1
+.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_and4X
+
+.SUBCKT Digital_XSPICE_d_AND4  gnd _net0 _net1 _net2 _net3 _net4 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 _net4 d_and4X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -30 1 0 A>
+    <.PortSym -30 -10 2 0 B>
+    <.PortSym -30 10 3 0 C>
+    <.PortSym -30 30 4 0 D>
+    <.PortSym 40 0 5 180 Y>
+    <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <Line -10 40 0 -80 #0000ff 2 1>
+    <Line 20 0 20 0 #000080 2 1>
+    <EArc -20 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line 0 20 -10 0 #0000ff 2 1>
+    <Line 0 -20 -10 0 #0000ff 2 1>
+  </Symbol>
+</Component>
+
+<Component d_AND8>
+  <Description>
+8-Input AND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_AND8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 gnd Type="d_and8_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_and8.cir.lst">
+  <Spice>
+**** XSPICE digital 8-Input AND ****
+*
+.subckt d_and8X A B C D E F G H Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C D E F G H] Y and1
+.model and1 d_and(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_and8X
+
+.SUBCKT Digital_XSPICE_d_AND8  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 d_and8X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <Line 20 0 20 0 #000080 2 1>
+    <EArc -20 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line 0 20 -10 0 #0000ff 2 1>
+    <Line 0 -20 -10 0 #0000ff 2 1>
+    <Line -30 50 20 0 #000080 2 1>
+    <Line -30 70 20 0 #000080 2 1>
+    <Line -30 -70 20 0 #000080 2 1>
+    <Line -30 -50 20 0 #000080 2 1>
+    <.PortSym -30 -70 1 0 A>
+    <.PortSym -30 -50 2 0 B>
+    <.PortSym -30 -30 3 0 C>
+    <.PortSym -30 -10 4 0 D>
+    <.PortSym -30 10 5 0 E>
+    <.PortSym -30 30 6 0 F>
+    <.PortSym -30 50 7 0 G>
+    <.PortSym -30 70 8 0 H>
+    <.PortSym 40 0 9 180 Y>
+    <Line -10 80 0 -160 #0000ff 2 1>
+  </Symbol>
+</Component>
+
+<Component d_NAND2>
+  <Description>
+2-Input NAND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_NAND2 _net0 _net1 _net2 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 gnd Type="d_nand2_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nand2.cir.lst">
+  <Spice>
+**** XSPICE digital 2-Input NAND ****
+*
+.subckt d_nand2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B] Y nand1
+.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nand2X
+
+.SUBCKT Digital_XSPICE_d_NAND2  gnd _net0 _net1 _net2 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 d_nand2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 10 2 0 B>
+    <.PortSym 30 0 3 180 Y>
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 0 -40 #0000ff 2 1>
+    <Ellipse 10 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line 18 0 12 0 #000080 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+  </Symbol>
+</Component>
+
+<Component d_NAND3>
+  <Description>
+3-Input NAND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_NAND3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_nand3_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nand3.cir.lst">
+  <Spice>
+**** XSPICE digital 3-Input NAND ****
+*
+.subckt d_nand3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C] Y nand1
+.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nand3X
+
+
+.SUBCKT Digital_XSPICE_d_NAND3  gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 d_nand3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 0 -40 #0000ff 2 1>
+    <Ellipse 10 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line 18 0 12 0 #000080 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 2 0 B>
+    <.PortSym -30 10 3 0 C>
+    <.PortSym 30 0 4 180 Y>
+  </Symbol>
+</Component>
+
+<Component d_NAND4>
+  <Description>
+4-Input NAND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_NAND4 _net0 _net1 _net2 _net3 _net4 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 _net4 gnd Type="d_nand4_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nand4.cir.lst">
+  <Spice>
+**** XSPICE digital 4-Input NAND ****
+*
+.subckt d_nand4X A B C D Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C D] Y nand1
+.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nand4X
+
+
+.SUBCKT Digital_XSPICE_d_NAND4  gnd _net0 _net1 _net2 _net3 _net4 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 _net4 d_nand4X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <Line -10 40 0 -80 #0000ff 2 1>
+    <.PortSym -30 -30 1 0 A>
+    <.PortSym -30 -10 2 0 B>
+    <.PortSym -30 10 3 0 C>
+    <.PortSym -30 30 4 0 D>
+    <.PortSym 40 0 5 180 Y>
+    <Line 28 0 12 0 #000080 2 1>
+    <Ellipse 20 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <EArc -20 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line 0 20 -10 0 #0000ff 2 1>
+    <Line 0 -20 -10 0 #0000ff 2 1>
+    <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+  </Symbol>
+</Component>
+
+<Component d_NAND8>
+  <Description>
+8-Input NAND
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_NAND8 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 gnd Type="d_nand8_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nand8.cir.lst">
+  <Spice>
+**** XSPICE digital 8-Input AND ****
+*
+.subckt d_nand8X A B C D E F G H Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C D E F G H] Y nand1
+.model nand1 d_nand(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nand8X
+
+.SUBCKT Digital_XSPICE_d_NAND8  gnd _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 _net4 _net5 _net6 _net7 _net8 d_nand8X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID 20 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 -30 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <Line -30 30 20 0 #000080 2 1>
+    <EArc -20 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line 0 20 -10 0 #0000ff 2 1>
+    <Line 0 -20 -10 0 #0000ff 2 1>
+    <Line -30 50 20 0 #000080 2 1>
+    <Line -30 70 20 0 #000080 2 1>
+    <Line -30 -70 20 0 #000080 2 1>
+    <Line -30 -50 20 0 #000080 2 1>
+    <.PortSym -30 -70 1 0 A>
+    <.PortSym -30 -50 2 0 B>
+    <.PortSym -30 -30 3 0 C>
+    <.PortSym -30 -10 4 0 D>
+    <.PortSym -30 10 5 0 E>
+    <.PortSym -30 30 6 0 F>
+    <.PortSym -30 50 7 0 G>
+    <.PortSym -30 70 8 0 H>
+    <.PortSym 40 0 9 180 Y>
+    <Line -10 80 0 -160 #0000ff 2 1>
+    <Ellipse 20 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line 28 0 12 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component d_OR2>
+  <Description>
+2-Input OR
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_OR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net2 _net1 gnd Type="d_or2_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_or2.cir.lst">
+  <Spice>
+**** XSPICE digital 2-Input OR ****
+*
+.subckt d_or2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B] Y or1
+.model or1 d_or(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_or2X
+
+.SUBCKT Digital_XSPICE_d_OR2  gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net2 _net1 d_or2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 10 2 0 B>
+    <.PortSym 30 0 3 180 Y>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 -5 0 #0000ff 2 1>
+    <Line -10 -20 -5 0 #0000ff 2 1>
+  </Symbol>
+</Component>
+
+<Component d_OR3>
+  <Description>
+3-Input OR
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_OR3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_or3_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_or3.cir.lst">
+  <Spice>
+**** XSPICE digital 3-Input OR ****
+*
+.subckt d_or3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C] Y or1
+.model or1 d_or(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_or3X
+
+.SUBCKT Digital_XSPICE_d_OR3  gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 d_or3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 -5 0 #0000ff 2 1>
+    <Line -10 -20 -5 0 #0000ff 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 2 0 B>
+    <.PortSym -30 10 3 0 C>
+    <.PortSym 30 0 4 180 Y>
+  </Symbol>
+</Component>
+
+<Component d_NOR2>
+  <Description>
+2-Input NOR
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_NOR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net2 _net1 gnd Type="d_nor2_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nor2.cir.lst">
+  <Spice>
+**** XSPICE digital 2-Input NOR ****
+*
+.subckt d_nor2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B] Y nor1
+.model nor1 d_nor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nor2X
+
+.SUBCKT Digital_XSPICE_d_NOR2  gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net2 _net1 d_nor2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 10 2 0 B>
+    <.PortSym 30 0 3 180 Y>
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 -5 0 #0000ff 2 1>
+    <Line -10 -20 -5 0 #0000ff 2 1>
+    <Ellipse 10 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line 18 0 12 0 #000080 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+  </Symbol>
+</Component>
+
+<Component d_NOR3>
+  <Description>
+2-Input NOR
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_NOR3 _net0 _net1 _net2 _net3 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 _net2 _net3 gnd Type="d_nor3_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nor3.cir.lst">
+  <Spice>
+**** XSPICE digital 3-Input NOR ****
+*
+.subckt d_nor3X A B C Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B C] Y nor1
+.model nor1 d_nor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nor3X
+
+.SUBCKT Digital_XSPICE_d_NOR3  gnd _net0 _net1 _net2 _net3 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 _net2 _net3 d_nor3X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #0000ff 2 1>
+    <Line -10 20 -5 0 #0000ff 2 1>
+    <Line -10 -20 -5 0 #0000ff 2 1>
+    <Ellipse 10 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line 18 0 12 0 #000080 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 0 20 0 #000080 2 1>
+    <.PortSym -30 0 2 0 B>
+    <.PortSym -30 10 3 0 C>
+    <.PortSym 30 0 4 180 Y>
+  </Symbol>
+</Component>
+
+<Component d_XOR2>
+  <Description>
+2-Input XOR
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_XOR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net2 _net1 gnd Type="d_xor2_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_xor2.cir.lst">
+  <Spice>
+**** XSPICE digital 2-Input XOR ****
+*
+.subckt d_xor2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B] Y xor1
+.model xor1 d_xor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_xor2X
+
+.SUBCKT Digital_XSPICE_d_XOR2  gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net2 _net1 d_xor2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 10 2 0 B>
+    <.PortSym 30 0 3 180 Y>
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line 10 0 20 0 #000080 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #0000ff 2 1>
+    <EArc -15 -20 10 40 4320 2880 #0000ff 2 1>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+  </Symbol>
+</Component>
+
+<Component d_XNOR2>
+  <Description>
+2-Input XNOR
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_XNOR2 _net0 _net2 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net2 _net1 gnd Type="d_nor2_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_nor2.cir.lst">
+  <Spice>
+**** XSPICE digital 2-Input NOR ****
+*
+.subckt d_nor2X A B Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 [A B] Y nor1
+.model nor1 d_nor(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_nor2X
+
+.SUBCKT Digital_XSPICE_d_XNOR2  gnd _net0 _net2 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net2 _net1 d_nor2X RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 10 2 0 B>
+    <.PortSym 30 0 3 180 Y>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <.PortSym -30 -10 1 0 A>
+    <EArc -30 -20 40 40 4320 2880 #0000ff 2 1>
+    <Line -30 -10 20 0 #000080 2 1>
+    <Line -30 10 20 0 #000080 2 1>
+    <EArc -20 -20 10 40 4320 2880 #0000ff 2 1>
+    <EArc -15 -20 10 40 4320 2880 #0000ff 2 1>
+    <Ellipse 10 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line 18 0 12 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component d_BUF>
+  <Description>
+Digital Buffer
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_BUF _net0 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 gnd Type="d_buf_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_buf.cir.lst">
+  <Spice>
+**** XSPICE digital Buffer ****
+*
+.subckt d_bufX A Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 A Y buf1
+.model buf1 d_buffer(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_bufX
+
+.SUBCKT Digital_XSPICE_d_BUF  gnd _net0 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 d_bufX RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 15 0 15 0 #000080 2 1>
+    <Line -30 0 20 0 #000080 2 1>
+    <Line -10 -15 25 15 #0000ff 2 1>
+    <Line -10 15 0 -30 #0000ff 2 1>
+    <Line -10 15 25 -15 #0000ff 2 1>
+    <.PortSym -30 0 1 0 A>
+    <.PortSym 30 0 2 180 Y>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+  </Symbol>
+</Component>
+
+<Component d_INV>
+  <Description>
+Digital Inverter
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_INV _net0 _net1 Rise_Delay="1e-10" Fall_Delay="1e-10" Input_Load="0.5e-12"
+Sub:X1 _net0 _net1 gnd Type="d_inv_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_inv.cir.lst">
+  <Spice>
+**** XSPICE digital Inverter ****
+*
+.subckt d_invX A Y rise_delay=1e-10 fall_delay=1e-10 input_load=0.5e-12
+*
+a1 A Y inv1
+.model inv1 d_inverter(rise_delay='rise_delay' fall_delay='fall_delay' input_load='input_load')
+*
+.ends d_invX
+
+.SUBCKT Digital_XSPICE_d_INV  gnd _net0 _net1 Rise_Delay=1e-10 Fall_Delay=1e-10 Input_Load=0.5e-12 
+X1 _net0 _net1 d_invX RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY INPUT_LOAD=INPUT_LOAD
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID 10 14 Y "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=">
+    <Line -30 0 20 0 #000080 2 1>
+    <Line -10 -15 25 15 #0000ff 2 1>
+    <Line -10 15 0 -30 #0000ff 2 1>
+    <Line -10 15 25 -15 #0000ff 2 1>
+    <.PortSym -30 0 1 0 A>
+    <.PortSym 30 0 2 180 Y>
+    <Ellipse 10 -4 8 8 #0000ff 1 1 #0000ff 1 1>
+    <Line 18 0 12 0 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component d_TRI>
+  <Description>
+Tri-State Buffer
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_TRI _net0 _net2 _net1 Delay="1e-10" Input_Load="0.5e-12" Enable_Load="0.5e-12"
+SpLib:X1 _net0 _net2 _net1 File="d_tri.cir" Device="D_TRIX" SymPattern="auto" Params="DELAY=DELAY INPUT_LOAD=INPUT_LOAD ENABLE_LOAD=ENABLE_LOAD" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT Digital_XSPICE_d_TRI  gnd _net0 _net2 _net1 Delay=1e-10 Input_Load=0.5e-12 Enable_Load=0.5e-12 
+XX1  _net0 _net2 _net1 D_TRIX DELAY=DELAY INPUT_LOAD=INPUT_LOAD ENABLE_LOAD=ENABLE_LOAD
+.ENDS
+  </Spice>
+  <VerilogModel>
+module Sub_Digital_XSPICE_d_TRI (net_net0, net_net2, net_net1);
+ inout net_net0, net_net1, net_net2;
+
+ parameter Delay = 1e-10;
+ parameter Input_Load = 0.5e-12;
+ parameter Enable_Load = 0.5e-12;
+
+endmodule
+  </VerilogModel>
+  <VHDLModel>
+library ieee;
+use ieee.std_logic_1164.all;
+entity Sub_Digital_XSPICE_d_TRI is
+ generic (Delay : real := 1e-10;
+ Input_Load : real := 0.5e-12;
+ Enable_Load : real := 0.5e-12;
+ );
+ port (net_net0 : inout  ;
+ net_net2 : inout  ;
+ net_net1 : inout  );
+end entity;
+use work.all;
+architecture Arch_Sub_Digital_XSPICE_d_TRI of Sub_Digital_XSPICE_d_TRI is
+begin
+end architecture;
+  </VHDLModel>
+  <Symbol>
+    <Line 15 0 15 0 #000080 2 1>
+    <Line -30 0 20 0 #000080 2 1>
+    <Line -10 -15 25 15 #0000ff 2 1>
+    <Line -10 15 0 -30 #0000ff 2 1>
+    <Line -10 15 25 -15 #0000ff 2 1>
+    <.PortSym -30 0 1 0 A>
+    <.PortSym 30 0 3 180 Y>
+    <.ID 20 14 Y "1=Delay=1e-10=Delay (sec)=" "1=Input_Load=0.5e-12=Input Load (F)=" "1=Enable_Load=0.5e-12=Enable Load (F)=">
+    <Line 0 10 0 10 #000080 2 1>
+    <.PortSym 0 20 2 0 E>
+  </Symbol>
+</Component>
+
+<Component d_D_FF>
+  <Description>
+D Flip-Flop
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_D_FF _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10"
+Sub:X1 _net0 _net1 _net4 _net5 _net2 _net3 gnd Type="d_dff_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_dff.cir.lst">
+  <Spice>
+* XSPICE d_dff Digital D Flip-Flop
+* 
+.subckt d_ff d_d d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10
+*
+ad1 d_d d_c d_set d_reset d_q d_q_ flop1
+.model flop1 d_dff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay')
+*
+.ends d_dff
+
+.SUBCKT Digital_XSPICE_d_D_FF  gnd _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 
+X1 _net0 _net1 _net4 _net5 _net2 _net3 d_ff  CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 0 -40 0 -20 #000080 2 1>
+    <Line 0 61 0 -20 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 -20 20 0 #000080 2 1>
+    <Line 30 -20 20 0 #000080 2 1>
+    <Line 30 20 20 0 #000080 2 1>
+    <Line 14 11 12 0 #000080 2 1>
+    <Text 14 -31 12 #000080 0 "Q">
+    <Text 14 9 12 #000080 0 "Q">
+    <Line -15 20 -15 -10 #000080 2 1>
+    <Line -30 30 15 -10 #000080 2 1>
+    <.PortSym -50 -20 1 0 D>
+    <.PortSym -50 20 2 0 C>
+    <.PortSym 50 -20 5 180 Q>
+    <.PortSym 50 20 6 180 Q_>
+    <Text -6 -40 12 #000080 0 "S">
+    <Text -6 20 12 #000080 0 "R">
+    <Text -26 -30 12 #000080 0 "D">
+    <Rectangle -30 -40 60 80 #0000ff 2 1 #c0c0c0 1 0>
+    <.PortSym 0 60 4 0 Reset>
+    <.PortSym 0 -60 3 0 Set>
+    <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=">
+  </Symbol>
+</Component>
+
+<Component d_D_FF_B>
+  <Description>
+D Flip-Flop
+Set-Reset Swapped
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_D_FF_B _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10"
+Sub:X1 _net0 _net1 _net4 _net5 _net2 _net3 gnd Type="d_dff_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_dff.cir.lst">
+  <Spice>
+* XSPICE d_dff Digital D Flip-Flop
+* 
+.subckt d_ff d_d d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10
+*
+ad1 d_d d_c d_set d_reset d_q d_q_ flop1
+.model flop1 d_dff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay')
+*
+.ends d_dff
+
+.SUBCKT Digital_XSPICE_d_D_FF_B  gnd _net0 _net1 _net4 _net5 _net2 _net3 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 
+X1 _net0 _net1 _net4 _net5 _net2 _net3 d_ff  CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 0 -40 0 -20 #000080 2 1>
+    <Line 0 61 0 -20 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 -20 20 0 #000080 2 1>
+    <Line 30 -20 20 0 #000080 2 1>
+    <Line 30 20 20 0 #000080 2 1>
+    <Line 14 11 12 0 #000080 2 1>
+    <Text 14 -31 12 #000080 0 "Q">
+    <Text 14 9 12 #000080 0 "Q">
+    <Line -15 20 -15 -10 #000080 2 1>
+    <Line -30 30 15 -10 #000080 2 1>
+    <.PortSym -50 -20 1 0 D>
+    <.PortSym -50 20 2 0 C>
+    <.PortSym 50 -20 5 180 Q>
+    <.PortSym 50 20 6 180 Q_>
+    <Text -26 -30 12 #000080 0 "D">
+    <Rectangle -30 -40 60 80 #0000ff 2 1 #c0c0c0 1 0>
+    <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=">
+    <Text -6 20 12 #000080 0 "S">
+    <Text -6 -40 12 #000080 0 "R">
+    <.PortSym 0 -60 4 0 Reset>
+    <.PortSym 0 60 3 0 Set>
+  </Symbol>
+</Component>
+
+<Component d_JK_FF>
+  <Description>
+JK Flip-Flop
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_JK_FF _net0 _net3 _net1 _net5 _net6 _net4 _net2 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10"
+Sub:X1 _net0 _net3 _net1 _net5 _net6 _net4 _net2 gnd Type="d_jkff_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_jkff.cir.lst">
+  <Spice>
+* XSPICE d_jkff Digital J-K Flip-Flop
+* 
+.subckt d_jkff d_j d_k d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10
+*
+ad1 d_j d_k d_c d_set d_reset d_q d_q_ flop1
+.model flop1 d_jkff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay')
+*
+.ends d_jkff
+
+.SUBCKT Digital_XSPICE_d_JK_FF  gnd _net0 _net3 _net1 _net5 _net6 _net4 _net2 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 
+X1 _net0 _net3 _net1 _net5 _net6 _net4 _net2 d_jkff  CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 0 -40 0 -20 #000080 2 1>
+    <Line 0 61 0 -20 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 -20 20 0 #000080 2 1>
+    <Line 30 -20 20 0 #000080 2 1>
+    <Line 30 20 20 0 #000080 2 1>
+    <Line 14 11 12 0 #000080 2 1>
+    <Text 14 -31 12 #000080 0 "Q">
+    <Text 14 9 12 #000080 0 "Q">
+    <.PortSym -50 -20 1 0 J>
+    <.PortSym -50 20 2 0 K>
+    <Text -6 -40 12 #000080 0 "S">
+    <Text -6 20 12 #000080 0 "R">
+    <Text -26 -30 12 #000080 0 "J">
+    <Rectangle -30 -40 60 80 #0000ff 2 1 #c0c0c0 1 0>
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 0 20 0 #000080 2 1>
+    <.PortSym -50 0 3 0 C>
+    <.PortSym 0 -60 4 0 Set>
+    <.PortSym 0 60 5 0 Reset>
+    <.PortSym 50 -20 6 180 Q>
+    <.PortSym 50 20 7 180 Q_>
+    <Text -26 10 12 #000080 0 "K">
+    <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=">
+  </Symbol>
+</Component>
+
+<Component d_SR_FF>
+  <Description>
+SR Flip-Flop
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_SR_FF _net5 _net6 _net0 _net3 _net4 _net2 _net1 Clk_Delay="1e-10" Set_Delay="1e-10" Reset_Delay="1e-10" IC="0" Rise_Delay="1e-10" Fall_Delay="1e-10"
+Sub:X1 _net5 _net6 _net0 _net3 _net4 _net2 _net1 gnd Type="d_srff_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_srff.cir.lst">
+  <Spice>
+* XSPICE d_srff Digital S-R Flip-Flop
+* 
+.subckt d_srff d_s d_r d_c d_set d_reset d_q d_q_ clk_delay=1.0e-10 set_delay=1.0e-10 reset_delay=1.0e-10 ic=0 rise_delay=1.0e-10 fall_delay=1e-10
+*
+ad1 d_s d_r d_c d_set d_reset d_q d_q_ flop1
+.model flop1 d_srff(clk_delay='clk_delay' set_delay='set_delay' reset_delay='reset_delay' ic='ic' rise_delay='rise_delay' fall_delay='fall_delay')
+*
+.ends d_srff
+
+.SUBCKT Digital_XSPICE_d_SR_FF  gnd _net5 _net6 _net0 _net3 _net4 _net2 _net1 Clk_Delay=1e-10 Set_Delay=1e-10 Reset_Delay=1e-10 IC=0 Rise_Delay=1e-10 Fall_Delay=1e-10 
+X1 _net5 _net6 _net0 _net3 _net4 _net2 _net1 d_srff  CLK_DELAY=CLK_DELAY SET_DELAY=SET_DELAY RESET_DELAY=RESET_DELAY IC=IC RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 0 -40 0 -20 #000080 2 1>
+    <Line 0 61 0 -20 #000080 2 1>
+    <Line -50 20 20 0 #000080 2 1>
+    <Line -50 -20 20 0 #000080 2 1>
+    <Line 30 -20 20 0 #000080 2 1>
+    <Line 30 20 20 0 #000080 2 1>
+    <Line 14 11 12 0 #000080 2 1>
+    <Text 14 -31 12 #000080 0 "Q">
+    <Text 14 9 12 #000080 0 "Q">
+    <.PortSym -50 -20 1 0 S>
+    <.PortSym -50 20 2 0 R>
+    <Text -6 -40 12 #000080 0 "S">
+    <Text -6 20 12 #000080 0 "R">
+    <Text -26 -30 12 #000080 0 "S">
+    <Rectangle -30 -40 60 80 #0000ff 2 1 #c0c0c0 1 0>
+    <.ID 20 44 Y "1=Clk_Delay=1e-10=Clock Delay (sec)=" "1=Set_Delay=1e-10=Set Delay (sec)=" "1=Reset_Delay=1e-10=Reset Delay (sec)=" "1=IC=0=Output Initial State=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=">
+    <Line -15 0 -15 -10 #000080 2 1>
+    <Line -30 10 15 -10 #000080 2 1>
+    <Line -50 0 20 0 #000080 2 1>
+    <.PortSym -50 0 3 0 C>
+    <.PortSym 0 -60 4 0 Set>
+    <.PortSym 0 60 5 0 Reset>
+    <.PortSym 50 -20 6 180 Q>
+    <.PortSym 50 20 7 180 Q_>
+    <Text -26 10 12 #000080 0 "R">
+  </Symbol>
+</Component>
+
+<Component d_Divider>
+  <Description>
+Digital Divider
+50/50 Duty Requires
+High-Cycles=(Div-Factor)/2
+XSPICE Based
+  </Description>
+  <Model>
+.Def:Digital_XSPICE_d_Divider _net0 _net1 Div_Factor="2" High_Cycles="1" I_Count="0" Rise_Delay="1e-10" Fall_Delay="1e-10"
+Sub:X1 _net0 _net1 gnd Type="d_divider_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "d_divider.cir.lst">
+  <Spice>
+**** XSPICE digital divider d_fdiv ****
+*
+* d_fin - digital input
+* d_fout - digital output
+*
+.subckt dig_div d_fin d_fout div_factor=2 high_cycles=1 i_count=0 rise_delay=1e-10 fall_delay=1e-10)
+*
+adiv1 d_fin d_fout divider
+*
+.model divider d_fdiv(div_factor='div_factor' high_cycles='high_cycles' i_count='i_count' rise_delay='rise_delay' fall_delay='fall_delay')
+*
+.ends dig_div
+
+.SUBCKT Digital_XSPICE_d_Divider  gnd _net0 _net1 Div_Factor=2 High_Cycles=1 I_Count=0 Rise_Delay=1e-10 Fall_Delay=1e-10 
+X1 _net0 _net1 dig_div DIV_FACTOR=DIV_FACTOR HIGH_CYCLES=HIGH_CYCLES I_COUNT=I_COUNT RISE_DELAY=RISE_DELAY FALL_DELAY=FALL_DELAY
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line 9 0 -17 0 #000000 2 1>
+    <Ellipse -3 5 6 6 #000000 1 1 #000000 1 1>
+    <Ellipse -3 -11 6 6 #000000 1 1 #000000 1 1>
+    <.PortSym -50 0 1 0 IN>
+    <.PortSym 50 0 2 180 OUT>
+    <Rectangle -30 -20 60 40 #0000ff 2 1 #c0c0c0 1 0>
+    <Line -50 0 20 0 #000080 2 1>
+    <Line 30 0 20 0 #000080 2 1>
+    <Text -24 -10 12 #000080 0 "I">
+    <Text 15 -10 12 #000080 0 "O">
+    <.ID -20 24 DIV "1=Div_Factor=2=Division Ratio=" "1=High_Cycles=1=Number of high clock cycles=" "1=I_Count=0=Initial count value=" "1=Rise_Delay=1e-10=Rise Delay (sec)=" "1=Fall_Delay=1e-10=Fall Delay (sec)=">
+  </Symbol>
+</Component>

library/DualGateMOSFET.lib

@@ -0,0 +1,306 @@
+<Qucs Library 25.1.0 "DualGateMOSFET">
+
+<Component BF980>
+  <Description>
+BF980 dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF980 _net0 _net1 _net2 _net3
+SpLib:X1 _net0 _net1 _net2 _net3 File="DualGateMos.cir" Device="BF980A" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF980  gnd _net0 _net1 _net2 _net3 
+XX1  _net0 _net1 _net2 _net3 BF980A 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 4 0 P4>
+    <.PortSym 0 -30 1 0 P1>
+    <.PortSym -30 10 3 0 P3>
+    <.PortSym -30 -10 2 0 P2>
+  </Symbol>
+</Component>
+
+<Component BF981>
+  <Description>
+BF981 dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF981 _net1 _net2 _net3 _net0
+SpLib:X1 _net0 _net1 _net2 _net3 File="DualGateMos.cir" Device="BF981" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF981  gnd _net1 _net2 _net3 _net0 
+XX1  _net0 _net1 _net2 _net3 BF981 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 1 0 P1>
+    <.PortSym 0 -30 2 0 P2>
+    <.PortSym -30 -10 3 0 P3>
+    <.PortSym -30 10 4 0 P4>
+  </Symbol>
+</Component>
+
+<Component BF992>
+  <Description>
+BF992 dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF992 _net0 _net1 _net3 _net2
+SpLib:X1 _net0 _net1 _net3 _net2 File="DualGateMos.cir" Device="BF992" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF992  gnd _net0 _net1 _net3 _net2 
+XX1  _net0 _net1 _net3 _net2 BF992 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 1 0 P1>
+    <.PortSym 0 -30 2 0 P2>
+    <.PortSym -30 -10 3 0 P3>
+    <.PortSym -30 10 4 0 P4>
+  </Symbol>
+</Component>
+
+<Component BF993>
+  <Description>
+BF993 dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF993 _net0 _net1 _net2 _net3
+SpLib:X1 _net0 _net1 _net2 _net3 File="DualGateMos.cir" Device="BF993" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF993  gnd _net0 _net1 _net2 _net3 
+XX1  _net0 _net1 _net2 _net3 BF993 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 -30 1 0 P1>
+    <.PortSym -30 -10 2 0 P2>
+    <.PortSym -30 10 3 0 P3>
+    <.PortSym 0 30 4 0 P4>
+  </Symbol>
+</Component>
+
+<Component BF994>
+  <Description>
+BF994 dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF994 _net0 _net1 _net3 _net2
+SpLib:X1 _net0 _net1 _net3 _net2 File="DualGateMos.cir" Device="BF994S" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF994  gnd _net0 _net1 _net3 _net2 
+XX1  _net0 _net1 _net3 _net2 BF994S 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 1 0 P1>
+    <.PortSym 0 -30 2 0 P2>
+    <.PortSym -30 -10 3 0 P3>
+    <.PortSym -30 10 4 0 P4>
+  </Symbol>
+</Component>
+
+<Component BF998>
+  <Description>
+BF998 dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF998 _net0 _net1 _net3 _net2
+SpLib:X1 _net0 _net1 _net3 _net2 File="DualGateMos.cir" Device="BF998" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF998  gnd _net0 _net1 _net3 _net2 
+XX1  _net0 _net1 _net3 _net2 BF998 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 1 0 P1>
+    <.PortSym 0 -30 2 0 P2>
+    <.PortSym -30 -10 3 0 P3>
+    <.PortSym -30 10 4 0 P4>
+  </Symbol>
+</Component>
+
+<Component BF998WR>
+  <Description>
+BF998WR dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_BF998WR _net0 _net1 _net3 _net2
+SpLib:X1 _net0 _net1 _net3 _net2 File="DualGateMos.cir" Device="BF998WR" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_BF998WR  gnd _net0 _net1 _net3 _net2 
+XX1  _net0 _net1 _net3 _net2 BF998WR 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 1 0 P1>
+    <.PortSym 0 -30 2 0 P2>
+    <.PortSym -30 -10 3 0 P3>
+    <.PortSym -30 10 4 0 P4>
+  </Symbol>
+</Component>
+
+<Component MN201>
+  <Description>
+MN201 (3N201) dual gate MOSFET
+  </Description>
+  <Model>
+.Def:DualGateMOSFET_MN201 _net0 _net2 _net1 _net3
+SpLib:X1 _net0 _net2 _net1 _net3 File="DualGateMos.cir" Device="MN201" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT DualGateMOSFET_MN201  gnd _net0 _net2 _net1 _net3 
+XX1  _net0 _net2 _net1 _net3 MN201 
+.ENDS
+  </Spice>
+<SpiceAttach "DualGateMos.cir">
+  <Symbol>
+    <.ID 8 -26 T>
+    <Line -10 -11 10 0 #000080 2 1>
+    <Line 0 -11 0 -19 #000080 2 1>
+    <Line -10 11 10 0 #000080 2 1>
+    <Line 0 0 0 30 #000080 2 1>
+    <Line -10 0 10 0 #000080 2 1>
+    <Line -10 -4 0 8 #000080 3 1>
+    <Line -10 7 0 9 #000080 3 1>
+    <Line -9 0 5 -5 #000080 2 1>
+    <Line -9 0 5 5 #000080 2 1>
+    <Line -30 10 16 0 #000080 2 1>
+    <Line -30 -10 16 0 #000080 2 1>
+    <Line -10 -16 0 9 #000080 3 1>
+    <Line -14 -15 0 5 #000080 3 1>
+    <Line -14 5 0 5 #000080 3 1>
+    <.PortSym 0 30 4 0 P4>
+    <.PortSym 0 -30 1 0 P1>
+    <.PortSym -30 10 3 0 P3>
+    <.PortSym -30 -10 2 0 P2>
+  </Symbol>
+</Component>
+

library/DualGateMOSFET/DualGateMos.cir

@@ -0,0 +1,242 @@
+*   BF992 SPICE MODEL JANUARY 1996 PHILIPS SEMICONDUCTORS
+*   ENVELOPE    SOT143 
+*   1.: SOURCE;  2.: DRAIN;  3.: GATE 2;  4.: GATE 1;
+.SUBCKT BF992 1 2 3 4
+        L10          1 10   0.12N
+        L20          2 20   0.12N
+        L30          3 30   0.12N
+        L40          4 40   0.12N
+        L11         10 11   1.20N
+        L21         20 21   1.20N
+        L31         30 31   1.20N
+        L41         40 41   1.20N
+        C13         10 30   0.085P
+        C14         10 40   0.085P
+        C21         10 20   0.017P
+        C23         20 30   0.085P
+        C24         20 40   0.005P
+        D11         42 11   ZENER
+        D12         42 41   ZENER
+        D21         32 11   ZENER
+        D22         32 31   ZENER
+        RS          10 12   100
+        MOS1        61 41 11 12 GATE1 L=2E-6 W=2200E-6
+        MOS2        21 31 61 12 GATE2 L=3.0E-6 W=2200E-6
+
+.MODEL  ZENER  D  BV=10 CJO=1.2E-12  RS=10
+
+.MODEL  GATE1
++  NMOS LEVEL=3 UO=904.9  VTO=-0.2051 NFS=300E9 TOX=60E-9
++  NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=500E-9 THETA=0.11
++  ETA=0.2095 KAPPA=0.6488 LD=0.3E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.MODEL  GATE2 
++  NMOS LEVEL=3 UO=600  VTO=-0.2051 NFS=300E9 TOX=60E-9
++  NSUB=3E15  VMAX=100E3 RS=2.0 RD=2.0 XJ=500E-9 THETA=0.11
++  ETA=0.06  KAPPA=2 LD=0.3E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=1.467E-12 CBS=0.5E-12
+
+.ENDS BF992
+
+
+
+*   BF998 SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS
+*   ENVELOPE    SOT143 
+*   1.: SOURCE;  2.: DRAIN;  3.: GATE 2;  4.: GATE 1;
+.SUBCKT BF998 1 2 3 4
+        L10          1 10   0.12N
+        L20          2 20   0.12N
+        L30          3 30   0.12N
+        L40          4 40   0.12N
+        L11         10 11   1.20N
+        L21         20 21   1.20N
+        L31         30 31   1.20N
+        L41         40 41   1.20N
+        C13         10 30   0.085P
+        C14         10 40   0.085P
+        C21         10 20   0.017P
+        C23         20 30   0.085P
+        C24         20 40   0.005P
+        D11         42 11   ZENER
+        D12         42 41   ZENER
+        D21         32 11   ZENER
+        D22         32 31   ZENER
+        RS          10 12   100
+        MOS1        61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
+        MOS2        21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
+
+.MODEL  ZENER  D  BV=10 CJO=1.2E-12  RS=10
+
+.MODEL  GATE1
++  NMOS LEVEL=3 UO=600  VTO=-0.250 NFS=300E9 TOX=42E-9
++  NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
++  ETA=0.06 KAPPA=2 LD=0.1E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.MODEL  GATE2 
++  NMOS LEVEL=3 UO=600  VTO=-0.250 NFS=300E9 TOX=42E-9
++  NSUB=3E15  VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
++  ETA=0.06  KAPPA=2 LD=0.1E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.ENDS BF998
+
+
+*   BF998WR SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS
+*   ENVELOPE    SOT343R 
+*   1.: SOURCE;  2.: DRAIN;  3.: GATE 2;  4.: GATE 1;
+.SUBCKT BF998WR 1 2 3 4
+        L10          1 10   0.10N
+        L20          2 20   0.34N
+        L30          3 30   0.34N
+        L40          4 40   0.34N
+        L11         10 11   1.10N
+        L21         20 21   1.10N
+        L31         30 31   1.10N
+        L41         40 41   1.10N
+        C13         10 30   0.060P
+        C14         10 40   0.060P
+        C21         10 20   0.050P
+        C23         20 30   0.070P
+        C24         20 40   0.005P
+        D11         42 11   ZENER
+        D12         42 41   ZENER
+        D21         32 11   ZENER
+        D22         32 31   ZENER
+        RS          10 12   100
+        MOS1        61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
+        MOS2        21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
+
+.MODEL  ZENER  D  BV=10 CJO=1.2E-12  RS=10
+
+.MODEL  GATE1
++  NMOS LEVEL=3 UO=600  VTO=-0.250 NFS=300E9 TOX=42E-9
++  NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
++  ETA=0.06 KAPPA=2 LD=0.1E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.MODEL  GATE2 
++  NMOS LEVEL=3 UO=600  VTO=-0.250 NFS=300E9 TOX=42E-9
++  NSUB=3E15  VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
++  ETA=0.06  KAPPA=2 LD=0.1E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.ENDS BF998WR
+
+
+*   BF994S SPICE MODEL MARCH 1996 PHILIPS SEMICONDUCTORS
+*   ENVELOPE    SOT143 
+*   1.: SOURCE;  2.: DRAIN;  3.: GATE 2;  4.: GATE 1;
+.SUBCKT BF994S 1 2 3 4
+        L10          1 10   0.12N
+        L20          2 20   0.12N
+        L30          3 30   0.12N
+        L40          4 40   0.12N
+        L11         10 11   1.20N
+        L21         20 21   1.20N
+        L31         30 31   1.20N
+        L41         40 41   1.20N
+        C13         10 30   0.085P
+        C14         10 40   0.085P
+        C21         10 20   0.017P
+        C23         20 30   0.085P
+        C24         20 40   0.005P
+        D11         42 11   ZENER
+        D12         42 41   ZENER
+        D21         32 11   ZENER
+        D22         32 31   ZENER
+        RS          10 12   100
+        MOS1        61 41 11 12 GATE1 L=2E-6 W=1280E-6
+        MOS2        21 31 61 12 GATE2 L=3.0E-6 W=1280E-6
+
+.MODEL  ZENER  D  BV=10 CJO=1.2E-12  RS=10
+
+.MODEL  GATE1
++  NMOS LEVEL=3 UO=750  VTO=-0.4357 NFS=300E9 TOX=60E-9
++  NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
++  ETA=0.1686 KAPPA=2.282 LD=0.3E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.MODEL  GATE2 
++  NMOS LEVEL=3 UO=600  VTO=-0.4357 NFS=300E9 TOX=60E-9
++  NSUB=3E15  VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
++  ETA=0.06  KAPPA=2 LD=0.3E-6
++  CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
+
+.ENDS BF994S
+
+
+
+*.SUBCKT BF981 1 2 3 4
+*Drain  Gate2 Gate1 Source   
+
+* Pin order changed in BF981 model
+*   1.: SOURCE;  2.: DRAIN;  3.: GATE 2;  4.: GATE 1;
+.SUBCKT BF981 4 1 2 3
+
+*Dual Gate Mosfet
+MD1 5 3 4 4 BF981A
+MD2 1 2 5 4 BF981B W=50U
+.MODEL BF981A NMOS (LEVEL=1 VTO=-1.1 KP=15M GAMMA=3.3U
++ PHI=.75 LAMBDA=3.75M RS=2.2 IS=12.5F PB=.8 MJ=.46
++ CBD=3.43P CBS=4.11P CGSO=240P CGDO=200P CGBO=20.5N)
+.MODEL BF981B NMOS (LEVEL=1 VTO=-.9 KP=18M GAMMA=19.08U
++ PHI=.75 LAMBDA=13.75M RD=41.3 IS=12.5F PB=.8 MJ=.46
++ CBD=3.43P CBS=4.11P CGSO=240P CGDO=200P CGBO=14.5N)
+* Philips
+* N-Channel Depletion DG-MOSFET
+.ENDS BF981
+*
+**********
+* Copyright Intusoft 1991
+* All Rights Reserved
+**********
+*SYM=DGMOS
+.SUBCKT BF993 1      2     3     4
+*Connections  Drain  Gate2 Gate1 Source
+*Dual Gate Mosfet
+MD1 5 3 4 4 BF993G1
+MD2 1 2 5 4 BF993G2 W=65U
+.MODEL BF993G1 NMOS (LEVEL=1 VTO=-1.0 KP=23M GAMMA=7.4U 
++ PHI=.75 LAMBDA=13.75M RS=2.5 IS=31.2F PB=.8 MJ=.46
++ CBD=9.66P CBS=11.5P CGSO=600P CGDO=500P CGBO=61.4N
+.MODEL BF993G2 NMOS (LEVEL=1 VTO=-.9 KP=25M GAMMA=30.4U
++ PHI=.75 LAMBDA=23.75M RD=74.4 IS=31.2F PB=.8 MJ=.46
++ CBD=9.66P CBS=11.5P CGSO=600P CGDO=500P CGBO=61.4N
+* Siemens
+* N-Channel Depletion DG-MOSFET 
+.ENDS
+**********
+*SYM=DGMOS
+.SUBCKT BF980A 1      2     3     4
+*Connections   Drain  Gate2 Gate1 Source
+*Dual Gate Mosfet
+MD1 5 3 4 4 BF980AA
+MD2 1 2 5 4 BF980AB W=50U
+.MODEL BF980AA NMOS (LEVEL=1 VTO=-1.0 KP=17M GAMMA=4.34U
++ PHI=.75 LAMBDA=4.16M RS=3.2 IS=20.8F PB=.8 MJ=.46
++ CBD=2.89P CBS=3.47P CGSO=300P CGDO=250P CGBO=25.4N)
+.MODEL BF980AB NMOS (LEVEL=1 VTO=-.9 KP=20M GAMMA=17.47U
++ PHI=.75 LAMBDA=14.16M RD=30 IS=20.8F PB=.8 MJ=.46
++ CBD=2.89P CBS=3.47P CGSO=300P CGDO=250P CGBO=25.4N)
+* Philips
+* N-Channel Depletion DG-MOSFET 
+.ENDS
+**********
+*SYM=DGMOS
+.SUBCKT MN201 1      2     3     4
+*Connections  Drain  Gate2 Gate1 Source
+*Dual Gate Mosfet
+MD1 5 3 4 4 MN201-1
+MD2 1 2 5 4 MN201-2 W=35U
+.MODEL MN201-1 NMOS (LEVEL=1 VTO=-1.45 KP=11.8M GAMMA=3.26U
++ PHI=.75 LAMBDA=30M RD=1M RS=20.8 IS=25F PB=.8 MJ=.46
++ CBD=6.64P CBS=7.97P CGSO=168P CGDO=140P CGBO=32.6N)
+.MODEL MN201-2 NMOS (LEVEL=1 VTO=-1.00 KP=12.5M GAMMA=27.26U
++ PHI=.75 LAMBDA=37M RD=15.3 RS=1M IS=30F PB=.8 MJ=.46
++ CBD=6.64P CBS=7.97P CGSO=168P CGDO=140P CGBO=32.6N)
+* Motorola
+* N-Channel Depletion DG-MOSFET 
+.ENDS
+*************

library/LaserDiodes.lib

@@ -0,0 +1,264 @@
+<Qucs Library 24.3.0 "LaserDiodes">
+
+<Component LaserDiodeRed>
+  <Description>
+Generic 650nm 100mw Laser Diode
+LD=150ma, PD=15piv
+by Alexander Bordodynov
+  </Description>
+  <Model>
+.Def:LaserDiodes_LaserDiodeRed _net0 _net2 _net1 _net3
+Sub:X1 _net0 _net2 _net1 _net3 gnd Type="LaserDiodeRed_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "LaserDiodeRed.cir.lst">
+  <Spice>
+* Alexander Bordodynov
+* 650nm 100mw Laser Diode
+.Subckt Laser com lk pha pw Pnom=100m inom=150m ith=35m iphnom=0.1m Pth=1m cLd=10p cph=40p rsLd=1 nLd=2 isLD=1e-17 tauLD=1n tauFd=5n
+.param k=(Pnom-Pth*inom/ith)/(inom-ith)
+.param kf=iphnom/Pnom
+.param ctau=0.001*tauFd
+cLd com lk {cLD}
+cph com pha {cph}
+D1 5 lk0 dLd
+D10 com lk0 dLd2
+rs lk0 lk {rsLd}
+VAm1 com 5 0
+rut lk com 10Meg
+v1 ith 0 {ith}
+*v3 kf 0 {iphnom/Pnom}
+Hled pwled 0 vam1 {2*Pth/ith}
+B1 pw pwled v=uramp(2*i(vam1)-v(ith))*{k}
+CtauFd pwtau 0 {ctau}
+Rtau pwtau pw 1k
+B2 com pha i=v(pwtau)*{kf}
+.model dLd D is={isLd/2} n={nLd} eg={nLd*1.11}
+.model dLd2 D is={isLd/2} n={nLd} eg={nLd*1.11} tt={tauLD*2}
+.ends Laser
+*
+.SUBCKT LaserDiodes_LaserDiodeRed  gnd _net0 _net2 _net1 _net3 
+X1 _net0 _net2 _net1 _net3 Laser
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -40 -20 0 40 #000080 2 1>
+    <Line -40 20 80 0 #000080 2 1>
+    <Line 20 30 0 -20 #000080 2 1>
+    <Line 40 -20 0 40 #000080 2 1>
+    <Line 40 0 10 0 #000080 2 1>
+    <Line -40 -20 80 0 #000080 2 1>
+    <Line 11 11 18 0 #000080 2 1>
+    <Line 11 -1 18 0 #000080 2 1>
+    <Line 20 11 -9 -12 #000080 2 1>
+    <Line 20 11 9 -12 #000080 2 1>
+    <Line -11 -1 -18 0 #000080 2 1>
+    <Line -11 11 -18 0 #000080 2 1>
+    <Line -20 -1 9 12 #000080 2 1>
+    <Line -20 -1 -9 12 #000080 2 1>
+    <Line 15 4 10 0 #000080 2 1>
+    <Line 20 -10 0 9 #000080 2 1>
+    <Line -20 -10 0 9 #000080 2 1>
+    <Ellipse -3 -13 6 6 #000080 1 1 #000080 1 1>
+    <Line -20 -10 40 0 #000080 2 1>
+    <Line -20 11 0 19 #000080 2 1>
+    <Line 0 -30 0 20 #000080 2 1>
+    <Text -36 -18 8 #000000 0 "PD">
+    <Text 24 -18 8 #000000 0 "LD">
+    <Line 36 5 -8 0 #000080 2 1>
+    <Line 8 5 -15 0 #000080 2 1>
+    <.PortSym 0 -30 1 0 COM>
+    <.PortSym -20 30 3 0 PHA>
+    <.PortSym 20 30 2 180 LK>
+    <.PortSym 50 0 4 180 PW>
+    <.ID 20 -46 LD>
+    <Line 34 2 3 3 #000080 2 1>
+    <Line 34 8 3 -3 #000080 2 1>
+    <Line -5 8 -3 -3 #000080 2 1>
+    <Line -5 2 -3 3 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component SLD1121VS>
+  <Description>
+Sony SLD1121VS
+670nm 5mw Laser Diode
+PIN Diode Power Monitor
+LD=50ma, PD=15piv
+  </Description>
+  <Model>
+.Def:LaserDiodes_SLD1121VS _net0 _net2 _net1
+Sub:X1 _net0 _net2 _net1 gnd Type="SLD1121VS_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "SLD1121VS.cir.lst">
+  <Spice>
+* SLD1121VS from Sony  EDN, RAP  7/97
+* LD = Laser diode cathode
+* C  = Common pin
+* PD = Photodiode anode
+.SUBCKT SLD1121 LD C PD
+Dld C I dlaser
+Vid I LD
+Eop op 0 TABLE {I(Vid)} (0,0) (37m,0.3m) (40m,0.5m) (47m,5m) (100m,40m)
+Rdummy op 0 1k
+Gopd C PD TABLE {V(op)} (0,0) (30m,1.5m) (60m,3.0m)
+Dpd PD C pdetec
+.model dlaser D IS=5E-37 N=1 RS=2 BV=2 IBV=10u
+*EG=2.8 XTI=3
+.model pdetec D CJO=5p BV=15 IBV=10u
+.ends SLD1121
+*
+
+.SUBCKT LaserDiodes_SLD1121VS  gnd _net0 _net2 _net1 
+X1 _net0 _net2 _net1 SLD1121
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -40 -20 0 40 #000080 2 1>
+    <Line -40 20 80 0 #000080 2 1>
+    <Line 20 30 0 -20 #000080 2 1>
+    <Line 40 -20 0 40 #000080 2 1>
+    <Line -40 -20 80 0 #000080 2 1>
+    <Line 11 11 18 0 #000080 2 1>
+    <Line 11 -1 18 0 #000080 2 1>
+    <Line 20 11 -9 -12 #000080 2 1>
+    <Line 20 11 9 -12 #000080 2 1>
+    <Line -11 -1 -18 0 #000080 2 1>
+    <Line -11 11 -18 0 #000080 2 1>
+    <Line -20 -1 9 12 #000080 2 1>
+    <Line -20 -1 -9 12 #000080 2 1>
+    <Line 15 4 10 0 #000080 2 1>
+    <Line 20 -10 0 9 #000080 2 1>
+    <Line -20 -10 0 9 #000080 2 1>
+    <Ellipse -3 -13 6 6 #000080 1 1 #000080 1 1>
+    <Line -20 -10 40 0 #000080 2 1>
+    <Line -20 11 0 19 #000080 2 1>
+    <Line 0 -30 0 20 #000080 2 1>
+    <Text -36 -18 8 #000000 0 "PD">
+    <Text 24 -18 8 #000000 0 "LD">
+    <Line 36 5 -8 0 #000080 2 1>
+    <Line 8 5 -15 0 #000080 2 1>
+    <.PortSym -20 30 3 0 PD>
+    <.ID 20 -46 LD>
+    <Line 34 2 3 3 #000080 2 1>
+    <Line 34 8 3 -3 #000080 2 1>
+    <Line -5 8 -3 -3 #000080 2 1>
+    <Line -5 2 -3 3 #000080 2 1>
+    <.PortSym 0 -30 2 0 C>
+    <.PortSym 20 30 1 180 LD>
+  </Symbol>
+</Component>
+
+<Component RLD90QZW3>
+  <Description>
+Rolm RLD90QZW3
+905nm 90W Pulsed Laser Diode
+LD=28A, Duty Cycle=0.1%
+Requirements:
+.spiceinit: set ngbehavior=psa
+  </Description>
+  <Model>
+.Def:LaserDiodes_RLD90QZW3 _net0 _net1 _net2 _net3
+Sub:X1 _net0 _net1 _net2 _net3 gnd Type="RLD90QZW3_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "RLD90QZW3.cir.lst">
+  <Spice>
+* RLD90QZW3
+* Optical Power model
+* LD
+* 4V 50A 
+* Model Generated by ROHM
+* All Rights Reserved
+* Commercial Use or Resale Restricted
+* Date: 2020/06/10
+* model version: 1
+**********************A C
+.SUBCKT RLD90QZW3_sub 1 2 OPT GND
+.PARAM T0=25
+*
+.PARAM s_rate= 1
+*
+.PARAM K1_fw= 794.3u
+.PARAM M1_fw= -5.817k
+.PARAM N1_fw= -498.5
+.PARAM k2_fw= 790m
+.PARAM M2_fw= -9.271k
+.PARAM k3_fw= 230m
+.PARAM M3_fw= 448.3
+.PARAM N3_fw= -89.69
+*
+.PARAM k1_rv= 1.259u
+.PARAM K2_rv= 500
+.PARAM M1_rv= 16.67
+.PARAM k3_rv= 115.3n
+.PARAM M3_rv= -1k
+.PARAM N3_rv= 314.6
+.PARAM K4_rv= 55.56
+.PARAM M4_rv= -5.405k
+*
+.PARAM k1_cr= 10.43
+.PARAM k2_cr= 3.956
+.PARAM k3_cr= 40.13
+.PARAM k4_cr= 7.911
+.PARAM k5_cr= -653.7m
+.PARAM k6_cr= -5k
+*
+.PARAM v1_lm_n= 300k
+.PARAM v1_lm_p= 400k
+.PARAM v42_lm_n= 6k
+.PARAM v42_lm_p= 10000
+*
+.FUNC R1(I)   {k3_fw*I*EXP((TEMP-T0)/M3_fw*EXP((TEMP-T0)/N3_fw))}
+.FUNC I1(V)   {MIN(MAX(IF(TIME>0,IF(V>0,{K1_fw*(EXP(V/k2_fw/EXP((TEMP-T0)/M2_fw))-1)*
++              EXP((TEMP-T0)/M1_fw*EXP((TEMP-T0)/N1_fw))},0),0),-1MEG),1MEG)}
+.FUNC I2(V)   {(EXP(V/K2_rv)-1)*k1_rv*EXP((TEMP-T0)/M1_rv)}
+.FUNC I3(V)   {(EXP(-V/(K4_rv *EXP((TEMP-T0)/M4_rv)))-1)*
++              k3_rv*EXP((TEMP-T0)/M3_rv *EXP((TEMP-T0)/N3_rv))}
+.FUNC C1(V,W) {k1_cr*(V-k2_cr)+k3_cr*(1-(-k6_cr)*TANH(W/(-k6_cr))/k4_cr)**k5_cr}
+V1 1 3 0
+E1 3 4 VALUE={R1(MIN(MAX(I(V1)/s_rate,-v1_lm_n),v1_lm_p))}
+V2 4 5 0
+C1 5 2 {1p * s_rate}
+G1 4 2 VALUE={s_rate*(I1(MIN(V(4,2),v42_lm_p))+
++             I2(MIN(V(4,2),v42_lm_p))-I3(MAX(V(4,2),-v42_lm_n)))+
++             I(V2)*C1(MAX(V(4,2),k2_cr),MIN(V(4,2),k2_cr))}
+R1 4 2 10T
+********* ********* ********* ********* ********* ********* ********* ********* ********* ********* *********
+E11 OPT GND VALUE={MIN(MAX(IF(TIME>0,IF(I(V1)>0.95,(-4.00458853433877E-05)*I(V1)*I(V1)*I(V1)+(-0.00857231667301519)*I(V1)*I(V1)+(3.42809879019094)*I(V1)+(-3.21312517416111),0),0),-1MEG),1MEG)}
+*
+.ENDS RLD90QZW3_sub
+
+
+.SUBCKT LaserDiodes_RLD90QZW3  gnd _net0 _net1 _net2 _net3 
+X1 _net0 _net1 _net2 _net3 RLD90QZW3_sub
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 20 60 0 #000080 2 1>
+    <Line 0 -6 0 -24 #000080 2 1>
+    <Line 0 30 0 -24 #000080 2 1>
+    <Line -9 6 18 0 #000080 2 1>
+    <Line -9 -6 18 0 #000080 2 1>
+    <Line 0 6 -9 -12 #000080 2 1>
+    <Line 0 6 9 -12 #000080 2 1>
+    <Line -5 -1 10 0 #000080 2 1>
+    <Line 16 0 -8 0 #000080 2 1>
+    <Line 14 -3 3 3 #000080 2 1>
+    <Line 14 3 3 -3 #000080 2 1>
+    <Line 30 -20 0 40 #000080 2 1>
+    <Line 30 -10 10 0 #000080 2 1>
+    <Line 30 10 10 0 #000080 2 1>
+    <Line -30 -20 0 40 #000080 2 1>
+    <Line -30 -20 60 0 #000080 2 1>
+    <Text -26 -18 8 #000000 0 "LD">
+    <Text 14 -18 8 #000000 0 "PO">
+    <Text 14 2 8 #000000 0 "GD">
+    <.PortSym 40 10 4 180 GND>
+    <.PortSym 40 -10 3 180 OPT>
+    <.PortSym 0 -30 1 0 A>
+    <.PortSym 0 30 2 0 C>
+    <.ID 20 -46 LD>
+  </Symbol>
+</Component>

library/Neon.lib

@@ -0,0 +1,51 @@
+<Qucs Library 24.3.0 "Neon">
+
+<Component Neon>
+  <Description>
+65V Neon Lamp Spice Model
+Author: Zabb Csaba
+
+  </Description>
+  <Model>
+.Def:Neon_Neon _net0 _net1
+Sub:X1 _net0 _net1 gnd Type="Neon_sp"
+.Def:End
+  </Model>
+  <ModelIncludes "Neon.sp.lst">
+  <Spice>
+.SUBCKT NB1 10 20
+D1  10 1  D1
+D2  20 1  D1
+D3  2  10 D1
+D4  2  20 D1
+D5  1  4  D2
+V1  4  5  0
+H1  6  0  V1 4.8E4
+R1  0  6  1E6
+B1  5  7  I=3.7E-4*V(5,7)+5.75E-3*V(5,7)*V(6)
+C1  5  7  1.3E-11
+R2  7  2  2.13E3
+R3  3  5  3.5E3
+R4  3  8  1.85E3
+V2  8  2  1.442E2
+.MODEL D1 D(IS=8E-16)
+.MODEL D2 D(IS=2.1E-13 N=1.8)
+.ENDS NB1
+
+
+.SUBCKT Neon_Neon  gnd _net0 _net1 
+X1 _net0 _net1 NB1
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -40 0 30 0 #000080 2 1>
+    <Line 10 0 30 0 #000080 2 1>
+    <Line -10 -20 0 40 #000080 2 1>
+    <Line 10 -20 0 40 #000080 2 1>
+    <Ellipse -30 -30 60 60 #ffaa00 2 1 #c0c0c0 12 1>
+    <.PortSym -40 0 1 0 P1>
+    <.PortSym 40 0 2 180 P2>
+    <.ID -20 44 NB>
+  </Symbol>
+</Component>
+

library/Optocoupler.lib

@@ -1,17 +1,15 @@
-<Qucs Library 2.1.0 "Optocoupler">
+<Qucs Library 24.3.0 "Optocoupler">
 
 <Component 4N25>
   <Description>
-4N25 BJT optocoupler 
+4N25 BJT optocoupler
   </Description>
   <Model>
 .Def:Optocoupler_4N25 _net0 _net1 _net2 _net3
 Sub:X1 _net0 _net1 _net2 _net3 gnd Type="n4N25_cir"
 .Def:End
   </Model>
-  <ModelIncludes "4N25.cir.lst">
-  <Spice>* Qucs 2.1.0  Optocoupler_4N25.sch
-
+  <Spice>
 * OPTO-ISO from User Library in TURBO SPICE
 * Orig 8/17/99
 * Modified TMH 2/15/23
@@ -57,26 +55,24 @@ X1 _net0 _net1 _net2 _net3 4N25
     <Line -30 -6 0 -24 #000080 2 1>
     <Line 30 -15 0 -15 #000080 2 1>
     <Line -50 20 100 0 #808080 2 1>
-    <.PortSym -30 -30 1 0>
-    <.PortSym -30 30 2 0>
-    <.PortSym 30 -30 3 180>
-    <.PortSym 30 30 4 180>
+    <.PortSym -30 -30 1 0 P1>
+    <.PortSym -30 30 2 0 P2>
+    <.PortSym 30 -30 3 180 P3>
+    <.PortSym 30 30 4 180 P4>
     <.ID 70 -16 X>
   </Symbol>
 </Component>
 
 <Component 4N33>
   <Description>
-4N33 Darlington optocoupler
+4N33 Dralington optocoupler
   </Description>
   <Model>
 .Def:Optocoupler_4N33 _net3 _net4 _net2 _net0 _net1
 Sub:X2 _net0 _net1 _net2 _net3 _net4 gnd Type="n4n33_cir"
 .Def:End
   </Model>
-  <ModelIncludes "4n33.cir.lst">
-  <Spice>* Qucs 2.1.0  Optocoupler_4N33.sch
-
+  <Spice>
 .subckt 4n33_MC 4 5 3 1 2
 * 4 -> LED ANODE   5 -> LED CATHODE
 * 3 -> EMITTER     1 -> COLLECTOR   2 -> BASE
@@ -168,26 +164,150 @@ X2 _net0 _net1 _net2 _net3 _net4 4n33_MC
     <Line 65 20 0 -40 #000080 2 1>
     <Line -45 20 110 0 #000080 2 1>
     <Line -45 -20 110 0 #000080 2 1>
-    <.PortSym -30 -30 4 180>
-    <.PortSym -30 30 5 0>
-    <.PortSym 50 30 3 180>
-    <.PortSym 50 -30 1 0>
-    <.PortSym 20 -30 2 0>
+    <.PortSym -30 -30 4 180 P4>
+    <.PortSym -30 30 5 0 P5>
+    <.PortSym 50 30 3 180 P3>
+    <.PortSym 50 -30 1 0 P1>
+    <.PortSym 20 -30 2 0 P2>
+  </Symbol>
+</Component>
+
+<Component ACPLK30T>
+  <Description>
+Automotive MOSFET driver photovoltaic optocoupler
+  </Description>
+  <Model>
+.Def:Optocoupler_ACPLK30T _net0 _net1 _net2 _net3
+Sub:X1 _net0 _net1 _net2 _net3 gnd Type="ACPLK30T_cir"
+.Def:End
+  </Model>
+  <Spice>
+* Copyright 2014 Avago Technologies
+* ACPL-K30T Spice Macromodel
+* Modified 2/22/23
+* ACPL-K30T.cir changed to ACPLK30T.cir to remove need for LTspice compat
+* Dietmar Warning, add NR=2 to .model PDC 
+* https://sourceforge.net/p/ngspice/discussion/120973/thread/8c874eb3ec/
+*
+.subckt ACPLK30T AN CA VOUT+ VOUT-
+*E1 N002 CA N014 N016 {CTR} ; removed need for LTspice compat
+E1 N002 CA N014 N016 0.083
+XX1 AN CA N016 N014 vbu
+XX2 N002 CA N017 N015 pdnoc
+XX3 N002 CA N008 N017 pdnoc
+XX4 N002 CA N015 N013 pdnoc
+XX5 N002 CA N013 N012 pdnoc
+XX6 N002 CA N012 N010 pdnoc
+XX7 N002 CA N010 N007 pdnoc
+XX8 N002 CA N007 N004 pdnoc
+XX9 N002 CA N004 N003 pdnoc
+XX10 N002 CA N003 P001 pdnoc
+XX11 N002 CA P002 P003 pdnoc
+XX12 N002 CA P003 N001 pdnoc
+XX13 N002 CA P001 P002 pdnoc
+E2 N011 VOUT- N008 N001 1
+R2 N009 N011 1k
+D1 VOUT- N001 D
+D2 N008 VOUT+ D
+E3 N009 N006 N008 VOUT- 1
+Q1 VOUT+ N006 N005 0 NPN
+R3 VOUT- N005 3k
+C1 VOUT- N009 37n
+C2 VOUT- VOUT+ 100p
+*.param CTR=0.083 ; removed need for LTspice compat
+.ends ACPLK30T
+
+.subckt vbu AN CA LOPN LOPP
+RSERIES AN 5 5
+DELECT 5 CA VBUNOR
+ELED 6 LOPN 5 CA 1
+DOPTIC 6 8 VBUNORC
+FPHOTO LOPN 3 VSENSE 1
+VSENSE 8 LOPN 0
+RL 3 LOPN 0.1
+EOUT LOPP LOPN 3 LOPN 60
+VSIM LOPN CA 0
+Rnl 6 N001 5k
+Vnl N002 LOPN 0
+Fnl LOPN LOPN Vnl 1
+Dsw N001 N002 DSW
+.model DSW D Is=1e-4
+.model VBUNOR D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u CJO=60p VJ=.75 M=.3333 FC=.5 TT=20n
+.model VBUNORC D IS=330E-21 N=1.5 XTI=3 EG=1.52 BV=10.38 IBV=100u CJO=0 VJ=.75 M=.3333 FC=.5 TT=0
+.ends vbu
+
+.subckt pdnoc LOPP LOPN AN CA
+D1 AN CA PDC
+G1 CA AN LOPP LOPN 0.0010
+.model PDC D IS=1E-14 N=1.5 CJO=10p M=0.95 VJ=0.75 ISR=100.0E-12 BV=100 TT=5E-9 NR=2; NR=2 added for ngspice
+.ends pdnoc
+
+.model D D
+
+.model NPN NPN
+.model PNP PNP
+
+
+
+
+
+.SUBCKT Optocoupler_ACPLK30T  gnd _net0 _net1 _net2 _net3 
+X1 _net0 _net1 _net2 _net3 ACPLK30T
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID -40 -96 U>
+    <.PortSym -60 -30 1 0 AN>
+    <.PortSym -60 30 2 0 CA>
+    <.PortSym 80 -30 3 180 VOUT_P>
+    <.PortSym 80 30 4 180 VOUT_N>
+    <Line -30 -30 -30 0 #000080 2 1>
+    <Line -60 30 30 0 #000080 2 1>
+    <Line -40 -10 20 0 #000080 2 1>
+    <Line -40 -10 10 20 #000080 2 1>
+    <Line -40 10 20 0 #000080 2 1>
+    <Line -30 30 0 -20 #000080 2 1>
+    <Line -30 -30 0 20 #000080 2 1>
+    <Line -30 10 10 -20 #000080 2 1>
+    <Line 0 0 0 0 #000080 0 1>
+    <Line 5 -5 -5 10 #000080 2 1>
+    <Line -5 -5 10 0 #000080 2 1>
+    <Line -15 5 20 -10 #000080 2 1>
+    <Rectangle -50 -50 120 100 #000080 2 1 #c0c0c0 1 0>
+    <Line 20 -30 60 0 #000080 2 1>
+    <Line 20 -25 0 -5 #000080 2 1>
+    <Line 20 30 0 -10 #000080 2 1>
+    <Line 10 -25 20 0 #000080 2 1>
+    <Line 10 -15 20 0 #000080 2 1>
+    <Line 15 -10 10 0 #000080 2 1>
+    <Line 10 -5 20 0 #000080 2 1>
+    <Line 15 0 10 0 #000080 2 1>
+    <Line 10 5 20 0 #000080 2 1>
+    <Line 15 10 10 0 #000080 2 1>
+    <Line 10 15 20 0 #000080 2 1>
+    <Line 15 20 10 0 #000080 2 1>
+    <Line 15 -20 10 0 #000080 2 1>
+    <Line 80 30 -60 0 #000080 2 1>
+    <Rectangle 40 -20 20 40 #000080 2 1 #c0c0c0 1 0>
+    <Line 50 -20 0 -10 #000080 2 1>
+    <Line 50 30 0 -10 #000080 2 1>
+    <Text 46 16 5 #000080 90 "TURN OFF">
+    <Line 50 -35 0 -10 #000080 2 1>
+    <Line 45 -40 10 0 #000080 2 1>
+    <Line 45 40 10 0 #000080 2 1>
   </Symbol>
 </Component>
 
 <Component MOC223>
   <Description>
-MOC223 Darlington optocoupler
+MOC223 Dralington optocoupler
   </Description>
   <Model>
 .Def:Optocoupler_MOC223 _net0 _net2 _net1 _net3 _net4
 Sub:X2 _net3 _net4 _net1 _net0 _net2 gnd Type="moc223_cir"
 .Def:End
   </Model>
-  <ModelIncludes "moc223.cir.lst">
-  <Spice>* Qucs 2.1.0  Optocoupler_MOC223.sch
-
+  <Spice>
 .subckt moc223_MC 4 5 3 1 2
 
 
@@ -286,11 +406,11 @@ X2 _net3 _net4 _net1 _net0 _net2 moc223_MC
     <Line 65 20 0 -40 #000080 2 1>
     <Line -45 20 110 0 #000080 2 1>
     <Line -45 -20 110 0 #000080 2 1>
-    <.PortSym -30 -30 4 180>
-    <.PortSym -30 30 5 0>
-    <.PortSym 50 30 3 180>
-    <.PortSym 50 -30 1 0>
-    <.PortSym 20 -30 2 0>
+    <.PortSym -30 -30 4 180 P4>
+    <.PortSym -30 30 5 0 P5>
+    <.PortSym 50 30 3 180 P3>
+    <.PortSym 50 -30 1 0 P1>
+    <.PortSym 20 -30 2 0 P2>
   </Symbol>
 </Component>
 
@@ -304,9 +424,7 @@ model provided by Helmut Sennewald  11/23/2008
 Sub:X1 _net0 _net3 _net1 _net2 gnd Type="MOC3082_sub_cir"
 .Def:End
   </Model>
-  <ModelIncludes "MOC3082_sub.cir.lst">
-  <Spice>* Qucs 2.1.0  Optocoupler_MOC3082.sch
-
+  <Spice>
 * OPTO TRIAC With Zero Crossing Switching
 * Helmut Sennewald  11/23/2008
 * 04/12/2009, change in B-sources: V(ctrl10) -> V(ctrl10,4)
@@ -358,10 +476,10 @@ X1 _net0 _net3 _net1 _net2 moc3082_sub
   </Spice>
   <Symbol>
     <.ID -40 -96 X>
-    <.PortSym -60 -30 1 0>
-    <.PortSym -60 30 2 0>
-    <.PortSym 80 -30 3 180>
-    <.PortSym 80 30 4 180>
+    <.PortSym -60 -30 1 0 P1>
+    <.PortSym -60 30 2 0 P2>
+    <.PortSym 80 -30 3 180 P3>
+    <.PortSym 80 30 4 180 P4>
     <Line -30 -30 -30 0 #000080 2 1>
     <Line -60 30 30 0 #000080 2 1>
     <Line -40 -10 20 0 #000080 2 1>
@@ -398,3 +516,108 @@ X1 _net0 _net3 _net1 _net2 moc3082_sub
   </Symbol>
 </Component>
 
+<Component MOC3052>
+  <Description>
+600V triac optocoupler; no zero-cross. LTspice mode is required for this model. Designed by Zabb Csaba: https://fotoelektronika.com/spice-models/
+  </Description>
+  <Model>
+.Def:Optocoupler_MOC3052 _net0 _net3 _net1 _net2
+SpLib:X1 _net0 _net3 _net1 _net2 File="moc3052_3062.cir" Device="MOC3052" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT Optocoupler_MOC3052  gnd _net0 _net3 _net1 _net2 
+XX1  _net0 _net3 _net1 _net2 MOC3052 
+.ENDS
+  </Spice>
+<SpiceAttach "moc3052_3062.cir">
+  <Symbol>
+    <.ID -40 -96 X>
+    <.PortSym -60 -30 1 0 P1>
+    <.PortSym -60 30 2 0 P2>
+    <.PortSym 80 -30 3 180 P3>
+    <.PortSym 80 30 4 180 P4>
+    <Line -30 -30 -30 0 #000080 2 1>
+    <Line -60 30 30 0 #000080 2 1>
+    <Line -40 -10 20 0 #000080 2 1>
+    <Line -40 -10 10 20 #000080 2 1>
+    <Line -40 10 20 0 #000080 2 1>
+    <Line -30 30 0 -20 #000080 2 1>
+    <Line -30 -30 0 20 #000080 2 1>
+    <Line -30 10 10 -20 #000080 2 1>
+    <Rectangle -50 -50 120 100 #000080 2 1 #c0c0c0 1 0>
+    <Line 40 6 0 24 #000080 2 1>
+    <Line 40 -30 0 24 #000080 2 1>
+    <Line 58 6 -36 0 #000080 2 1>
+    <Line 31 6 -9 -12 #000080 2 1>
+    <Line 31 6 9 -12 #000080 2 1>
+    <Line 49 -6 9 12 #000080 2 1>
+    <Line 49 -6 -9 12 #000080 2 1>
+    <Line 58 -6 -36 0 #000080 2 1>
+    <Line 80 30 -40 0 #000080 2 1>
+    <Line 80 -30 -40 0 #000080 2 1>
+    <Line 0 2 4 -4 #000080 2 1>
+    <Line -6 -4 6 6 #000080 2 1>
+    <Arrow 4 -2 10 10 9 3 #000080 2 1 1>
+    <Arrow 2 8 10 10 9 3 #000080 2 1 1>
+    <Line -2 12 4 -4 #000080 2 1>
+    <Line -8 6 6 6 #000080 2 1>
+  </Symbol>
+</Component>
+
+<Component MOC3063>
+  <Description>
+600V triac optocoupler with zero-cross detector. LTspice mode is required for this model. Designed by Zabb Csaba: https://fotoelektronika.com/spice-models/
+  </Description>
+  <Model>
+.Def:Optocoupler_MOC3063 _net0 _net3 _net1 _net2
+SpLib:X1 _net0 _net3 _net1 _net2 File="moc3052_3062.cir" Device="MOC3063" SymPattern="auto" Params="" PinAssign=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT Optocoupler_MOC3063  gnd _net0 _net3 _net1 _net2 
+XX1  _net0 _net3 _net1 _net2 MOC3063 
+.ENDS
+  </Spice>
+<SpiceAttach "moc3052_3062.cir">
+  <Symbol>
+    <.ID -40 -96 X>
+    <.PortSym -60 -30 1 0 P1>
+    <.PortSym -60 30 2 0 P2>
+    <.PortSym 80 -30 3 180 P3>
+    <.PortSym 80 30 4 180 P4>
+    <Line -30 -30 -30 0 #000080 2 1>
+    <Line -60 30 30 0 #000080 2 1>
+    <Line -40 -10 20 0 #000080 2 1>
+    <Line -40 -10 10 20 #000080 2 1>
+    <Line -40 10 20 0 #000080 2 1>
+    <Line -30 30 0 -20 #000080 2 1>
+    <Line -30 -30 0 20 #000080 2 1>
+    <Line -30 10 10 -20 #000080 2 1>
+    <Rectangle -50 -50 120 100 #000080 2 1 #c0c0c0 1 0>
+    <Line 40 6 0 24 #000080 2 1>
+    <Line 40 -30 0 24 #000080 2 1>
+    <Line 58 6 -36 0 #000080 2 1>
+    <Line 22 10 5 0 #000080 2 3>
+    <Line 27 10 4 -4 #000080 2 3>
+    <Line 31 6 -9 -12 #000080 2 1>
+    <Line 31 6 9 -12 #000080 2 1>
+    <Line 49 -6 9 12 #000080 2 1>
+    <Line 49 -6 -9 12 #000080 2 1>
+    <Line 58 -6 -36 0 #000080 2 1>
+    <Line -10 2 4 -4 #000080 2 1>
+    <Line -16 -4 6 6 #000080 2 1>
+    <Arrow -6 -2 10 10 9 3 #000080 2 1 1>
+    <Arrow -8 8 10 10 9 3 #000080 2 1 1>
+    <Line -12 12 4 -4 #000080 2 1>
+    <Line -18 6 6 6 #000080 2 1>
+    <Rectangle 6 14 24 20 #000080 2 1 #c0c0c0 1 0>
+    <Line 22 14 0 -4 #000080 2 3>
+    <Text 8 18 8 #000080 0 "ZCC">
+    <Line 14 14 0 -28 #000080 2 3>
+    <Line 14 -14 26 0 #000080 2 3>
+    <Line 30 24 10 0 #000080 2 3>
+    <Line 80 30 -40 0 #000080 2 1>
+    <Line 80 -30 -40 0 #000080 2 1>
+  </Symbol>
+</Component>

library/Optocoupler/moc3052_3062.cir

@@ -0,0 +1,144 @@
+*  MOC3063 Zero-Cross Optoisolators Triac Driver Output Spice Model
+*  Date  : 08/09/2024
+*  Author: Zabb Csaba
+*  IRED  emitting  diodes  optically  coupled  to  monolithic  silicon  detectors
+*  performing the functions of Zero Voltage Crossing bilateral triac drivers.
+*  VINH=Inhibit Voltage (MT1–MT2 Voltage above which device will not trigger.)
+*
+.SUBCKT MOC3063  1   2   6    4    
+*                A   K  MT2  MT1 
+DL  1   3   IRLED
+V1  3   2   0
+H1  17  0   V1  1
+E1  DEL 0   TABLE {V(17)}
++ (5m,  50)
++ (10m, 30)
++ (15m, 19)
++ (20m, 14)
++ (25m, 11)
++ (30m, 10)
++ (35m, 9.0)
++ (40m, 8.0)
++ (45m, 7.0)
++ (50m, 6.5)
++ (55m, 6.1)
+E2  11  0   VALUE {IF(V(17)>5m,1,0)}
+X1  11  10  DEL 0 VCRES
+C1  10  0   1n
+E3  12  4   VALUE {IF(V(10)>0.63,1,0)}
+S1  6   13  11  0 SW1
+R1  13  8   3MEG
+C2  8   4   10p
+D1  8   7   DX
+D2  4   7   DX 
+E4  9   4   VALUE {IF(ABS(V(8,4))<12,1,0)}
+B1  G   4   I=V(12,4)*V(9,4)*10m
+C3  2   4   800f
+R2  2   4   10G
+X2  6   4   G   TRIAC Ih=0.25m
+.MODEL  DX D(BV=50 IBV=10u)
+.MODEL  SW1 VSWITCH (ROFF=1G RON=1 VOFF=0 VON=1)
+.MODEL  IRLED D (IS=8E-17 N=1.5 RS=2 IKF=7.5E-2 IBV=1.5E-08 NBV=7E1  BV=1.6E1 CJO=4E-11 TT=1E-08 EG=1.46)
+.ENDS MOC3063
+
+*  Author: Zabb Csaba
+*  IRED emitting diode optically coupled to a non-zero-crossing silicon bilateral AC switch (triac).
+*
+.SUBCKT MOC3052  1   2   6    4   
+*                A   K  MT2  MT1 
+DL  1   5   IRLED
+V1  5   2   0
+H1  7   0   V1  1
+E1  DEL 0   TABLE {V(7)}
++ (10m, 30)
++ (15m, 19)
++ (20m, 14)
++ (25m, 11)
++ (30m, 10)
++ (35m, 9.0)
++ (40m, 8.0)
++ (45m, 7.0)
++ (50m, 6.5)
++ (55m, 6.1)
+E2  11  0   VALUE {IF(V(7)>10m,1,0)}
+X1  11  9   DEL 0 VCRES
+C1  9   0   1n
+E3  8   4   VALUE {IF(V(9)>0.63,1,0)}
+G1  G   4   8   4   10m
+C2  2   4   800f
+R1  2   4   10G
+X2  6   4   G   TRIAC Ih=0.28m
+.MODEL  IRLED D (IS=8E-17 N=1.5 RS=2 IKF=7.5E-2 IBV=1.5E-08 NBV=7E1 BV=1.6E1 CJO=4E-11 TT=1E-08 EG=1.46)
+.ENDS MOC3052
+
+*
+.SUBCKT VCRES	1 2	4 5
++PARAMS: R1=1k
+ERES	1	3	VALUE={IF(V(4,5)>0,I(VSENSE)*{R1}*V(4,5),-I(VSENSE)*{R1}*V(4,5))}
+VSENSE	3	2	0
+.ENDS VCRES
+*
+.SUBCKT TRIAC MT2 MT1 G params:
++ Vdrm=600   
++ Igt=5m
++ Ih=0.28m       
++ Rt=3.3
++ Standard=1
+S1  MT2 2   3   0 SW1
+D1  2   4   DAK 
+R1  2   4   1k
+V1  4   MT1 0
+S2  MT2 5   6   0 SW1
+D2  7   5   DAK 
+R2  5   7   1k 
+V2  MT1 7   0 
+R3  G   MT1 1G  
+D3  8   G   DGK 
+D4  G   8   DGK 
+V3  8   MT1 0 
+R4  G   8   1k  
+R5  9   3   2.2  
+C1  0   3   5u 
+E1  9   0   VALUE {IF(((V(10)>0.5)|(V(13)>0.5)|(V(12)>0.5)),400,0)}
+R6  14  6   2.2   
+C2  0   6   5u  
+E2  14  0   VALUE {IF(((V(10)>0.5)|(V(11)>0.5)|(V(12)>0.5)),400,0)}
+E3  15  0   VALUE {IF((ABS(I(V3)))>(Igt-1u),1,0)}
+E4  16  0   VALUE {V(17)*V(15)}
+E5  17  0   VALUE {IF(((I(V3)>(Igt-1u))&((V(MT2)-V(MT1))<0)&(Standard==0)),0,1)}
+X1  16  10  BUFDELAY
+E6  18  0   VALUE {IF(((I(V1))>(Ih/2)),1,0)}
+E7  19  0   VALUE {IF(((I(V1))>(Ih/3)),1,0)} 
+E8  20  0   VALUE {IF((V(18)*V(19)+V(19)*(1-V(18))*(V(21)))>0.5,1,0)}
+C3  21  0   1n  
+R7  20  21  1k  
+R8  21  0   100MEG  
+X2  21  13  BUFDELAY
+E9  22  0   VALUE {IF(((I(V2))>(Ih/2)),1,0)}
+E10 23  0   VALUE {IF(((I(V2))>(Ih/3)),1,0)} 
+E11 24  0   VALUE {IF((V(22)*V(23)+V(23)*(1-V(22))*(V(25)))>0.5,1,0)}
+C4  25  0   1n  
+R9  24  25  1k  
+R10 25  0   100MEG 
+X3  25  11  BUFDELAY
+E12 26  0   VALUE {IF((ABS(V(MT2)-V(MT1))>(Vdrm*1.3)),1,0)}
+E13 27  0   VALUE {IF((I(V1)>(Vdrm*1.3)/5MEG)|(I(V2)>(Vdrm*1.3)/5MEG),1,0)}
+E14 28  0   VALUE {IF((V(26)+(1-V(26))*V(27)*V(29) )>0.5,1,0)}
+C5  29  0   1n  
+R11 28  29  100  
+R12 29  0   100MEG 
+X4  29  12  BUFDELAY
+.MODEL  SW1 VSWITCH (ROFF=1G RON={Rt} VOFF=0 VON=1)
+.MODEL  DAK D(IS=3E-12 N=1.66 CJO=5p) 
+.MODEL  DGK D(IS=1E-16 CJO=50p Rs=5) 
+.ENDS TRIAC
+*
+.SUBCKT BUFDELAY A Y PARAMS:DELAY=1u 
+E1 Y1 0  VALUE {IF(V(A)>0.5,1,0)}
+R1 Y1 Y2 1
+C1 Y2 0  {DELAY*1.44}
+E2 Y3 0  VALUE {IF(V(Y2)>0.5,1,0)}
+R2 Y3 Y  1
+C2 Y  0  1n
+.ENDS BUFDELAY
+*$

library/RC.lib

@@ -0,0 +1,124 @@
+<Qucs Library 25.1.0 "RC">
+
+<Component C>
+  <Description>
+Capacitor with parasitic inductance and ESR. The model contains the generic data. Substitute the ESR and parasitic inductance value after RF measurements before insertion in the schematic!
+  </Description>
+  <Model>
+.Def:RC_C _net0 _net1 Cs="100n" Rs="1" Ls="1n"
+C:C1 _net0 _net2 C="Cs" V=""
+L:L1 _net3 _net1 L="Ls" I=""
+R:R1 _net2 _net3 R="Rs" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT RC_C  gnd _net0 _net1 Cs=100n Rs=1 Ls=1n 
+C1 _net0 _net2  {CS} 
+L1 _net3 _net1  {LS} 
+R1 _net2 _net3  {RS} tc1=0.0 tc2=0.0 
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID -20 14 SUB "1=Cs=100n=Capacitance (F)=" "1=Rs=1=Series resististance ESR (Ohms)=" "1=Ls=1n=Series inductance (H)=">
+    <.PortSym -30 0 1 0 P1>
+    <.PortSym 30 0 2 0 P2>
+    <Line -30 0 26 0 #000080 2 1>
+    <Line -4 -11 0 22 #000080 3 1>
+    <Line 4 -11 0 22 #000080 3 1>
+    <Line 4 0 26 0 #000080 2 1>
+    <Text -20 -40 12 #000000 0 "PAR">
+  </Symbol>
+</Component>
+
+<Component C_ESR>
+  <Description>
+Capacitor with ESR. The model contains the generic data. Substitute the ESR value before insertion in the schematic!
+  </Description>
+  <Model>
+.Def:RC_C_ESR _net0 _net1 Cs="10u" Rs="1"
+R:R1 _net2 _net1 R="Rs" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+C:C1 _net0 _net2 C="Cs" V=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT RC_C_ESR  gnd _net0 _net1 Cs=10u Rs=1 
+R1 _net2 _net1  {RS} tc1=0.0 tc2=0.0 
+C1 _net0 _net2  {CS} 
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID -20 14 X "1=Cs=10u=Series capacitance (F)=" "1=Rs=1=Series resistance ESD (Ohms)=">
+    <.PortSym -30 0 1 0 P1>
+    <.PortSym 30 0 2 0 P2>
+    <Line -30 0 26 0 #000080 2 1>
+    <Line 4 0 26 0 #000080 2 1>
+    <Line -14 -8 6 0 #ff0000 2 1>
+    <Line -4 -11 0 22 #000080 3 1>
+    <EArc 4 -12 20 24 1952 1856 #000080 3 1>
+    <Line -11 -5 0 -6 #ff0000 2 1>
+    <Text -10 -40 12 #000000 0 "ESR">
+  </Symbol>
+</Component>
+
+<Component R>
+  <Description>
+Resistor with parasitic inductance and capacitance. The model contains the generic data. Substitute the parasitics value after RF measurements before insertion in the schematic!
+  </Description>
+  <Model>
+.Def:RC_R _net2 _net1 Rs="1k" Ls="10n" Cp="1p"
+L:L1 _net0 _net1 L="Ls" I=""
+R:R1 _net2 _net0 R="Rs" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+C:C1 _net2 _net1 C="Cp" V=""
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT RC_R  gnd _net2 _net1 Rs=1k Ls=10n Cp=1p 
+L1 _net0 _net1  {LS} 
+R1 _net2 _net0  {RS} tc1=0.0 tc2=0.0 
+C1 _net2 _net1  {CP} 
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 0 12 0 #000080 2 1>
+    <Line 18 0 12 0 #000080 2 1>
+    <Line -18 -9 36 0 #000080 2 1>
+    <Line 18 -9 0 18 #000080 2 1>
+    <Line 18 9 -36 0 #000080 2 1>
+    <Line -18 9 0 -18 #000080 2 1>
+    <.PortSym -30 0 1 0 P1>
+    <.PortSym 30 0 2 0 P2>
+    <.ID -20 14 X "1=Rs=1k=Resistance (Ohms)=" "1=Ls=10n=Series inductance (H)=" "1=Cp=1p=Parallel capacitance (F)=">
+    <Text -20 -30 12 #000000 0 "PAR">
+  </Symbol>
+</Component>
+
+<Component R_L>
+  <Description>
+Resistor with parasitic inductance. The model contains the generic data. Substitute the parasitic inductance value after measurements before insertion in the schematic!
+  </Description>
+  <Model>
+.Def:RC_R_L _net2 _net1 Rs="1k" Ls="10n"
+L:L1 _net0 _net1 L="Ls" I=""
+R:R1 _net2 _net0 R="Rs" Temp="26.85" Tc1="0.0" Tc2="0.0" Tnom="26.85"
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT RC_R_L  gnd _net2 _net1 Rs=1k Ls=10n 
+L1 _net0 _net1  {LS} 
+R1 _net2 _net0  {RS} tc1=0.0 tc2=0.0 
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -30 0 12 0 #000080 2 1>
+    <Line 18 0 12 0 #000080 2 1>
+    <Line -18 -9 36 0 #000080 2 1>
+    <Line 18 -9 0 18 #000080 2 1>
+    <Line 18 9 -36 0 #000080 2 1>
+    <Line -18 9 0 -18 #000080 2 1>
+    <.PortSym -30 0 1 0 P1>
+    <.PortSym 30 0 2 0 P2>
+    <.ID -20 14 X "1=Rs=1k=Resistance (Ohms)=" "1=Ls=10n=Series inductance (H)=">
+    <Text -20 -30 12 #000000 0 "PAR">
+  </Symbol>
+</Component>
+

library/SPICE_TLine.lib

@@ -0,0 +1,205 @@
+<Qucs Library 24.3.2 "SPICE_TLine">
+
+<Component DirectionalCoupler>
+  <Description>
+SPICE ideal directional coupler
+  </Description>
+  <Model>
+.Def:SPICE_TLine_DirectionalCoupler _net0 _net1 _net2 _net3
+Sub:X2 _net0 _net1 _net2 _net3 gnd Type="TLCoupler_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "TLCoupler.cir.lst">
+  <Spice>
+* Ideal Lossless Directional Coupler Model
+* Intusoft
+* NOMINAL IMPEDANCE IS 50 OHMS
+* SCALE RESISTORS R2 THRU R19 LINEARLY FOR ANY OTHER DESIRED IMPEDANCE
+* ANY IMPEDANCE CONNECTED TO THE OUT PORT WILL BE REFLECTED EXACTLY AND APPEAR AT THE IN PORT
+* FWD PORT WILL OUTPUT THE FOWARD TRAVELING VOLTAGE
+* REV PORT WILL OUTPUT THE REVERSE TRAVELING VOLTAGE
+* THIS MODEL FUNCTIONS IN BOTH THE TIME AND FREQUENCY DOMAINS
+*
+* PINOUT ORDER    IN OUT FWD REV
+.SUBCKT ICOUPLER  1  2   3   4
+R02 1 12 100
+R03 12 8 323.6
+R04 8 0 100
+R05 1 7 100
+R06 7 9 323.6
+R07 2 9 100
+R08 9 11 323.6
+R09 11 0 100
+R10 2 10 100
+R11 10 12 323.6
+R12 12 13 100
+R13 12 15 323.6
+R14 15 0 100
+R15 13 14 100
+R16 14 16 323.6
+R17 13 0 50
+R18 4 0 1E6
+R19 3 0 1E6
+* VCVS
+E1 9 0 8 7 100E3
+E2 12 0 11 10 100E3
+E3 16 0 15 14 100E3
+E4 4 0 13 0 -1
+E5 3 0 2 4 1
+.ENDS ICOUPLER
+
+.SUBCKT SPICE_TLine_DirectionalCoupler  gnd _net0 _net1 _net2 _net3 
+X2 _net0 _net1 _net2 _net3 ICOUPLER
+.ENDS
+  </Spice>
+  <Symbol>
+    <Line -20 -30 40 0 #000080 2 1>
+    <Line -20 30 40 0 #000080 2 1>
+    <Line 9 14 5 0 #800000 2 1>
+    <Line -14 14 5 0 #800000 2 1>
+    <Line -14 14 0 -5 #800000 2 1>
+    <Line 14 14 0 -5 #800000 2 1>
+    <Line 12 -12 -24 24 #800000 2 1>
+    <Line -12 -12 24 24 #800000 2 1>
+    <Line -20 -30 0 60 #000080 2 1>
+    <Line -30 20 10 0 #000080 2 1>
+    <Line -30 -20 10 0 #000080 2 1>
+    <Line 30 20 -10 0 #000080 2 1>
+    <Line 20 -30 0 60 #000080 2 1>
+    <Line -14 -14 5 0 #800000 2 1>
+    <Line 9 -14 5 0 #800000 2 1>
+    <Line -14 -9 0 -5 #800000 2 1>
+    <Line 14 -9 0 -5 #800000 2 1>
+    <Text -16 15 6 #000000 0 "R">
+    <Text 11 -26 6 #000000 0 "O">
+    <Text -15 -26 6 #000000 0 "I">
+    <Line 30 -20 -10 0 #000080 2 1>
+    <.PortSym -30 -20 1 0 IN>
+    <.PortSym -30 20 4 0 REV>
+    <.PortSym 30 20 3 180 FWD>
+    <.PortSym 30 -20 2 180 OUT>
+    <Text 10 15 6 #000000 0 "F">
+    <.ID -15 32 DC>
+    <Text -16 -41 6 #000000 0 "LOSSLESS">
+  </Symbol>
+</Component>
+
+<Component TL_Hybrid_90>
+  <Description>
+SPICE hybrid quadrature coupler
+  </Description>
+  <Model>
+.Def:SPICE_TLine_TL_Hybrid_90 _net0 _net1 _net2 _net3 F="1 GHz"
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT SPICE_TLine_TL_Hybrid_90  gnd _net0 _net1 _net2 _net3 F=1 GHz 
+T3 _net0 0 _net2 0 Z0=35.4 F={F} NL=0.25 IC=0, 0, 0, 0 
+T2 _net2 0 _net3 0 Z0=50 F={F} NL=0.25 IC=0, 0, 0, 0 
+T1 _net1 0 _net0 0 Z0=50 F={F} NL=0.25 IC=0, 0, 0, 0 
+T4 _net3 0 _net1 0 Z0=35.4 F={F} NL=0.25 IC=0, 0, 0, 0 
+.ENDS
+  </Spice>
+  <Symbol>
+    <.PortSym -30 20 2 0 ISO>
+    <.PortSym 30 20 4 180 O_90>
+    <.PortSym -30 -20 1 0 IN>
+    <.PortSym 30 -20 3 180 O_0>
+    <Line -20 -30 40 0 #000080 2 1>
+    <Line -20 30 40 0 #000080 2 1>
+    <Line 9 14 5 0 #800000 2 1>
+    <Line -14 14 5 0 #800000 2 1>
+    <Line -14 14 0 -5 #800000 2 1>
+    <Line 14 14 0 -5 #800000 2 1>
+    <Line 12 -12 -24 24 #800000 2 1>
+    <Line -12 -12 24 24 #800000 2 1>
+    <Line -20 -30 0 60 #000080 2 1>
+    <Line -30 20 10 0 #000080 2 1>
+    <Line -30 -20 10 0 #000080 2 1>
+    <Line 30 -20 -10 0 #000080 2 1>
+    <Line 30 20 -10 0 #000080 2 1>
+    <Line 20 -30 0 60 #000080 2 1>
+    <Line -14 -14 5 0 #800000 2 1>
+    <Line 9 -14 5 0 #800000 2 1>
+    <Line -14 -9 0 -5 #800000 2 1>
+    <Line 14 -9 0 -5 #800000 2 1>
+    <Text -16 15 6 #000000 0 "ISO">
+    <Text 8 15 6 #000000 0 "90">
+    <Text 11 -26 6 #000000 0 "0">
+    <Text -15 -26 6 #000000 0 "I">
+    <.ID -15 34 HYB "1=F=1 GHz=Center Frequency=">
+  </Symbol>
+</Component>
+
+<Component TLine_NL>
+  <Description>
+Transmission line defined using Z0, frequency, and length (in wavelength)
+  </Description>
+  <Model>
+.Def:SPICE_TLine_TLine_NL _net0 _net2 _net1 _net3 Z0="50" F="1e9" NL="0.25"
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT SPICE_TLine_TLine_NL  gnd _net0 _net2 _net1 _net3 Z0=50 F=1e9 NL=0.25 
+T1 _net0 _net2 _net1 _net3 Z0={Z0} F={F} NL={NL} IC=0, 0, 0, 0 
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID -10 24 TL "1=Z0=50=Z0=" "1=F=1e9=Frequency=" "1=NL=0.25=Nominal Length=">
+    <Ellipse 5 -10 10 20 #800000 2 1 #c0c0c0 1 0>
+    <Line 20 0 -10 0 #800000 2 1>
+    <Line 20 0 10 0 #000080 2 1>
+    <Line 10 20 0 -10 #800000 2 1>
+    <Line 20 20 -10 0 #800000 2 1>
+    <Line 30 20 -10 0 #000080 2 1>
+    <.PortSym 30 0 4 180 P4>
+    <.PortSym 30 20 3 180 P3>
+    <Ellipse -15 -10 10 20 #800000 2 1 #c0c0c0 1 0>
+    <Line -20 0 10 0 #800000 2 1>
+    <Line -30 0 10 0 #000080 2 1>
+    <Line -10 20 0 -10 #800000 2 1>
+    <Line -30 20 10 0 #000080 2 1>
+    <Line -10 20 -10 0 #800000 2 1>
+    <.PortSym -30 20 2 0 P2>
+    <.PortSym -30 0 1 0 P1>
+    <Line -10 -10 20 0 #800000 2 1>
+    <Line -10 10 20 0 #800000 2 1>
+  </Symbol>
+</Component>
+
+<Component TLine_TD>
+  <Description>
+Transmission line defined using Z0 and time delay
+  </Description>
+  <Model>
+.Def:SPICE_TLine_TLine_TD _net0 _net2 _net1 _net3 Z0="50" Td="0"
+.Def:End
+  </Model>
+  <Spice>
+.SUBCKT SPICE_TLine_TLine_TD  gnd _net0 _net2 _net1 _net3 Z0=50 Td=0 
+T1 _net0 _net2 _net1 _net3 Z0={Z0} Td={TD} F=0 NL=0 IC=0, 0, 0, 0 
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID -10 24 TL "1=Z0=50=Z0=" "1=Td=0=Time Delay=">
+    <.PortSym 30 0 4 180 P4>
+    <.PortSym 30 20 3 180 P3>
+    <.PortSym -30 20 2 0 P2>
+    <.PortSym -30 0 1 0 P1>
+    <Ellipse 5 -10 10 20 #800000 2 1 #c0c0c0 1 0>
+    <Line 20 0 -10 0 #800000 2 1>
+    <Line 20 0 10 0 #000080 2 1>
+    <Line 10 20 0 -10 #800000 2 1>
+    <Line 20 20 -10 0 #800000 2 1>
+    <Line 30 20 -10 0 #000080 2 1>
+    <Ellipse -15 -10 10 20 #800000 2 1 #c0c0c0 1 0>
+    <Line -20 0 10 0 #800000 2 1>
+    <Line -30 0 10 0 #000080 2 1>
+    <Line -10 20 0 -10 #800000 2 1>
+    <Line -30 20 10 0 #000080 2 1>
+    <Line -10 20 -10 0 #800000 2 1>
+    <Line -10 -10 20 0 #800000 2 1>
+    <Line -10 10 20 0 #800000 2 1>
+  </Symbol>
+</Component>
+

library/Thyristor.lib

@@ -333,3 +333,158 @@ X1 _net0 _net1 _net2 XS8020L
   </Symbol>
 </Component>
 
+<Component TriacGeneric>
+  <Description>
+Generic triac model from ST microelectronics. This model works only with LTSpice compatibility option:
+============================
+* Vdrm : Repetitive forward off-state voltage
+* Ih   : Holding current 
+* Igt  : Gate trigger current 
+* Rt   : Dynamic on-state resistance
+* Standard : Differenciation between Snubberless and Standard TRIACs
+* (Standard=0 => Snubberless TRIACs, Standard=1 => Standard TRIACs)
+  </Description>
+  <Model>
+.Def:Thyristor_TriacGeneric _net0 _net1 _net2 Vdrm="400" Igt="20m" Ih="6m" Rt="0.10" Standard="1"
+Sub:X1 _net0 _net2 _net1 gnd Type="TriacST_orig_cir"
+.Def:End
+  </Model>
+  <ModelIncludes "TriacST_orig.cir.lst">
+  <Spice>
+.subckt Triac_ST A K G PARAMS:
++ Vdrm=400v     
++ Igt=20ma
++ Ih=6ma        
++ Rt=0.01
++ Standard=1
+*
+* Vdrm : Repetitive forward off-state voltage
+* Ih   : Holding current 
+* Igt  : Gate trigger current 
+* Rt   : Dynamic on-state resistance
+* Standard : Differenciation between Snubberless and Standard TRIACs
+* (Standard=0 => Snubberless TRIACs, Standard=1 => Standard TRIACs)
+*
+****************************
+* Power circuit *
+****************************
+*
+****************************
+*Switch circuit*
+****************************
+* Q1 & Q2 Conduction
+S_S3           A Plip1 positive 0 Smain
+*RS_S3         positive 0 1G
+D_DAK1         Plip1 Plip2 Dak 
+R_Rlip         Plip1 Plip2  1k
+V_Viak         Plip2 K DC 0 AC 0 
+*
+* Q3 & Q4 Conduction
+S_S4           A Plin1 negative 0 Smain
+*RS_S4         negative 0 1G
+D_DKA1         Plin2 Plin1 Dak 
+R_Rlin         Plin1 Plin2  1k 
+V_Vika         K Plin2 DC 0 AC 0  
+****************************
+*Gate circuit*
+****************************
+R_Rgk          G K  10G  
+D_DGKi         Pg2 G Dgk 
+D_DGKd         G Pg2 Dgk 
+V_Vig          Pg2 K DC 0 AC 0 
+R_Rlig         G Pg2  1k  
+*
+****************************
+*Interface circuit*
+****************************
+* positive pilot
+R_Rp              Controlp positive  2.2  
+C_Cp              0 positive  1u 
+E_IF15OR3         Controlp 0 VALUE {IF(  ( (V(CMDIG)>0.5) | (V(CMDILIH)>0.5) | (V(CMDVdrm)>0.5) ),400,0 )}
+* 
+* negative pilot
+R_Rn              Controln negative  2.2   
+C_Cn              0 negative  1u  
+E_IF14OR3         Controln 0 VALUE {IF(  ( (V(CMDIG)>0.5) | (V(CMDILIHN)>0.5) |  (V(CMDVdrm)>0.5) ),400,0 )}
+*
+****************************
+* Pilots circuit *
+****************************
+****************************
+* Pilot Gate     *
+****************************
+E_IF1IG             inIG 0 VALUE {IF(  ( ABS(I(V_Vig)) ) > (Igt-1u) ,1,0 )}
+E_MULT2MULT         CMDIG 0 VALUE {V(Q4)*V(inIG)}
+E_IF2Quadrant4      Q4 0 VALUE {IF(((I(V_Vig)>(Igt-0.000001))&((V(A)-V(K))<0)&(Standard==0)),0,1)}
+*
+****************************
+* Pilot IHIL     *
+****************************
+*
+E_IF10IL         inIL 0 VALUE {IF( ((I(V_Viak))>(Ih/2)),1,0 )}
+E_IF5IH          inIH 0 VALUE {IF( ((I(V_Viak))>(Ih/3)),1,0 )} 
+*
+* Flip_flop IHIL
+E_IF6DIHIL         SDIHIL 0 VALUE {IF((V(inIL)*V(inIH)+V(inIH)*(1-V(inIL))*(V(CMDILIH)) )>0.5,1,0)}
+C_CIHIL            CMDILIH 0  1n  
+R_RIHIL            SDIHIL CMDILIH  1K  
+R_RIHIL2           CMDILIH 0  100Meg  
+*
+****************************
+* Pilot IHILN    *
+****************************
+*
+E_IF11ILn           inILn 0 VALUE {IF( ((I(V_Vika))>(Ih/2)),1,0 )}
+E_IF3IHn            inIHn 0 VALUE {IF( ((I(V_Vika))>(Ih/3)),1,0 )} 
+* Flip_flop IHILn
+E_IF4DIHILN         SDIHILN 0 VALUE {IF((V(inILn)*V(inIHn)+V(inIHn)*(1-V(inILn))*(V(CMDILIHN)) )>0.5,1,0)}
+C_CIHILn            CMDILIHN 0  1n  
+R_RIHILn            SDIHILN CMDILIHN  1K  
+R_RIHILn2           CMDILIHN 0  100Meg  
+*
+****************************
+* Pilot VDRM     *
+****************************
+E_IF8Vdrm           inVdrm 0 VALUE {IF( (ABS(V(A)-V(K))>(Vdrm*1.3)),1,0 )}
+E_IF9IHVDRM         inIhVdrm 0 VALUE {IF( (I(V_Viak)>(Vdrm*1.3)/1.2meg)| (I(V_Vika)>(Vdrm*1.3)/1.2meg),1,0)}
+* Flip_flop VDRM
+E_IF7DVDRM          SDVDRM 0 VALUE {IF((V(inVdrm)+(1-V(inVdrm))*V(inIhVdrm)*V(CMDVdrm) )>0.5,1,0)}
+C_CVdrm             CMDVdrm 0  1n  
+R_RVdrm             SDVDRM CMDVdrm  100  
+R_RVdrm2            CMDVdrm 0  100Meg  
+*
+****************************
+* Switch Model *
+****************************
+.MODEL Smain VSWITCH Roff=1.2meg Ron={Rt} Voff=0 Von=100
+****************
+* Diodes Model *
+****************
+.MODEL  Dak D( Is=3E-12 Cjo=5pf) 
+.MODEL  Dgk D( Is=1E-16 Cjo=50pf Rs=5) 
+.ends 
+
+
+.SUBCKT Thyristor_TriacGeneric  gnd _net0 _net1 _net2 Vdrm=400 Igt=20m Ih=6m Rt=0.10 Standard=1 
+X1 _net0 _net2 _net1 Triac_ST Vdrm={Vdrm} Igt={Igt} Ih={Ih} Rt={Rt} Standard={Standard}
+.ENDS
+  </Spice>
+  <Symbol>
+    <.ID -20 44 SUB "1=Vdrm=400=Repetitive forward off-state voltage=" "1=Igt=20m=Gate trigger current =" "1=Ih=6m=Holding current =" "1=Rt=0.10=Dynamic on-state resistance=" "1=Standard=1=0 -- Snubberless TRIACs;1 -- Standard TRIACs=">
+    <.PortSym 0 -30 1 0 P1>
+    <Line 0 6 0 24 #000080 2 1>
+    <Line 0 -30 0 24 #000080 2 1>
+    <Line 18 6 -36 0 #000080 2 1>
+    <Line -30 10 17 0 #000080 2 1>
+    <Line -13 10 4 -4 #000080 2 1>
+    <Line -9 6 -9 -12 #000080 2 1>
+    <Line -9 6 9 -12 #000080 2 1>
+    <Line 9 -6 9 12 #000080 2 1>
+    <Line 9 -6 -9 12 #000080 2 1>
+    <Line 18 -6 -36 0 #000080 2 1>
+    <.PortSym 0 30 3 0 P3>
+    <.PortSym -30 10 2 0 P2>
+  </Symbol>
+</Component>
+
+

library/TubesExtended/2P2.CIR

@@ -0,0 +1,27 @@
+* 2P2 Miniature Power Pentode Spice Model
+* Author: Zabb Csaba
+* Date:   4/12/2021
+* The following parameters are not modelled:
+*   (1) Filament and filament warmup time
+*   (2) Limiting values
+* This model is valid for the following tubes (within max. ratings):
+*   DL92, 3S4, CV484, VT-174
+.SUBCKT 2P2 A S G K 
++ PARAMS: MU=5.5 KG1=3916 KP=39.04 KVB=12 VCT=0.0025 EX=1.19 KG2=6384 KNEE=2.88 KVC=2.133
++ KLAM=2.75E-7 KLAMG=6.12E-4 KNEE2=11.76 KNEX=2.85
+E1  1 0  VALUE={V(S,K)/KP*LOG(1+EXP((1/MU+(VCT+V(G,K))/SQRT(KVB+V(S,K)*V(S,K)))*KP))}
+E2  2 0  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))}
+G4  A K  VALUE={IF(V(A,K)>0,V(2)/KG1*ATAN((V(A,K)+KNEX)/KNEE)*TANH(V(A,K)/KNEE2)*(1+KLAMG*V(A,K)),0)}
+E4  4 K  VALUE={IF(V(A,K)>0,V(A,K),0)}
+G2  S K  VALUE={V(2)/KG2*(KVC-ATAN((V(4,K)+KNEX)/KNEE)*TANH(V(4,K)/KNEE2))/(1+KLAMG*V(4,K))}
+B1  G K  I=URAMP(V(G,K)+8.68E-1)^1.5*2.1E-5*V(5)
+G3  G K  VALUE={3.1E-5*(PWR(V(G,K),1.5)+PWRS(V(G,K),1.5))/1.5} ; G1 diode
+E3  3 0  VALUE={IF(V(S,K)>0,1/(1+ABS(V(S,K))/20)^2.5,1)} ;G1 Splash current change
+E5  5 0  VALUE={IF(V(A,K)>=3,V(3),1)}
+R1  3 0  1G
+R2  5 0  1G
+C1  G K  4.4p
+C2  G A  0.4p
+C3  A K  6p 
+.ENDS
+*$

library/TubesExtended/2P3.CIR

@@ -0,0 +1,29 @@
+* 2P3 Miniature Power Pentode Spice Model
+* Author: Zabb Csaba
+* Date: 25/02/2023
+* The following parameters are not modelled:
+*   (1) Filament and filament warmup time
+*   (2) Limiting values
+* 2P3 maximum ratings:
+* Ua  max. 150V
+* Ug2 max. 135V
+* Ik  max. 25mA
+* Uf  1.4V
+* If  200mA
+* The cathode symbol is the negative end of the filament (pin 5, parallel filament).
+.SUBCKT 2P3 A S G K 
++ PARAMS: MU=5.2 KG1=5535 KP=60.06 KVB=12.96 VCT=0.274 EX=1.4 KG2=6852 KNEE=12 KVC=1.874
++ KLAMG=5.61E-4 KNEE2=21.41 KNEX=26.4  
+E1  1 0  VALUE={V(S,K)/KP*LOG(1+EXP((1/MU+(VCT+V(G,K))/SQRT(KVB+V(S,K)*V(S,K)))*KP))}
+E2  2 0  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))}
+G1  A K  VALUE={IF(V(A,K)>0,V(2)/KG1*ATAN((V(A,K)+KNEX)/KNEE)*TANH(V(A,K)/KNEE2)*(1+KLAMG*V(A,K)),0)}
+E3  4 K  VALUE={IF(V(A,K)>0,V(A,K),0)}
+G2  S K  VALUE={V(2)/KG2*(KVC-ATAN((V(4,K)+KNEX)/KNEE)*TANH(V(4,K)/KNEE2))/(1+KLAMG*V(4,K))}
+B1  G K  I=URAMP(V(G,K)+960m)^1.5*5.3E-5
+G3  G K  VALUE={3.1E-5*(PWR(V(G,K),1.5)+PWRS(V(G,K),1.5))/1.5} ; G1 diode
+C1  K G  4.8p  
+C2  G A  0.36p
+C3  K A  4.2p 
+.ENDS 2P3
+*
+

library/TubesExtended/5899.CIR

@@ -0,0 +1,22 @@
+* 5899 Special Quality Variable-mu Pentode Spice Model
+* Author: Zabb Csaba
+* Date:   30/10/2021
+* The following parameters are not modelled:
+*   (1) Filament and filament warmup time
+*   (2) Limiting values
+.SUBCKT 5899 A S G K 
++ PARAMS: MU=27.2 KG1=11545.6 KP=35.3 KVB=11.88 VCT=8.438E-5 EX=2.64 KG2=7324 KNEE=7.44 KVC=1.772
++ KLAM=3E-8 KLAMG=2.04E-4 KNEE2=15.64 KNEX=10.8   
+E1  1 0  VALUE={V(S,K)/KP*LOG(1+EXP((1/MU+(VCT+V(G,K)*V(3))/SQRT(KVB+V(S,K)*V(S,K)))*KP))}
+E2  2 0  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))}
+G1  A K  VALUE={IF(V(A,K)>0,V(2)/KG1*ATAN((V(A,K)+KNEX)/KNEE)*TANH(V(A,K)/KNEE2)*(1+KLAMG*V(A,K)),0)}
+E4  4 K  VALUE={IF(V(A,K)>0,V(A,K),0)}
+G2  S K  VALUE={V(2)/KG2*(KVC-ATAN((V(4,K)+KNEX)/KNEE)*TANH(V(4,K)/KNEE2))/(1+KLAMG*V(4,K))}
+G3  G K  VALUE={2.16E-3*(PWR(V(G,K),1.5)+PWRS(V(G,K),1.5))/2} ; G1 diode
+E3  3 0  VALUE={IF(V(G,K)<0,(1-EXP(10/V(G,K)))^1.3,1)}
+B1  G K  I=URAMP(V(G,K)+8.56E-1)^1.5*2.6E-4
+C1  G K  4p
+C2  A K  1.9p
+C3  A G  0.03p
+.ENDS 5899
+*$

library/TubesExtended/6F12P.CIR

@@ -0,0 +1,38 @@
+* 6F12P Triode-Pentode Spice Model
+* Author: Zabb Csaba
+* Date:   27/10/2021
+* The following parameters are not modelled:
+*   (1) Filament and filament warmup time
+*   (2) Limiting values
+.SUBCKT 6F12P A S G K 
++ PARAMS: MU=66.4 KG1=352 KP=423.45 KVB=5.64 VCT=6.25E-4 EX=1.596 KG2=672 KNEE=1.14 KVC=2.07
++ KLAM=2.5E-8 KLAMG=3.637E-5 KNEE2=14.56 KNEX=2.1 
+E1  1 0  VALUE={V(S,K)/KP*LOG(1+EXP((1/MU+(VCT+V(G,K))/SQRT(KVB+V(S,K)*V(S,K)))*KP))}
+E2  2 0  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))}
+G4  A K  VALUE={IF(V(A,K)>0,V(2)/KG1*ATAN((V(A,K)+KNEX)/KNEE)*TANH(V(A,K)/KNEE2)*(1+KLAMG*V(A,K)),0)}
+E4  4 K  VALUE={IF(V(A,K)>0,V(A,K),0)}
+G2  S K  VALUE={V(2)/KG2*(KVC-ATAN((V(4,K)+KNEX)/KNEE)*TANH(V(4,K)/KNEE2))/(1+KLAMG*V(4,K))}
+G3  G K  VALUE={2.1E-2*(PWR(V(G,K),1.5)+PWRS(V(G,K),1.5))/2} ; G1 diode
+B1  G K  I=URAMP(V(G,K)+1.045)^1.5*3.2E-4*V(3)
+B2  G K  I=URAMP(V(G,K)+1.045)^1.5*9.5E-5  
+E3  3 0  VALUE={IF(V(S,K)>0,1/(1+ABS(V(S,K))/20)^1.8,1)} ;G1 Splash current change
+R1  3 0  1G
+C1  K G  6.6p 
+C2  G A  0.02p
+C3  K A  1.9p
+.ENDS
+*$
+.SUBCKT 6F12PT A G K 
++PARAMS: MU=101 KG1=161.7 KP=691.2 KVB=69.96 VCT=0.1786 EX=1.44 
+E1  1 0  VALUE={V(A,K)/KP*LOG(1+EXP(KP*(1/MU+(VCT+V(G,K))/SQRT(KVB+V(A,K)*V(A,K)))))} 
+G1  A K  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))/KG1} 
+G3  G K  VALUE={3.5E-2*(PWR(V(G,K),1.5)+PWRS(V(G,K),1.5))/2} ; G1 diode
+B1  G K  I=URAMP(V(G,K)+1.05)^1.5*4.6E-4*V(3) 
+B2  G K  I=URAMP(V(G,K)+1.05)^1.5*7E-5  
+E3  3 0  VALUE={IF(V(A,K)>0,1/(1+ABS(V(A,K))/20)^2,1)} ;G1 Splash current change
+R1  3 0  1G
+C1  G K  2.1p
+C2  A K  0.26p
+C3  G A  1.6p
+.ENDS 
+*$

library/TubesExtended/6K1J.CIR

@@ -0,0 +1,25 @@
+* 6K1J Variable-mu VHF Pentode Spice Model
+* Author: Zabb Csaba
+* Date:   6/11/2021
+* The following parameters are not modelled:
+*   (1) Filament and filament warmup time
+*   (2) Limiting values
+* This model is valid for the following tubes (within max. ratings):
+* RCA 956, VT-238, E2F
+.SUBCKT 6K1J A S G K 
++ PARAMS: MU=19.2 KG1=95744 KP=12.95 KVB=5.76 VCT=0.0575 EX=2.828 KG2=120960 KNEE=14.4 KVC=2.339
++ KLAM=2.5E-8 KLAMG=7.8E-5 KNEE2=13.39 KNEX=11.1  
+E1 1 0  VALUE={V(S,K)/KP*LOG(1+EXP((1/MU+(VCT+V(G,K)*V(3))/SQRT(KVB+V(S,K)*V(S,K)))*KP))}
+E3 3 0  VALUE={ATAN(V(G,K)/19+1)/2.7+0.5}
+E2 2 0  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))}
+G1 A K  VALUE={IF(V(A,K)>0,0.831*V(2)/KG1*ATAN((V(A,K)+KNEX)/KNEE)*TANH(V(A,K)/KNEE2)*(1+KLAMG*V(A,K)),0)}
+E4 4 K  VALUE={IF(V(A,K)>0,V(A,K),0)}
+G2 S K  VALUE={0.822*V(2)/KG2*(KVC-ATAN((V(4,K)+KNEX)/KNEE)*TANH(V(4,K)/KNEE2))/(1+KLAMG*V(4,K))}
+B1 G K  I=URAMP(V(G,K)+1.15)^1.5*2.6E-4*V(5)
+E5 5 0  VALUE={IF(V(S,K)>0,1/(1+ABS(V(S,K))/20)^1.3,1)} ;G1 Splash current change
+R1 5 0  1G
+C1 G K  3.4p
+C2 A K  3p
+C3 G A  0.007p
+.ENDS
+*$

library/TubesExtended/EF183.CIR

@@ -0,0 +1,25 @@
+* EF183 Variable-mu Pentode Spice Model
+* Author: Zabb Csaba
+* Date:   26/10/2021
+* The following parameters are not modelled:
+*   (1) Filament and filament warmup time
+*   (2) Limiting values
+.SUBCKT EF183 A S G K 
++ PARAMS: MU=45.58 KG1=126.5 KP=141.9 KVB=12 VCT=6.25E-4 EX=1.008 KG2=258 KNEE=7.92 KVC=2.82
++ KLAM=2E-7 KLAMG=9.9E-5 KNEE2=7.963 KNEX=2.756  
+E1  1 0  VALUE={V(S,K)/KP*LOG(1+EXP((1/MU+(VCT+V(G,K)*V(3))/SQRT(KVB+V(S,K)*V(S,K)))*KP))}
+E2  2 0  VALUE={(PWR(V(1),EX)+PWRS(V(1),EX))}
+G1  A K  VALUE={IF(V(A,K)>0,V(2)/KG1*ATAN((V(A,K)+KNEX)/KNEE)*TANH(V(A,K)/KNEE2)*(1+KLAMG*V(A,K)),0)}
+E4  4 K  VALUE={IF(V(A,K)>0,V(A,K),0)}
+G2  S K  VALUE={V(2)/KG2*(KVC-ATAN((V(4,K)+KNEX)/KNEE)*TANH(V(4,K)/KNEE2))/(1+KLAMG*V(4,K))}
+G3  G K  VALUE={3.16E-2*(PWR(V(G,K),1.5)+PWRS(V(G,K),1.5))/2} ; G1 diode
+E3  3 0  VALUE={IF(V(G,K)<0,(1-EXP(14/V(G,K)))^1.3,1)}
+B1  G K  I=URAMP(V(G,K)+1.015)^1.5*5.1E-4*V(6)
+B2  G K  I=URAMP(V(G,K)+1.015)^1.5*2E-4  
+E5  5 0  VALUE={IF(V(S,K)>0,1/(1+ABS(V(S,K))/20)^2,1)} ;G1 Splash current change
+E6  6 0  VALUE={IF(V(A,K)>=15,V(5),1)}
+C1  G K  9p
+C2  A K  3p
+C3  A G  0.005p
+.ENDS EF183
+*$

library/TubesExtended/EF184.cir

@@ -0,0 +1,32 @@
+* EF184 Pentode Spice Model
+* Copyright 2003--2006 by Ayumi Nakabayashi, All rights reserved.
+* Version 3.01, Generated on Wed Mar 22 17:19:41 2006
+* -Ig1 splash current modified by Zabb Csaba 21/10/2021
+.SUBCKT EF184 A G2 G1 K
+BGG   GG   0  V=V(G1,K)+0.40321166
+BEP   EP   0  V=URAMP(V(A,K))+1e-10
+BEG   EG   0  V=URAMP(V(G1,K))+1e-10
+BEG2  EG2  0  V=URAMP(V(G2,K))+1e-10
+BM1   M1   0  V=(0.0054275937*(URAMP(V(EG2)-1e-10)+1e-10))^-0.61801526
+BM2   M2   0  V=(0.7082102*(URAMP(V(GG)+V(EG2)/53.760436)+1e-10))^2.1180153
+BP    P    0  V=0.019963362*(URAMP(V(GG)+V(EG2)/75.910283)+1e-10)^1.5
+BIK   IK   0  V=U(V(GG))*V(P)+(1-U(V(GG)))*0.011540933*V(M1)*V(M2)
+BIG   IG   0  V=0.0099816812*V(EG)^1.5*(V(EG)/(V(EP)+V(EG))*1.2+0.4)
+BIK2  IK2  0  V=V(IK,IG)*(1-0.4*(EXP(-V(EP)/V(EG2)*15)-EXP(-15)))
+BIG2T IG2T 0  V=V(IK2)*(0.71666698*(1-V(EP)/(V(EP)+10))^1.5+0.28333302)
+BIK3  IK3  0  V=V(IK2)*(V(EP)+5500)/(V(EG2)+5500)
+BIK4  IK4  0  V=V(IK3)-URAMP(V(IK3)-(0.010377457*(V(EP)+URAMP(V(EG2,EP)))^1.5))
+BIP   IP   0  V=URAMP(V(IK4,IG2T)-URAMP(V(IK4,IG2T)-(0.010377457*V(EP)^1.5)))
+BIAK  A    K  I=V(IP)+1e-10*V(A,K)
+BIG2  G2   K  I=URAMP(V(IK4,IP))
+B1    G1   K  I=URAMP(V(G1,K)+1.3)^1.5*4.3E-4*V(3)
+G3    G1   K  VALUE={9.516E-3*(PWR(V(G1,K),1.5)+PWRS(V(G1,K),1.5))/2} ; G1 diode
+E3    3    0  VALUE={IF(V(G2,K)>0,1/(1+ABS(V(G2,K))/20)^1.3,1)} ;G1 Splash current change
+E5    5    0  VALUE={IF(V(A,K)>=8,V(3),1)}
+R1    3    0  1G
+R2    5    0  1G
+CGA   G1   A  0.005p
+CGK   G1   K  7.2p
+C12   G1   G2 2.8p
+CAK   A    K  3p
+.ENDS

library/XyceDigital/A2DBRIDGE.sym

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library/XyceDigital/A2DBRIDGEX2.sym

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library/XyceDigital/A2DBRIDGEX4.sym

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library/XyceDigital/A2DBRIDGEX8.sym

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library/XyceDigital/AND2.sym

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library/XyceDigital/AND4.sym

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library/XyceDigital/ANDOR4X2.sym

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library/XyceDigital/BUF.sym

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library/XyceDigital/D2ABRIDGE.sym

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library/XyceDigital/D2ABRIDGEX2.sym

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library/XyceDigital/D2ABRIDGEX4.sym

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library/XyceDigital/D2ABRIDGEX8.sym

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library/XyceDigital/FADDER.sym

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library/XyceDigital/GEN0OR1X4.sym

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library/XyceDigital/GEN0OR1X8.sym

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library/XyceDigital/INV.sym

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library/XyceDigital/LOGIC0.sym

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library/XyceDigital/LOGIC1.sym

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library/XyceDigital/MUX2TO1.sym

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-  <Line -80 20 20 0 #000080 2 1>
-  <.PortSym -80 20 3 0>
-  <Line -80 40 20 0 #000080 2 1>
-  <.PortSym -80 40 4 0>
-  <Text -57 -13 12 #005500 0 "G">
-  <Text -57 -33 12 #005500 0 "En">
-  <Text -58 8 12 #005500 0 "D0">
-  <Text -58 27 12 #005500 0 "D1">
-  <Line 40 10 20 0 #000080 2 1>
-  <.PortSym 60 10 5 180>
-  <Text 23 0 12 #005500 0 "Z">
-  <.ID -61 76 X>
+  <Rectangle -50 -70 100 130 #005500 3 1 #c0c0c0 1 0>
+  <Text -18 -67 12 #005500 0 "MUX">
+  <Ellipse -60 -35 10 10 #00007f 3 1 #c0c0c0 1 0>
+  <Line -70 -30 10 0 #000080 2 1>
+  <.PortSym -70 -30 1 0 >
+  <Line -70 -10 20 0 #000080 2 1>
+  <.PortSym -70 -10 2 0 >
+  <Line -70 10 20 0 #000080 2 1>
+  <.PortSym -70 10 3 0 >
+  <Line -70 30 20 0 #000080 2 1>
+  <.PortSym -70 30 4 0 >
+  <Text -47 -23 12 #005500 0 "G">
+  <Text -47 -43 12 #005500 0 "En">
+  <Text -48 -2 12 #005500 0 "D0">
+  <Text -48 17 12 #005500 0 "D1">
+  <Line 50 0 20 0 #000080 2 1>
+  <.PortSym 70 0 5 180 >
+  <Text 33 -10 12 #005500 0 "Z">
+  <.ID -51 66 X>
 </Symbol>
-

library/XyceDigital/MUX4TO1.sym

@@ -1,31 +1,31 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Rectangle -40 -80 90 200 #005500 3 1 #c0c0c0 1 0>
-  <Text -13 -78 12 #005500 0 "MUX">
-  <Line -80 -40 25 0 #000080 2 1>
-  <Ellipse -55 -48 15 15 #005500 3 1 #c0c0c0 1 0>
-  <.PortSym -80 -40 1 0>
-  <Text -36 -52 12 #005500 0 "En">
-  <Line -80 -20 40 0 #000080 2 1>
-  <Text -35 -32 12 #005500 0 "G0">
-  <.PortSym -80 -20 2 0>
-  <Line -80 0 40 0 #000080 2 1>
-  <Line -80 20 40 0 #000080 2 1>
-  <.PortSym -80 0 3 0>
-  <.PortSym -80 20 4 0>
-  <Text -36 -12 12 #005500 0 "G1">
-  <Text -36 9 12 #005500 0 "D0">
-  <Line -80 40 40 0 #000080 2 1>
-  <.PortSym -80 40 5 0>
-  <Text -36 26 12 #005500 0 "D1">
-  <Line -80 60 40 0 #000080 2 1>
-  <.PortSym -80 60 6 0>
-  <Line -80 80 40 0 #000080 2 1>
-  <.PortSym -80 80 7 0>
-  <Text -36 49 12 #005500 0 "D2">
-  <Text -36 70 12 #005500 0 "D3">
-  <Line 50 20 30 0 #000080 2 1>
-  <Text 34 9 14 #005500 0 "Z">
-  <.PortSym 80 20 8 180>
-  <.ID -30 124 X>
+  <Rectangle -50 -100 90 200 #005500 3 1 #c0c0c0 1 0>
+  <Text -23 -98 12 #005500 0 "MUX">
+  <Line -80 -60 15 0 #000080 2 1>
+  <Ellipse -65 -68 15 15 #005500 3 1 #c0c0c0 1 0>
+  <Text -46 -72 12 #005500 0 "En">
+  <Line -80 -40 30 0 #000080 2 1>
+  <Text -45 -52 12 #005500 0 "G0">
+  <Line -80 -20 30 0 #000080 2 1>
+  <Line -80 0 30 0 #000080 2 1>
+  <Text -46 -32 12 #005500 0 "G1">
+  <Text -46 -11 12 #005500 0 "D0">
+  <Text -46 6 12 #005500 0 "D1">
+  <Line -80 40 30 0 #000080 2 1>
+  <Line -80 60 30 0 #000080 2 1>
+  <Text -46 29 12 #005500 0 "D2">
+  <Text -46 50 12 #005500 0 "D3">
+  <Text 24 -11 14 #005500 0 "Z">
+  <.ID -40 104 X>
+  <Line 40 0 20 0 #000080 2 1>
+  <.PortSym 60 0 8 180 >
+  <Line -80 20 30 0 #000080 2 1>
+  <.PortSym -80 -60 1 0 >
+  <.PortSym -80 -40 2 0 >
+  <.PortSym -80 -20 3 0 >
+  <.PortSym -80 0 4 0 >
+  <.PortSym -80 20 5 0 >
+  <.PortSym -80 40 6 0 >
+  <.PortSym -80 60 7 0 >
 </Symbol>
-

library/XyceDigital/MUX8TO1.sym

@@ -1,46 +1,46 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Rectangle -40 -80 90 290 #005500 3 1 #c0c0c0 1 0>
-  <Text -13 -78 12 #005500 0 "MUX">
-  <Line -80 -40 25 0 #000080 2 1>
-  <Ellipse -55 -48 15 15 #005500 3 1 #c0c0c0 1 0>
-  <.PortSym -80 -40 1 0>
-  <Text -36 -52 12 #005500 0 "En">
-  <Line -80 -20 40 0 #000080 2 1>
-  <.PortSym -80 -20 2 0>
-  <Line -80 0 40 0 #000080 2 1>
-  <Line -80 20 40 0 #000080 2 1>
-  <.PortSym -80 0 3 0>
-  <.PortSym -80 20 4 0>
-  <Line -80 40 40 0 #000080 2 1>
-  <.PortSym -80 40 5 0>
-  <Line -80 60 40 0 #000080 2 1>
-  <.PortSym -80 60 6 0>
-  <Line -80 80 40 0 #000080 2 1>
-  <.PortSym -80 80 7 0>
-  <Line -80 100 40 0 #000080 2 1>
-  <Line -80 120 40 0 #000080 2 1>
-  <Line -80 140 40 0 #000080 2 1>
-  <Line -80 160 40 0 #000080 2 1>
-  <.PortSym -80 100 8 0>
-  <.PortSym -80 120 9 0>
-  <.PortSym -80 140 10 0>
-  <.PortSym -80 160 11 0>
-  <Line 50 50 30 0 #000080 2 1>
-  <Text 33 36 14 #005500 0 "Z">
-  <Line -80 180 40 0 #000080 2 1>
-  <.PortSym -80 180 12 0>
-  <.PortSym 80 50 13 180>
-  <Text -34 167 12 #005500 0 "D7">
-  <Text -35 146 12 #005500 0 "D6">
-  <Text -35 127 12 #000000 0 "D5">
-  <Text -36 107 12 #005500 0 "D4">
-  <Text -36 86 12 #005500 0 "D3">
-  <Text -36 66 12 #005500 0 "D2">
-  <Text -36 47 12 #005500 0 "D1">
-  <Text -36 27 12 #005500 0 "D0">
-  <Text -37 7 12 #005500 0 "G2">
-  <Text -36 -13 12 #005500 0 "G1">
-  <Text -36 -33 12 #005500 0 "G0">
-  <.ID -30 214 X>
+  <Rectangle -50 -130 90 290 #005500 3 1 #c0c0c0 1 0>
+  <Text -23 -128 12 #005500 0 "MUX">
+  <Ellipse -65 -98 15 15 #005500 3 1 #c0c0c0 1 0>
+  <Text -46 -102 12 #005500 0 "En">
+  <Line -80 -70 30 0 #000080 2 1>
+  <Line -80 -50 30 0 #000080 2 1>
+  <Line -80 -30 30 0 #000080 2 1>
+  <Line -80 -10 30 0 #000080 2 1>
+  <Line -80 10 30 0 #000080 2 1>
+  <Line -80 30 30 0 #000080 2 1>
+  <Line -80 50 30 0 #000080 2 1>
+  <Line -80 70 30 0 #000080 2 1>
+  <Line -80 90 30 0 #000080 2 1>
+  <Line -80 110 30 0 #000080 2 1>
+  <Line 40 0 20 0 #000080 2 1>
+  <Text 23 -14 14 #005500 0 "Z">
+  <Line -80 130 30 0 #000080 2 1>
+  <Text -44 117 12 #005500 0 "D7">
+  <Text -45 96 12 #005500 0 "D6">
+  <Text -45 77 12 #000000 0 "D5">
+  <Text -46 57 12 #005500 0 "D4">
+  <Text -46 36 12 #005500 0 "D3">
+  <Text -46 16 12 #005500 0 "D2">
+  <Text -46 -3 12 #005500 0 "D1">
+  <Text -46 -23 12 #005500 0 "D0">
+  <Text -47 -43 12 #005500 0 "G2">
+  <Text -46 -63 12 #005500 0 "G1">
+  <Text -46 -83 12 #005500 0 "G0">
+  <.ID -40 164 X>
+  <.PortSym 60 0 13 180 >
+  <Line -80 -90 15 0 #000080 2 1>
+  <.PortSym -80 -90 1 0 >
+  <.PortSym -80 -70 2 0 >
+  <.PortSym -80 -50 3 0 >
+  <.PortSym -80 -30 4 0 >
+  <.PortSym -80 -10 5 0 >
+  <.PortSym -80 10 6 0 >
+  <.PortSym -80 30 7 0 >
+  <.PortSym -80 50 8 0 >
+  <.PortSym -80 70 9 0 >
+  <.PortSym -80 90 10 0 >
+  <.PortSym -80 110 11 0 >
+  <.PortSym -80 130 12 0 >
 </Symbol>
-

library/XyceDigital/NAND2.sym

@@ -1,12 +1,13 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Rectangle -20 -40 40 81 #005500 3 1 #c0c0c0 1 0>
   <Ellipse 20 -5 10 10 #005500 3 1 #c0c0c0 1 0>
-  <Line 30 0 30 0 #000080 2 1>
   <Line -40 -10 20 0 #000080 2 1>
   <Line -40 10 20 0 #000080 2 1>
-  <.PortSym -40 -10 1 0>
-  <.PortSym -40 10 2 0>
-  <.PortSym 60 0 3 180>
-  <.ID -30 44 X>
-  <Text -5 -39 12 #005500 0 "&">
+  <.PortSym -40 -10 1 0 >
+  <.PortSym -40 10 2 0 >
+  <Text -5 -29 12 #005500 0 "&">
+  <Rectangle -20 -30 40 60 #005500 3 1 #c0c0c0 1 0>
+  <.ID -30 34 X>
+  <Line 30 0 10 0 #000080 2 1>
+  <.PortSym 40 0 3 180 >
 </Symbol>

library/XyceDigital/NAND4.sym

@@ -1,16 +1,17 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Line -60 -40 20 0 #000080 2 1>
-  <.PortSym -60 -40 1 0>
-  <Line -60 -20 20 0 #000080 2 1>
-  <.PortSym -60 -20 2 0>
-  <Line -60 0 20 0 #000080 2 1>
-  <Line -60 20 20 0 #000080 2 1>
-  <.PortSym -60 0 3 0>
-  <.PortSym -60 20 4 0>
-  <Rectangle -40 -70 70 120 #005500 3 1 #c0c0c0 1 0>
-  <Ellipse 30 -18 15 14 #00007f 3 1 #c0c0c0 1 0>
-  <Line 45 -10 35 0 #000080 2 1>
-  <.PortSym 80 -10 5 180>
-  <.ID -40 54 X>
-  <Text -11 -71 12 #005500 0 "&">
+  <Line -50 -30 20 0 #000080 2 1>
+  <.PortSym -50 -30 1 0 >
+  <Line -50 -10 20 0 #000080 2 1>
+  <.PortSym -50 -10 2 0 >
+  <Line -50 10 20 0 #000080 2 1>
+  <Line -50 30 20 0 #000080 2 1>
+  <.PortSym -50 10 3 0 >
+  <.PortSym -50 30 4 0 >
+  <.ID -30 64 X>
+  <Rectangle -30 -60 60 120 #005500 3 1 #c0c0c0 1 0>
+  <Ellipse 30 -8 15 14 #00007f 3 1 #c0c0c0 1 0>
+  <Line 45 0 15 0 #000080 2 1>
+  <.PortSym 60 0 5 180 >
+  <Text -6 -56 12 #005500 0 "&">
 </Symbol>

library/XyceDigital/NOR2.sym

@@ -1,13 +1,13 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Rectangle -20 -40 40 81 #005500 3 1 #c0c0c0 1 0>
   <Ellipse 20 -5 10 10 #005500 3 1 #c0c0c0 1 0>
-  <Line 30 0 30 0 #000080 2 1>
+  <Line 30 0 10 0 #000080 2 1>
   <Line -40 -10 20 0 #000080 2 1>
   <Line -40 10 20 0 #000080 2 1>
-  <.PortSym -40 -10 1 0>
-  <.PortSym -40 10 2 0>
-  <.PortSym 60 0 3 180>
-  <.ID -30 44 X>
-  <Text -10 -39 12 #005500 0 "≥ 1">
+  <.PortSym -40 -10 1 0 >
+  <.PortSym -40 10 2 0 >
+  <Rectangle -20 -30 40 60 #005500 3 1 #c0c0c0 1 0>
+  <.ID -30 34 X>
+  <.PortSym 40 0 3 180 >
+  <Text -20 -29 12 #005500 0 ">= 1">
 </Symbol>
-

library/XyceDigital/NOR4.sym

@@ -1,16 +1,17 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Line -60 -40 20 0 #000080 2 1>
-  <.PortSym -60 -40 1 0>
-  <Line -60 -20 20 0 #000080 2 1>
-  <.PortSym -60 -20 2 0>
-  <Line -60 0 20 0 #000080 2 1>
-  <Line -60 20 20 0 #000080 2 1>
-  <.PortSym -60 0 3 0>
-  <.PortSym -60 20 4 0>
-  <Text -16 -71 12 #005500 0 "≥ 1">
-  <Rectangle -40 -70 70 120 #005500 3 1 #c0c0c0 1 0>
-  <Ellipse 30 -18 15 14 #00007f 3 1 #c0c0c0 1 0>
-  <Line 45 -10 35 0 #000080 2 1>
-  <.PortSym 80 -10 5 180>
-  <.ID -40 54 X>
+  <Line -50 -30 20 0 #000080 2 1>
+  <.PortSym -50 -30 1 0 >
+  <Line -50 -10 20 0 #000080 2 1>
+  <.PortSym -50 -10 2 0 >
+  <Line -50 10 20 0 #000080 2 1>
+  <Line -50 30 20 0 #000080 2 1>
+  <.PortSym -50 10 3 0 >
+  <.PortSym -50 30 4 0 >
+  <.ID -30 64 X>
+  <Rectangle -30 -60 60 120 #005500 3 1 #c0c0c0 1 0>
+  <Ellipse 30 -8 15 14 #00007f 3 1 #c0c0c0 1 0>
+  <Line 45 0 15 0 #000080 2 1>
+  <.PortSym 60 0 5 180 >
+  <Text -16 -51 12 #005500 0 ">= 1">
 </Symbol>

library/XyceDigital/NXOR.sym

@@ -1,13 +1,13 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Rectangle -20 -40 40 81 #005500 3 1 #c0c0c0 1 0>
   <Ellipse 20 -5 10 10 #005500 3 1 #c0c0c0 1 0>
-  <Line 30 0 30 0 #000080 2 1>
   <Line -40 -10 20 0 #000080 2 1>
   <Line -40 10 20 0 #000080 2 1>
-  <.PortSym -40 -10 1 0>
-  <.PortSym -40 10 2 0>
-  <.PortSym 60 0 3 180>
+  <.PortSym -40 -10 1 0 >
+  <.PortSym -40 10 2 0 >
   <.ID -30 44 X>
   <Text -10 -39 12 #005500 0 "= 1">
+  <Line 30 0 10 0 #000080 2 1>
+  <.PortSym 40 0 3 180 >
 </Symbol>
-

library/XyceDigital/OR2.sym

@@ -1,12 +1,12 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Line -40 -40 20 0 #000080 2 1>
-  <.PortSym -40 -40 1 0>
+  <.PortSym -40 -40 1 0 >
   <Line -40 -20 20 0 #000080 2 1>
-  <.PortSym -40 -20 2 0>
+  <.PortSym -40 -20 2 0 >
   <Line 40 -30 -20 0 #000080 2 1>
-  <.PortSym 40 -30 3 180>
+  <.PortSym 40 -30 3 180 >
   <Rectangle -20 -60 40 60 #005500 3 1 #c0c0c0 1 0>
-  <Text -11 -58 12 #005500 0 "≥ 1">
   <.ID -30 4 X>
+  <Text -21 -58 12 #005500 0 ">= 1">
 </Symbol>
-

library/XyceDigital/OR4.sym

@@ -1,17 +1,16 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Line -60 -40 20 0 #000080 2 1>
-  <.PortSym -60 -40 1 0>
-  <Line -60 -20 20 0 #000080 2 1>
-  <.PortSym -60 -20 2 0>
-  <Line -60 0 20 0 #000080 2 1>
-  <Line -60 20 20 0 #000080 2 1>
-  <.PortSym -60 0 3 0>
-  <.PortSym -60 20 4 0>
-  <Rectangle -40 -70 70 120 #005500 3 1 #c0c0c0 1 0>
-  <.ID -40 54 X>
-  <Line 30 -10 30 0 #000080 2 1>
-  <.PortSym 60 -10 5 180>
-  <Text -17 -71 12 #005500 0 "≥ 1">
+  <Line -50 -30 20 0 #000080 2 1>
+  <Line -50 -10 20 0 #000080 2 1>
+  <Line -50 10 20 0 #000080 2 1>
+  <Line -50 30 20 0 #000080 2 1>
+  <Rectangle -30 -60 60 120 #005500 3 1 #c0c0c0 1 0>
+  <Line 30 0 20 0 #000080 2 1>
+  <Text -16 -51 12 #005500 0 ">= 1">
+  <.PortSym 50 0 5 180 >
+  <.PortSym -50 -30 1 0 >
+  <.PortSym -50 -10 2 0 >
+  <.PortSym -50 10 3 0 >
+  <.PortSym -50 30 4 0 >
+  <.ID -40 64 X>
 </Symbol>
-
-

library/XyceDigital/PATGENX1.sym

@@ -1,12 +1,12 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
-  <Line -40 -10 60 0 #005500 3 1>
-  <Line -40 10 60 0 #005500 3 1>
-  <Line 20 10 10 -10 #005500 3 1>
-  <Line 20 -10 10 10 #005500 3 1>
-  <Line 30 0 10 0 #000080 2 1>
-  <.PortSym 40 0 1 180>
-  <Line -40 -10 0 20 #005500 3 1>
-  <.ID -40 14 X >
-  <Text -37 -13 12 #005500 0 "PG">
+  <Line -50 -10 60 0 #005500 3 1>
+  <Line -50 10 60 0 #005500 3 1>
+  <Line 10 10 10 -10 #005500 3 1>
+  <Line 10 -10 10 10 #005500 3 1>
+  <Line 20 0 10 0 #000080 2 1>
+  <.PortSym 30 0 1 180 >
+  <Line -50 -10 0 20 #005500 3 1>
+  <.ID -49 14 X>
+  <Text -37 -10 12 #005500 0 "PG">
 </Symbol>
-

library/XyceDigital/PATGENX128.sym

@@ -1,40 +1,36 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Line -50 -10 70 0 #005500 3 1>
   <Line -20 10 40 0 #005500 3 1>
   <Line 20 10 10 -10 #005500 3 1>
   <Line 20 -10 10 10 #005500 3 1>
   <Line 30 0 10 0 #000080 2 1>
-  <.PortSym 40 0 1 180>
+  <.PortSym 40 0 1 180 >
   <Line -50 10 70 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line 20 30 10 -10 #005500 3 1>
   <Line 20 10 10 10 #005500 3 1>
   <Line 30 20 10 0 #000080 2 1>
-  <.PortSym 40 20 2 180>
-  <Text 9 9 10 #005500 0 "x2">
-  <Text 9 -12 10 #005500 0 "x1">
+  <.PortSym 40 20 2 180 >
   <Line -50 -10 0 20 #005500 3 1>
   <Line -50 10 0 20 #005500 3 1>
-  <Text -44 -13 12 #005500 0 "PG">
   <Line -20 30 40 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line 20 50 10 -10 #005500 3 1>
   <Line 20 30 10 10 #005500 3 1>
-  <Text 9 29 10 #005500 0 "x4">
   <Line -50 30 0 20 #005500 3 1>
   <Line 30 40 10 0 #000080 2 1>
-  <.PortSym 40 40 3 180>
+  <.PortSym 40 40 3 180 >
   <Line -50 50 70 0 #005500 3 1>
   <Line -20 50 40 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line -50 70 70 0 #005500 3 1>
   <Line 20 70 10 -10 #005500 3 1>
   <Line 20 50 10 10 #005500 3 1>
-  <Text 9 49 10 #005500 0 "x8">
   <Line -50 50 0 20 #005500 3 1>
   <Line 30 60 10 0 #000080 2 1>
-  <.PortSym 40 60 4 180>
+  <.PortSym 40 60 4 180 >
   <Line -50 70 70 0 #005500 3 1>
   <Line -20 70 40 0 #005500 3 1>
   <Line -50 70 70 0 #005500 3 1>
@@ -49,12 +45,10 @@
   <Line 20 110 10 -10 #005500 3 1>
   <Line 20 90 10 10 #005500 3 1>
   <Line -50 90 0 20 #005500 3 1>
-  <Text 0 89 10 #005500 0 "x32">
-  <Text 2 69 10 #005500 0 "x16">
   <Line 30 80 10 0 #000080 2 1>
   <Line 30 100 10 0 #000080 2 1>
-  <.PortSym 40 80 5 180>
-  <.PortSym 40 100 6 180>
+  <.PortSym 40 80 5 180 >
+  <.PortSym 40 100 6 180 >
   <Line -50 110 70 0 #005500 3 1>
   <Line -50 110 70 0 #005500 3 1>
   <Line -20 110 40 0 #005500 3 1>
@@ -70,11 +64,18 @@
   <Line 20 150 10 -10 #005500 3 1>
   <Line 20 130 10 10 #005500 3 1>
   <Line -50 130 0 20 #005500 3 1>
-  <Text 1 109 10 #005500 0 "x64">
-  <Text -7 129 10 #005500 0 "x128">
   <Line 30 120 10 0 #000080 2 1>
   <Line 30 140 10 0 #000080 2 1>
-  <.PortSym 40 120 7 180>
-  <.PortSym 40 140 8 180>
-  <.ID -63 155 X >
+  <.PortSym 40 120 7 180 >
+  <.PortSym 40 140 8 180 >
+  <.ID -63 155 X>
+  <Text -37 -10 12 #005500 0 "PG">
+  <Text 8 11 10 #005500 0 "x2">
+  <Text 8 -10 10 #005500 0 "x1">
+  <Text 8 31 10 #005500 0 "x4">
+  <Text 8 51 10 #005500 0 "x8">
+  <Text -1 91 10 #005500 0 "x32">
+  <Text 1 71 10 #005500 0 "x16">
+  <Text 0 111 10 #005500 0 "x64">
+  <Text -8 131 10 #005500 0 "x128">
 </Symbol>

library/XyceDigital/PATGENX2.sym

@@ -1,20 +1,21 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Line -50 -10 70 0 #005500 3 1>
   <Line -20 10 40 0 #005500 3 1>
   <Line 20 10 10 -10 #005500 3 1>
   <Line 20 -10 10 10 #005500 3 1>
   <Line 30 0 10 0 #000080 2 1>
-  <.PortSym 40 0 1 180>
+  <.PortSym 40 0 1 180 >
   <Line -50 10 70 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line 20 30 10 -10 #005500 3 1>
   <Line 20 10 10 10 #005500 3 1>
   <Line 30 20 10 0 #000080 2 1>
-  <.PortSym 40 20 2 180>
-  <Text 9 9 10 #005500 0 "x2">
-  <Text 9 -12 10 #005500 0 "x1">
+  <.PortSym 40 20 2 180 >
   <Line -50 -10 0 20 #005500 3 1>
   <Line -50 10 0 20 #005500 3 1>
-  <.ID -53 35 X >
-  <Text -44 -13 12 #005500 0 "PG">
+  <.ID -53 35 X>
+  <Text -37 -10 12 #005500 0 "PG">
+  <Text 9 11 10 #005500 0 "x2">
+  <Text 9 -10 10 #005500 0 "x1">
 </Symbol>

library/XyceDigital/PATGENX32.sym

@@ -1,40 +1,36 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Line -50 -10 70 0 #005500 3 1>
   <Line -20 10 40 0 #005500 3 1>
   <Line 20 10 10 -10 #005500 3 1>
   <Line 20 -10 10 10 #005500 3 1>
   <Line 30 0 10 0 #000080 2 1>
-  <.PortSym 40 0 1 180>
+  <.PortSym 40 0 1 180 >
   <Line -50 10 70 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line 20 30 10 -10 #005500 3 1>
   <Line 20 10 10 10 #005500 3 1>
   <Line 30 20 10 0 #000080 2 1>
-  <.PortSym 40 20 2 180>
-  <Text 9 9 10 #005500 0 "x2">
-  <Text 9 -12 10 #005500 0 "x1">
+  <.PortSym 40 20 2 180 >
   <Line -50 -10 0 20 #005500 3 1>
   <Line -50 10 0 20 #005500 3 1>
-  <Text -44 -13 12 #005500 0 "PG">
   <Line -20 30 40 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line 20 50 10 -10 #005500 3 1>
   <Line 20 30 10 10 #005500 3 1>
-  <Text 9 29 10 #005500 0 "x4">
   <Line -50 30 0 20 #005500 3 1>
   <Line 30 40 10 0 #000080 2 1>
-  <.PortSym 40 40 3 180>
+  <.PortSym 40 40 3 180 >
   <Line -50 50 70 0 #005500 3 1>
   <Line -20 50 40 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line -50 70 70 0 #005500 3 1>
   <Line 20 70 10 -10 #005500 3 1>
   <Line 20 50 10 10 #005500 3 1>
-  <Text 9 49 10 #005500 0 "x8">
   <Line -50 50 0 20 #005500 3 1>
   <Line 30 60 10 0 #000080 2 1>
-  <.PortSym 40 60 4 180>
+  <.PortSym 40 60 4 180 >
   <Line -50 70 70 0 #005500 3 1>
   <Line -20 70 40 0 #005500 3 1>
   <Line -50 70 70 0 #005500 3 1>
@@ -49,12 +45,16 @@
   <Line 20 110 10 -10 #005500 3 1>
   <Line 20 90 10 10 #005500 3 1>
   <Line -50 90 0 20 #005500 3 1>
-  <Text 0 89 10 #005500 0 "x32">
-  <Text 2 69 10 #005500 0 "x16">
   <Line 30 80 10 0 #000080 2 1>
   <Line 30 100 10 0 #000080 2 1>
-  <.PortSym 40 80 5 180>
-  <.PortSym 40 100 6 180>
-  <.ID -53 115 X >
+  <.PortSym 40 80 5 180 >
+  <.PortSym 40 100 6 180 >
+  <.ID -53 115 X>
+  <Text -37 -10 12 #005500 0 "PG">
+  <Text 9 11 10 #005500 0 "x2">
+  <Text 9 -10 10 #005500 0 "x1">
+  <Text 9 31 10 #005500 0 "x4">
+  <Text 9 51 10 #005500 0 "x8">
+  <Text 0 91 10 #005500 0 "x32">
+  <Text 2 71 10 #005500 0 "x16">
 </Symbol>
-

library/XyceDigital/PATGENX4.sym

@@ -1,30 +1,30 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Line -50 -10 70 0 #005500 3 1>
   <Line -20 10 40 0 #005500 3 1>
   <Line 20 10 10 -10 #005500 3 1>
   <Line 20 -10 10 10 #005500 3 1>
   <Line 30 0 10 0 #000080 2 1>
-  <.PortSym 40 0 1 180>
+  <.PortSym 40 0 1 180 >
   <Line -50 10 70 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line 20 30 10 -10 #005500 3 1>
   <Line 20 10 10 10 #005500 3 1>
   <Line 30 20 10 0 #000080 2 1>
-  <.PortSym 40 20 2 180>
-  <Text 9 9 10 #005500 0 "x2">
-  <Text 9 -12 10 #005500 0 "x1">
+  <.PortSym 40 20 2 180 >
   <Line -50 -10 0 20 #005500 3 1>
   <Line -50 10 0 20 #005500 3 1>
-  <Text -44 -13 12 #005500 0 "PG">
   <Line -20 30 40 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line 20 50 10 -10 #005500 3 1>
   <Line 20 30 10 10 #005500 3 1>
-  <Text 9 29 10 #005500 0 "x4">
   <Line -50 30 0 20 #005500 3 1>
   <Line 30 40 10 0 #000080 2 1>
-  <.PortSym 40 40 3 180>
-  <.ID -53 55 X >
+  <.PortSym 40 40 3 180 >
+  <.ID -53 55 X>
+  <Text -37 -10 12 #005500 0 "PG">
+  <Text 9 11 10 #005500 0 "x2">
+  <Text 9 -10 10 #005500 0 "x1">
+  <Text 9 31 10 #005500 0 "x4">
 </Symbol>
-

library/XyceDigital/PATGENX8.sym

@@ -1,40 +1,40 @@
+<Qucs Schematic 24.3.99>
 <Symbol>
   <Line -50 -10 70 0 #005500 3 1>
   <Line -20 10 40 0 #005500 3 1>
   <Line 20 10 10 -10 #005500 3 1>
   <Line 20 -10 10 10 #005500 3 1>
   <Line 30 0 10 0 #000080 2 1>
-  <.PortSym 40 0 1 180>
+  <.PortSym 40 0 1 180 >
   <Line -50 10 70 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line 20 30 10 -10 #005500 3 1>
   <Line 20 10 10 10 #005500 3 1>
   <Line 30 20 10 0 #000080 2 1>
-  <.PortSym 40 20 2 180>
-  <Text 9 9 10 #005500 0 "x2">
-  <Text 9 -12 10 #005500 0 "x1">
+  <.PortSym 40 20 2 180 >
   <Line -50 -10 0 20 #005500 3 1>
   <Line -50 10 0 20 #005500 3 1>
-  <Text -44 -13 12 #005500 0 "PG">
   <Line -20 30 40 0 #005500 3 1>
   <Line -50 30 70 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line 20 50 10 -10 #005500 3 1>
   <Line 20 30 10 10 #005500 3 1>
-  <Text 9 29 10 #005500 0 "x4">
   <Line -50 30 0 20 #005500 3 1>
   <Line 30 40 10 0 #000080 2 1>
-  <.PortSym 40 40 3 180>
+  <.PortSym 40 40 3 180 >
   <Line -50 50 70 0 #005500 3 1>
   <Line -20 50 40 0 #005500 3 1>
   <Line -50 50 70 0 #005500 3 1>
   <Line -50 70 70 0 #005500 3 1>
   <Line 20 70 10 -10 #005500 3 1>
   <Line 20 50 10 10 #005500 3 1>
-  <Text 9 49 10 #005500 0 "x8">
   <Line -50 50 0 20 #005500 3 1>
   <Line 30 60 10 0 #000080 2 1>
-  <.PortSym 40 60 4 180>
-  <.ID -53 75 X >
+  <.PortSym 40 60 4 180 >
+  <Text -37 -10 12 #005500 0 "PG">
+  <Text 9 11 10 #005500 0 "x2">
+  <Text 9 -10 10 #005500 0 "x1">
+  <Text 9 31 10 #005500 0 "x4">
+  <Text 9 51 10 #005500 0 "x8">
+  <.ID -53 75 X>
 </Symbol>
-

library/XyceDigital/XOR.sym

@@ -1,3 +1,4 @@
+<Qucs Schematic 1.0.0>
 <Symbol>
   <Line -40 -40 20 0 #000080 2 1>
   <.PortSym -40 -40 1 0>

library/qucs.blacklist

@@ -1,5 +1,10 @@
+Analog.lib
 SpiceOpamp.lib
 Cores.lib
+Digital_CD.lib
+Digital_HC.lib
+Digital_LV.lib
+LaserDiodes.lib
 Transformers.lib
 Xanalogue.lib
 BF998.lib
@@ -8,3 +13,10 @@ VoltageRegulators.lib
 VoltageReferences.lib
 PWM_Controller.lib
 MixerIC.lib
+SPICE_TLine.lib
+Digital_AUX.lib
+Digital_XSPICE.lib
+DualGateMOSFET.lib
+TubesExtended.lib
+Neon.lib
+Optocoupler.lib

library/symbols/led.sym

@@ -0,0 +1,14 @@
+<Qucs Schematic 24.4.1>
+<Symbol>
+  <Line 0 30 0 -24 #000080 2 1>
+  <Line 0 -6 0 -24 #000080 2 1>
+  <Line -9 6 18 0 #000080 2 1>
+  <Line -9 -6 18 0 #000080 2 1>
+  <Line 0 6 -9 -12 #000080 2 1>
+  <Line 0 6 9 -12 #000080 2 1>
+  <Arrow 13 -5 10 -10 9 3 #000080 2 1 0>
+  <Arrow 13 5 10 -10 9 3 #000080 2 1 0>
+  <.ID 30 -16 SUB>
+  <.PortSym 0 -30 1 0 1>
+  <.PortSym 0 30 2 0 1>
+</Symbol>

library/symbols/schottky.sym

@@ -0,0 +1,13 @@
+<Qucs Schematic 24.4.1>
+<Symbol>
+  <Line 9 -6 -18 0 #000080 2 1>
+  <Line 9 6 -18 0 #000080 2 1>
+  <Line 0 -30 0 24 #000080 2 1>
+  <Line 0 6 0 24 #000080 2 1>
+  <Line -9 -6 0 5 #000080 2 1>
+  <Line 0 -6 -9 12 #000080 2 1>
+  <Line 0 -6 9 12 #000080 2 1>
+  <.ID 20 -16 SUB>
+  <.PortSym 0 30 1 0 1>
+  <.PortSym 0 -30 2 0 2>
+</Symbol>

library/xyce.blacklist

@@ -1,4 +1,8 @@
 Substrates.lib
 Xanalogue.lib
 PWM_Controller.lib
-
+Digital_CD.lib
+Digital_HC.lib
+Digital_LV.lib
+Digital_AUX.lib
+Digital_XSPICE.lib

qucs-activefilter/CMakeLists.txt

@@ -6,9 +6,14 @@ SET(QUCS_NAME "qucs-s")
 
 # use top VERSION file
 file (STRINGS ${PROJECT_SOURCE_DIR}/../VERSION QUCS_VERSION)
-message(STATUS "Configuring ${PROJECT_NAME} (GUI): VERSION ${QUCS_VERSION}")
 
-set(PROJECT_VERSION "${QUCS_VERSION}")
+if(DEFINED CI_VERSION)
+    set(PROJECT_VERSION "${CI_VERSION}")
+else()
+    set(PROJECT_VERSION "${QUCS_VERSION}")
+endif()
+
+message(STATUS "Configuring ${PROJECT_NAME} (GUI): VERSION ${PROJECT_VERSION}")
 
 set(PROJECT_VENDOR "Qucs team. This program is licensed under the GNU GPL")
 set(PROJECT_COPYRIGHT_YEAR "2014")
@@ -28,39 +33,44 @@ CONFIGURE_FILE (
 
 INCLUDE_DIRECTORIES("${PROJECT_BINARY_DIR}")
 
-if(WITH_QT6)
-    set(QT_VERSION_MAJOR 6)
-else()
-    set(QT_VERSION_MAJOR 5)
-endif()
-
-
-if(QT_VERSION_MAJOR EQUAL 6)
-  find_package(Qt${QT_VERSION_MAJOR} REQUIRED COMPONENTS Core  Widgets Svg SvgWidgets)
+  find_package(Qt6 REQUIRED COMPONENTS Core  Widgets Svg SvgWidgets)
   include_directories(
-      ${Qt${QT_VERSION_MAJOR}Core_INCLUDE_DIRS}
-      ${Qt${QT_VERSION_MAJOR}Widgets_INCLUDE_DIRS}
-      ${Qt${QT_VERSION_MAJOR}Svg_INCLUDE_DIRS}
-      ${Qt${QT_VERSION_MAJOR}SvgWidgets_INCLUDE_DIRS}
+      ${Qt6Core_INCLUDE_DIRS}
+      ${Qt6Widgets_INCLUDE_DIRS}
+      ${Qt6Svg_INCLUDE_DIRS}
+      ${Qt6SvgWidgets_INCLUDE_DIRS}
       )
+
+set(QT_VERSION ${Qt6Core_VERSION})
+
+if (${QT_VERSION} VERSION_LESS "6.7.0")
+    set(CMAKE_CXX_STANDARD 17)
 else()
-  find_package(Qt${QT_VERSION_MAJOR} REQUIRED COMPONENTS Core  Widgets Svg)
-  include_directories(
-      ${Qt${QT_VERSION_MAJOR}Core_INCLUDE_DIRS}
-      ${Qt${QT_VERSION_MAJOR}Widgets_INCLUDE_DIRS}
-      ${Qt${QT_VERSION_MAJOR}Svg_INCLUDE_DIRS}
-      )
+    set(CMAKE_CXX_STANDARD 20)
 endif()
-
-
-set(CMAKE_CXX_STANDARD 17)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
+set(CMAKE_CXX_EXTENSIONS OFF)
 
-if (MSVC)
-  add_compile_options(/Zc:__cplusplus /permissive- /MP /Zc:preprocessor)
-else()
-  # additional warnings
-  add_compile_options(-Wall -Wextra)
+if (CMAKE_BUILD_TYPE STREQUAL "Debug")
+    if (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC")
+        add_compile_definitions(_CRT_SECURE_NO_WARNINGS _SCL_SECURE_NO_WARNINGS)
+        add_compile_options(/permissive- /Zc:__cplusplus /Zc:preprocessor /MP /Od /vmg)
+        add_compile_options(/wd4244 /wd4267 /wd4312)
+    else()
+        add_compile_options(-Wall -Wextra -O0 -g)
+        if (CMAKE_CXX_COMPILER_ID MATCHES "^AppleClang$|^Clang$")
+            add_compile_options(-Wno-ignored-attributes)
+        endif()
+    endif()
+elseif(CMAKE_BUILD_TYPE STREQUAL "Release")
+    if (CMAKE_CXX_COMPILER_ID STREQUAL "MSVC")
+        add_compile_definitions(_CRT_SECURE_NO_WARNINGS _SCL_SECURE_NO_WARNINGS)
+        string(REGEX REPLACE "/W1" "/w" CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}")
+        add_compile_options(/permissive- /Zc:__cplusplus /Zc:preprocessor /MP /vmg)
+        add_link_options(/OPT:REF /OPT:ICF)
+    else()
+        add_compile_options(-w)
+    endif()
 endif()
 
 ADD_DEFINITIONS(${QT_DEFINITIONS})
@@ -84,13 +94,8 @@ helpdialog.h
 )
 
 SET(RESOURCES qucsactivefilter.qrc)
-IF(QT_VERSION_MAJOR EQUAL 6)
 QT6_WRAP_CPP(QUCS-ACTIVE-FILTER_MOC_SRCS ${QUCS-ACTIVE-FILTER_MOC_HDRS})
 QT6_ADD_RESOURCES(RESOURCES_SRCS ${RESOURCES})
-ELSE()
-QT5_WRAP_CPP(QUCS-ACTIVE-FILTER_MOC_SRCS ${QUCS-ACTIVE-FILTER_MOC_HDRS})
-QT5_ADD_RESOURCES(RESOURCES_SRCS ${RESOURCES})
-ENDIF()
 
 
 
@@ -118,13 +123,7 @@ ADD_EXECUTABLE(${QUCS_NAME}activefilter MACOSX_BUNDLE WIN32
   ${RESOURCES_SRCS} )
 
 
-if(QT_VERSION_MAJOR EQUAL 6)
-    TARGET_LINK_LIBRARIES(${QUCS_NAME}activefilter Qt${QT_VERSION_MAJOR}::Core
-        Qt${QT_VERSION_MAJOR}::Widgets Qt${QT_VERSION_MAJOR}::Svg Qt${QT_VERSION_MAJOR}::SvgWidgets)
-else()
-    TARGET_LINK_LIBRARIES(${QUCS_NAME}activefilter Qt${QT_VERSION_MAJOR}::Core
-        Qt${QT_VERSION_MAJOR}::Widgets Qt${QT_VERSION_MAJOR}::Svg )
-endif()
+TARGET_LINK_LIBRARIES(${QUCS_NAME}activefilter Qt6::Core Qt6::Widgets Qt6::Svg Qt6::SvgWidgets)
 
 
 SET_TARGET_PROPERTIES(${QUCS_NAME}activefilter PROPERTIES POSITION_INDEPENDENT_CODE TRUE)

qucs-activefilter/bitmaps/AFR.svg

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-
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-   xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
-   xmlns:svg="http://www.w3.org/2000/svg"
-   xmlns="http://www.w3.org/2000/svg"
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-   xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
-   width="196.69392"
-   height="170.28023"
-   id="svg2"
-   version="1.1"
-   inkscape:version="0.48.3.1 r9886"
-   sodipodi:docname="AFR.svg">
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