AboutDialog About Qucs Version Copyright (C) GUI programmer, Verilog-A dynamic loader project maintainer, simulator interface and GUI design component models, documentation Xyce integration Testing, examples Qt6 support, general improvements Digital simulation, general improvements CI setup, build system, MacOS support testing, general bugfixes testing, modelling and documentation, tutorial contributor testing, modelling, Octave. bondwire and rectangular waveguide model implementation GUI programmer, release filter synthesis (qucs-activefilter), SPICE integration (NGSPICE, Xyce) testing, general fixes refactoring, modularity RF design tools Schematic rendering engine, refactoring Documentation Refactoring, general improvements founder of the project, GUI programmer Programmer of simulator webpages and translator tester and applyer of Stefan's patches, author of documentation coplanar line and filter synthesis code, documentation contributor some filter synthesis code and attenuator synthesis GUI programmer, Qt4 porter programmer of the Verilog-AMS interface equation solver contributions, exponential sources, author of documentation temperature model for rectangular waveguide GUI programmer German by Polish by Romanian by French by Portuguese by Spanish by Japanese by Italian by Hebrew by Swedish by Turkish by Hungarian by Russian by Czech by Catalan by Ukrainian by Arabic by Kazakh by Chinese by Home Page Documentation start page Bugtracker page Forum Qucs-S project team: Based on Qucs project developed by: Authors Translations Support License &OK Previous Developers GUI translations : AbstractSpiceKernel Simulate Failed to create dataset file Check write permission of the directory ArrowDialog Edit Arrow Properties Head Length: Head Width: Line color: Line Width: Line style: solid line dash line dot line dash dot line dash dot dot line Arrow head: two lines filled OK Cancel AuxFilesDialog Select Cancel ChangeDialog Change Component Properties Components: all components resistors capacitors inductors transistors Component Names: Property Name: New Value: Replace Cancel Error Regular expression for component name is invalid. Found Components Change properties of these components ? Yes ComponentDialog Edit Component Properties Equation Editor Put result in dataset Sweep Properties Name Simulation Sweep Parameter Type Values Start Stop Step Number Populate parameters from SPICE file... Value Show Description Select a file All Files Touchstone files CSV files SPICE files VHDL files Verilog files CustomSimDialog Edit SPICE code Component: display in schematic Variables to plot (semicolon separated) Extra outputs (semicolon separated; raw-SPICE or XYCE-STD or scalars print format) Apply Cancel OK Find all variables Find all outputs SPICE code editor DiagramDialog Edit Diagram Properties left Axis right Axis y-Axis smith Axis polar Axis z-Axis Graph Input Plot Vs. Number Notation: real/imaginary magnitude/angle (degree) magnitude/angle (radian) Precision: Color: Style: solid line dash line dot line long dash line stars circles arrows Thickness: y-Axis: Dataset Data from simulator: Name Type Size Graph New Graph Delete Graph Data x-Axis Label: Label: <b>Label text</b>: Use LaTeX style for special characters, e.g. \tau show Grid Grid Color: Grid Style: dash dot line dash dot dot line Number notation: scientific notation engineering notation logarithmic X Axis Grid Grid logarithmic hide invisible lines Rotation around x-Axis: Rotation around y-Axis: Rotation around z-Axis: 2D-projection: Properties x-Axis manual start step stop number Limits OK Apply Cancel DigiSettingsDialog Document Settings Digital Simulation Settings Simulation Duration of Simulation: Precompile Module Library Name: Libraries: Ok Cancel Error DisplayDialog SPICE Qucs Close ExportDialog Export graphics Save to file (Graphics format by extension) Height in pixels Scale factor: Image format: Export Cancel Width in pixels Browse Colour Monochrome Grayscale Original width to height ratio Original size Export selected only Export schematic to raster or vector image Export Schematic to Image Export diagram to raster or vector image ExternSimDialog Stop Save netlist Exit Simulation console Simulate with external simulator There were simulation errors. Please check log. There were simulation warnings. Please check log. Simulation finished. Now place diagram on schematic to plot the result. Simulation successful. Now place diagram on schematic to plot the result. started... Simulation started on: Failed to start simulator! Simulator crashed! Simulator error! error... FillDialog Line Width: Line Color: Line Style: solid line dash line dot line dash dot line dash dot dot line Line Style enable filling Fill Color: Fill Style: no filling solid dense 1 (densest) dense 2 dense 3 dense 4 dense 5 dense 6 dense 7 (least dense) horizontal line vertical line crossed lines hatched backwards hatched forwards diagonal crossed Filling Style OK Cancel GraphicTextDialog Edit Text Properties Use LaTeX style for special characters, e.g. \tau Use _{..} and ^{..} for sub- and super-positions. &OK &Cancel Text color: Text size: Rotation angle: Error The text must not be empty! HelpDialog QucsFilter is a filter synthesis program. To create a filter, simply enter all parameters and press the big button at the bottom of the main window. Immediately, the schematic of the filter is calculated and put into the clipboard. Now go to Qucs, open an empty schematic and press CTRL-V (paste from clipboard). The filter schematic can now be inserted and simulated. Have lots of fun! Close Help QucsTranscalc is an analysis and synthesis tool for calculating the electrical and physical properties of different kinds of RF and microwave transmission lines. For each type of transmission line, using dialog boxes, you can enter values for the various parameters, and either calculate its electrical properties, or use the given electrical requirements to synthesize physical parameters of the required transmission line. Dismiss QucsActiveFilter is a active filter synthesis program. Butterworth, Chebyshev, Inverse Chebyshev, Cauer, Bessel and User defined transfer function are supported.To create a filter, simply enter all parameters and press the big button at the bottom of the main window. Immediately, the schematic of the filter is calculated and put into the clipboard. Now go to Qucs, open an empty schematic and press CTRL-V (paste from clipboard). The filter schematic can now be inserted and simulated. Have lots of fun! ID_Dialog Edit Subcircuit Properties Prefix: Parameters display Name Default Description Type yes no display in schematic Name: Default Value: Description: Type: Add Remove OK Apply Cancel Error Parameter must not be named "File"! Parameter "%1" already in list! ImportDialog Convert Data File... File specification Input File: Browse Output File: Output Data: Qucs dataset Touchstone CSV Input Format: SPICE netlist VCD dataset Citi ZVR MDL Output Format: Qucs library Qucs netlist Matlab Library Name: Messages Convert Abort Close All known Touchstone files CSV files CITI files ZVR ASCII files IC-CAP model files VCD files Qucs dataset files SPICE files Any file Error Cannot open file: Enter a Data File Name Qucsator netlist Info Output file already exists! Overwrite it? Running command line: ERROR: Cannot start converter! Successfully converted file! Converter ended with errors! LabelDialog Insert Nodename Enter the label: Initial node voltage: Less... Ok Cancel More... SPICE checker Node name "%1" is Nutmeg reserved keyword! Please select another node name! Node name will not be changed. LibraryDialog Create Library Library Name: Choose subcircuits: Add subcircuit description Analog models only Select All Deselect All Cancel Next >> Enter description for: Description: Previous Create Message: Close No projects! Error Please insert a library name! Please choose at least one subcircuit! Warning Cannot create user library directory ! A library with this name already exists! Rewrite? Next... Saving library... Error: Cannot create library! Loading subcircuit "%1". Error: Cannot load subcircuit "%1". Creating Qucs netlist. Error: Cannot create netlist for "%1". Creating SPICE netlist. Creating Verilog netlist. Creating VHDL netlist. Error creating library. Successfully created library. LoadDialog Load Verilog-A symbols Choose Verilog-A symbol files: Select All Deselect All Cancel Ok Change Icon auto-load selected Load the selected symbols when opening the project. Info Icon not found: %1.png Open File Icon image (*.png) Error File not found: %1 MarkerDialog Edit Marker Properties Precision: real/imaginary magnitude/angle (degree) magnitude/angle (radian) Number Notation: X-axis position: Off Square Triangle Marker Indicator Z0: transparent OK Cancel MatchDialog Create Matching Circuit Reference Impedance Port 1 Port 2 S Parameter Input format Implementation Microstrip Substrate Relative Permitivity Substrate height Metal thickness Minimum width Maximum width tanD Resistivity Method L-section Single stub Double stub Multistage Open stub Short circuit stub Number of sections Weighting Binomial Chebyshev Maximum ripple Use balanced stubs Calculate two-port matching Add S-Parameter simulation Synthesize microstrip lines Real/Imag mag/deg S11 S21 S12 S22 Frequency: Create Cancel Reflexion Coefficient Impedance (Ohms) The device is not unconditionally stable: K = %1 |%2| = %3 It is not possible to synthesize a matching network. Consider adding resistive losses and/or feedback to reach unconditional stability (K > 1 and |%2| < 1) It is not possible to match this load using the double stub method Error Real part of impedance must be greater zero, but is %1 ! MessageDock admsXml Compiler admsXml Dock NewProjDialog Create new project Project name: open new project Create Cancel Ngspice Problem with SaveNetlist OctaveWindow ERROR: Failed to execute "%1" OptimizeDialog Edit Optimization Properties Name: Simulation: General Method: Maximum number of iterations: Output refresh cycle: Number of parents: Constant F: Crossing over factor: Pseudo random number seed: Minimum cost variance: Cost objectives: Cost constraints: Algorithm Name active initial min max Type initial: min: max: linear double logarithmic double linear integer logarithmic integer E3 series E6 series E12 series E24 series E48 series E96 series E192 series Add Delete Type: Copy current values to equation Variables Value Value: minimize maximize less greater equal monitor Goals OK Apply Cancel yes no Error Every text field must be non-empty! Variable "%1" aleardy in list! Goal "%1" already in list! Set precision Precision: OptionsDialog Options Units Frequency Length Resistance Angle Save as Default Dismiss ProjectView Content of %1 Note Datasets Data Displays Verilog Verilog-A VHDL Octave Schematics Symbols SPICE Others -port QObject ac simulation AC sensitivity simulation Output variable sweep type start frequency in Hertz stop frequency in Hertz number of simulation steps calculate noise voltages ac voltage source with amplitude modulator AM peak voltage in Volts frequency in Hertz initial phase in degrees offset voltage (SPICE only) delay time (SPICE only) modulation level AM modulated Source ideal ac current source peak current in Ampere offset current (SPICE only) damping factor (transient simulation only) ac Current Source ideal dc current source current in Ampere dc Current Source noise current source current power spectral density in A^2/Hz frequency exponent frequency coefficient additive frequency term Noise Current Source ideal amplifier voltage gain reference impedance of input port reference impedance of output port noise figure Amplifier 4x2 andor verilog device transfer function high scaling factor output delay s 4x2 AndOr 4x3 andor verilog device 4x3 AndOr 4x4 andor verilog device 4x4 AndOr attenuator power attenuation reference impedance simulation temperature in degree Celsius Attenuator bias t for transient simulation: inductance in Henry for transient simulation: capacitance in Farad Bias T 4bit binary to Gray converter verilog device transfer function scaling factor 4Bit Bin2Gray bipolar junction transistor npn transistor pnp transistor polarity saturation current forward emission coefficient reverse emission coefficient high current corner for forward beta high current corner for reverse beta forward early voltage reverse early voltage base-emitter leakage saturation current base-emitter leakage emission coefficient base-collector leakage saturation current base-collector leakage emission coefficient forward beta reverse beta minimum base resistance for high currents current for base resistance midpoint collector ohmic resistance emitter ohmic resistance zero-bias base resistance (may be high-current dependent) base-emitter zero-bias depletion capacitance base-emitter junction built-in potential base-emitter junction exponential factor base-collector zero-bias depletion capacitance base-collector junction built-in potential base-collector junction exponential factor fraction of Cjc that goes to internal base pin zero-bias collector-substrate capacitance substrate junction built-in potential substrate junction exponential factor forward-bias depletion capacitance coefficient ideal forward transit time coefficient of bias-dependence for Tf voltage dependence of Tf on base-collector voltage high-current effect on Tf ideal reverse transit time flicker noise coefficient flicker noise exponent flicker noise frequency exponent burst noise coefficient burst noise exponent burst noise corner frequency in Hertz excess phase in degrees temperature exponent for forward- and reverse beta saturation current temperature exponent energy bandgap in eV temperature at which parameters were extracted default area for bipolar transistor bipolar junction transistor with substrate bond wire length of the wire diameter of the wire height above ground plane specific resistance of the metal relative permeability of the metal bond wire model substrate Bond Wire simulation temperature capacitor capacitance in Farad initial voltage for transient simulation schematic symbol Capacitor current controlled current source forward transfer factor delay time (Qucsator only) delay time Current Controlled Current Source current controlled voltage source Current Controlled Voltage Source circulator reference impedance of port 1 reference impedance of port 2 reference impedance of port 3 Circulator coaxial transmission line relative permittivity of dielectric specific resistance of conductor relative permeability of conductor inner diameter of shield diameter of inner conductor mechanical length of the line loss tangent Coaxial Line 1bit comparator verilog device 1Bit Comparator 2bit comparator verilog device 2Bit Comparator 4bit comparator verilog device 4Bit Comparator number of input ports voltage of high level Error Format Error: Wrong line start! Format Error: Unknown component! %1 Do you want to load schematic anyway? Unknown components will be replaced by dummy subcircuit placeholders. Format Error: Wrong 'component' line format! coplanar line name of substrate definition width of the line width of a gap length of the line material at the backside of the substrate use approximation instead of precise equation Coplanar Line ideal coupler coupling factor phase shift of coupling path in degree Coupler coplanar gap width of gap between the two lines Coplanar Gap coplanar open width of gap at end of line Coplanar Open coplanar short Coplanar Short coplanar step width of line 1 width of line 2 distance between ground planes Coplanar Step coupled transmission lines characteristic impedance of even mode characteristic impedance of odd mode electrical length of the line relative dielectric constant of even mode relative dielectric constant of odd mode attenuation factor per length of even mode attenuation factor per length of odd mode Coupled Transmission Line D flip flop with asynchronous reset D-FlipFlop dc simulation relative tolerance for convergence absolute tolerance for currents absolute tolerance for voltages put operating points into dataset maximum number of iterations until error save subcircuit nodes into dataset preferred convergence algorithm method for solving the circuit matrix dc block dc Block dc feed dc Feed D flip flop with set and reset verilog device cross coupled gate transfer function high scaling factor cross coupled gate transfer function low scaling factor cross coupled gate delay D-FlipFlop w/ SR diac (bidirectional trigger diode) (bidirectional) breakover voltage (bidirectional) breakover current parasitic capacitance emission coefficient intrinsic junction resistance Diac digital simulation type of simulation duration of TimeList simulation netlist format digital source number of the port initial output value list of times for changing output value diode zero-bias junction capacitance grading coefficient junction potential linear capacitance recombination current parameter emission coefficient for Isr ohmic series resistance transit time high-injection knee current (0=infinity) reverse breakdown voltage current at reverse breakdown voltage Bv linear temperature coefficient Rs linear temperature coefficient Tt linear temperature coefficient Tt quadratic temperature coefficient M linear temperature coefficient M quadratic temperature coefficient default area for diode Diode data voltage level shifter (digital to analogue) verilog device voltage level time delay D2A Level Shifter data voltage level shifter (analogue to digital) verilog device V A2D Level Shifter 2to4 demultiplexer verilog device 2to4 Demux 3to8 demultiplexer verilog device 3to8 Demux 4to16 demultiplexer verilog device 4to16 Demux externally controlled voltage source voltage in Volts Externally Controlled Voltage Source m transconductance parameter A/V**2 1/V HICUM Level 2 v2.22 verilog device GICCR constant A^2s Zero-bias hole charge Coul High-current correction for 2D and 3D effects Emitter minority charge weighting factor in HBTs Collector minority charge weighting factor in HBTs B-E depletion charge weighting factor in HBTs B-C depletion charge weighting factor in HBTs Internal B-E saturation current Internal B-E current ideality factor Internal B-E recombination saturation current Internal B-E recombination current ideality factor Peripheral B-E saturation current Peripheral B-E current ideality factor Peripheral B-E recombination saturation current Peripheral B-E recombination current ideality factor Non-ideality factor for III-V HBTs Base current recombination time constant at B-C barrier for high forward injection Internal B-C saturation current Internal B-C current ideality factor External B-C saturation current External B-C current ideality factor B-E tunneling saturation current Exponent factor for tunneling current Specifies the base node connection for the tunneling current Avalanche current factor Exponent factor for avalanche current Relative TC for FAVL 1/K Relative TC for QAVL Zero bias internal base resistance External base series resistance Factor for geometry dependence of emitter current crowding Correction factor for modulation by B-E and B-C space charge layer Ratio of HF shunt to total internal capacitance (lateral NQS effect) Ration of internal to total minority charge Emitter series resistance External collector series resistance Substrate transistor transfer saturation current Forward ideality factor of substrate transfer current C-S diode saturation current Ideality factor of C-S diode current Transit time for forward operation of substrate transistor Substrate series resistance Substrate shunt capacitance Internal B-E zero-bias depletion capacitance Internal B-E built-in potential Internal B-E grading coefficient Ratio of maximum to zero-bias value of internal B-E capacitance Peripheral B-E zero-bias depletion capacitance Peripheral B-E built-in potential Peripheral B-E grading coefficient Ratio of maximum to zero-bias value of peripheral B-E capacitance Internal B-C zero-bias depletion capacitance Internal B-C built-in potential Internal B-C grading coefficient Internal B-C punch-through voltage External B-C zero-bias depletion capacitance External B-C built-in potential External B-C grading coefficient External B-C punch-through voltage Partitioning factor of parasitic B-C cap Partitioning factor of parasitic B-E cap C-S zero-bias depletion capacitance C-S built-in potential C-S grading coefficient C-S punch-through voltage Low current forward transit time at VBC=0V Time constant for base and B-C space charge layer width modulation Time constant for modelling carrier jam at low VCE Neutral emitter storage time Exponent factor for current dependence of neutral emitter storage time Saturation time constant at high current densities Smoothing factor for current dependence of base and collector transit time Partitioning factor for base and collector portion Internal collector resistance at low electric field Voltage separating ohmic and saturation velocity regime Internal C-E saturation voltage Collector punch-through voltage Storage time for inverse operation Total parasitic B-E capacitance Total parasitic B-C capacitance Factor for additional delay time of minority charge Factor for additional delay time of transfer current Flag for turning on and off of vertical NQS effect Flicker noise coefficient Flicker noise exponent factor Flag for determining where to tag the flicker noise source Scaling factor for collector minority charge in direction of emitter width Scaling factor for collector minority charge in direction of emitter length Bandgap voltage extrapolated to 0 K First order relative TC of parameter T0 Second order relative TC of parameter T0 Temperature exponent for RCI0 Relative TC of saturation drift velocity Relative TC of VCES Temperature exponent of internal base resistance Temperature exponent of external base resistance Temperature exponent of external collector resistance Temperature exponent of emitter resistance Temperature exponent of mobility in substrate transistor transit time Effective emitter bandgap voltage Effective collector bandgap voltage Effective substrate bandgap voltage Coefficient K1 in T-dependent band-gap equation Coefficient K2 in T-dependent band-gap equation Exponent coefficient in transfer current temperature dependence Exponent coefficient in B-E junction current temperature dependence Relative TC of forward current gain for V2.1 model Flag for turning on and off self-heating effect Thermal resistance K/W Thermal capacitance J/W Flag for compatibility with v2.1 model (0=v2.1) Temperature at which parameters are specified C Temperature change w.r.t. chip temperature for particular transistor K HICUM L2 v2.22 Ohm F/m A F diode relative area parameter measurement temperature Celsius equation defined device type of equations number of branches current equation charge equation Equation Defined Device equation Equation put result into dataset Qucsator equation externally driven transient simulation integration method order of integration method initial step size in seconds minimum step size in seconds relative tolerance of local truncation error absolute tolerance of local truncation error overestimation of local truncation error relax time step raster perform an initial DC analysis maximum step size in seconds External transient simulation 1bit full adder verilog device 1Bit FullAdder 2bit full adder verilog device 2Bit FullAdder gated D latch verilog device Gated D-Latch 4bit Gray to binary converter verilog device 4Bit Gray2Bin ground (reference potential) Ground gyrator (impedance inverter) gyrator ratio Gyrator 1bit half adder verilog device 1Bit HalfAdder Harmonic balance simulation number of harmonics Harmonic balance 4bit highest priority encoder (binary form) verilog device 4Bit HPRI-Bin hybrid (unsymmetrical 3dB coupler) phase shift in degree Hybrid exponential current source current before rising edge maximum current of the pulse start time of the exponentially rising edge start of exponential decay time constant of the rising edge time constant of the falling edge Exponential Current Pulse file based current source name of the sample file interpolation type repeat waveform current gain File Based Current Source inductor inductance in Henry initial current for transient simulation Inductor current probe Current Probe ideal current pulse source current before and after the pulse current of the pulse start time of the pulse ending time of the pulse rise time of the leading edge fall time of the trailing edge Current Pulse ideal rectangle current source current at high pulse duration of high pulses duration of low pulses initial delay time Rectangle Current isolator Isolator junction field-effect transistor threshold voltage channel-length modulation parameter parasitic drain resistance parasitic source resistance gate-junction saturation current gate-junction emission coefficient gate-junction recombination current parameter Isr emission coefficient zero-bias gate-source junction capacitance zero-bias gate-drain junction capacitance gate-junction potential forward-bias junction capacitance coefficient gate P-N grading coefficient Vt0 temperature coefficient Beta exponential temperature coefficient default area for JFET n-JFET p-JFET JK flip flop with asynchronous set and reset JK-FlipFlop jk flip flop with set and reset verilog device JK-FlipFlop w/ SR Component taken from Qucs library name of qucs library file name of component in library Logarithmic Amplifier verilog device scale factor scale factor error % input I1 bias current input reference bias current number of decades conformity error output offset error amplifier input resistance amplifier 3dB frequency Hz amplifier output resistance conformity error temperature coefficient %/Celsius offset temperature coefficient V/Celsius scale factor error temperature coefficient input I1 bias current temperature coefficient A/Celsius input reference bias current temperature coefficient Logarithmic Amplifier I R logic 0 verilog device logic 0 voltage level Logic 0 logic 1 verilog device logic 1 voltage level Logic 1 logical AND n-port AND logical buffer Buffer logical inverter Inverter logical NAND n-port NAND logical NOR n-port NOR logical OR n-port OR logical XNOR n-port XNOR logical XOR n-port XOR MESFET verilog device model selector pinch-off voltage A/(V*V) saturation voltage parameter channel length modulation parameter doping profile parameter power law exponent parameter power feedback parameter 1/W maximum junction voltage limit before capacitance limiting capacitance saturation transition voltage capacitance threshold transition voltage dc drain pull coefficient subthreshold conductance parameter diode saturation current diode emission coefficient built-in gate potential gate-drain junction reverse bias breakdown voltage diode saturation current temperature coefficient transit time under gate channel resistance area factor gate reverse breakdown current energy gap eV zero bias gate-drain junction capacitance zero bias gate-source junction capacitance zero bias drain-source junction capacitance Beta temperature coefficient Alpha temperature coefficient Gamma temperature coefficient Subthreshold slope gate parameter subthreshold drain pull parameter gate-source current equation selector gate-drain current equation selector gate-source charge equation selector gate-drain charge equation selector drain-source charge equation selector Vto temperature coefficient gate resistance Ohms drain resistance source resistance gate resistance temperature coefficient 1/Celsius drain resistance temperature coefficient source resistance temperature coefficient forward bias slope resistance breakdown slope resistance shot noise coefficient MESFET Modular Operational Amplifier verilog device Gain bandwidth product (Hz) Open-loop differential gain at DC (dB) Second pole frequency (Hz) Output resistance (Ohm) Differential input capacitance (F) Differential input resistance (Ohm) Input offset current (A) Input bias current (A) Input offset voltage (V) Common-mode rejection ratio at DC (dB) Common-mode zero corner frequency (Hz) Positive slew rate (V/s) Negative slew rate (V/s) Positive output voltage limit (V) Negative output voltage limit (V) Maximum DC output current (A) Current limit scale factor Modular OpAmp MOS field-effect transistor n-MOSFET p-MOSFET depletion MOSFET zero-bias threshold voltage transconductance coefficient in A/V^2 bulk threshold in sqrt(V) surface potential channel-length modulation parameter in 1/V drain ohmic resistance source ohmic resistance gate ohmic resistance bulk junction saturation current bulk junction emission coefficient channel width channel length lateral diffusion length oxide thickness gate-source overlap capacitance per meter of channel width in F/m gate-drain overlap capacitance per meter of channel width in F/m gate-bulk overlap capacitance per meter of channel length in F/m zero-bias bulk-drain junction capacitance zero-bias bulk-source junction capacitance bulk junction potential bulk junction bottom grading coefficient bulk junction forward-bias depletion capacitance coefficient zero-bias bulk junction periphery capacitance per meter of junction perimeter in F/m bulk junction periphery grading coefficient bulk transit time substrate bulk doping density in 1/cm^3 surface state density in 1/cm^2 gate material type: 0 = alumina; -1 = same as bulk; 1 = opposite to bulk surface mobility in cm^2/Vs drain and source diffusion sheet resistance in Ohms/square number of equivalent drain squares number of equivalent source squares zero-bias bulk junction bottom capacitance per square meter of junction area in F/m^2 bulk junction saturation current per square meter of junction area in A/m^2 drain diffusion area in m^2 source diffusion area in m^2 drain junction perimeter source junction perimeter Use global SPICE temperature MOS field-effect transistor with substrate microstrip corner width of line Microstrip Corner coupled microstrip line spacing between the lines microstrip model microstrip dispersion model Coupled Microstrip Line microstrip cross width of line 3 width of line 4 quasi-static microstrip model show port numbers in symbol or not Microstrip Cross microstrip gap width of the line 1 width of the line 2 spacing between the microstrip ends Microstrip Gap microstrip lange coupler Microstrip Lange Coupler microstrip line Microstrip Line microstrip mitered bend Microstrip Mitered Bend microstrip open microstrip open end model Microstrip Open microstrip radial stub inner radius outer radius feeding line width stub angle Effective dimension Model degrees Microstrip Radial Stub microstrip impedance step width 1 of the line width 2 of the line Microstrip Step microstrip tee temperature in degree Celsius Microstrip Tee microstrip via diameter of round via conductor Microstrip Via two mutual inductors inductance of coil 1 inductance of coil 2 coupling factor between coil 1 and 2 Mutual Inductors three mutual inductors inductance of coil 3 coupling factor between coil 1 and 3 coupling factor between coil 2 and 3 3 Mutual Inductors several mutual inductors number of mutual inductances inductance of coil coupling factor between coil %1 and coil %2 N Mutual Inductors 2to1 multiplexer verilog device 2to1 Mux 4to1 multiplexer verilog device 4to1 Mux 8to1 multiplexer verilog device 8to1 Mux NIGBT verilog device gate-drain overlap area m**2 area of the device MOS transconductance ambipolar recombination lifetime metallurgical base width avalanche uniformity factor avalanche multiplication exponent gate-source capacitance per unit area F/cm**2 gate-drain oxide capacitance per unit area emitter saturation current density A/cm**2 triode region factor electron mobility cm**2/Vs hole mobility base doping 1/cm**3 transverse field factor gate-drain overlap depletion threshold NIGBT correlated current sources current power spectral density of source 1 current power spectral density of source 2 normalized correlation coefficient Correlated Noise Sources voltage power spectral density of source 2 voltage power spectral density of source 1 operational amplifier absolute value of maximum and minimum output voltage OpAmp Optimization optimization 2bit pattern generator verilog device pad output value 2Bit Pattern 3bit pattern generator verilog device 3Bit Pattern 4bit pattern generator verilog device 4Bit Pattern Parameter sweep simulation to perform parameter sweep on parameter to sweep start value for sweep stop value for sweep Simulation step phase shifter Phase Shifter Photodiode verilog device photodiode emission coefficient series lead resistance diode dark current responsivity A/W shunt resistance quantum efficiency light wavelength nm responsivity calculator selector Photodiode Phototransistor verilog device dark current collector series resistance emitter series resistance base series resistance responsivity at relative selectivity=100% relative selectivity polynomial coefficient Phototransistor ac voltage source with phase modulator PM SPICE V(SFFM): offset volage carrier amplitude carrier signal frequency modulation index modulating signal frequency V(SFFM) PM modulated Source Potentiometer verilog device nominal device resistance shaft/wiper arm rotation resistive law taper coefficient device type selector maximum shaft/wiper rotation linearity error wiper arm contact resistance resistance temperature coefficient PPM/Celsius Potentiometer B SPICE T: Characteristic impedance Transmission delay Frequency Normalised length at given frequency Initial voltage at end 1 Initial current at end 1 Initial voltage at end 2 Initial current at end 2 T Rectangular Waveguide widest side shortest side material parameter for temperature model relay threshold voltage in Volts hysteresis voltage in Volts resistance of "on" state in Ohms resistance of "off" state in Ohms Relay resistor ohmic resistance in Ohms first order temperature coefficient second order temperature coefficient temperature at which parameters were extracted (Qucsator only) Resistor Resistor US equation defined RF device type of parameters number of ports representation during DC analysis parameter equation Equation Defined RF Device RF equation defined 2-port RF device Equation Defined 2-port RF Device RLCG transmission line RLCG resistive load Ohm/m inductive load H/m capacitive load conductive load S/m RLCG Transmission Line RS flip flop RS-FlipFlop ac power source port impedance (available) ac power in dBm enable transient model as sine source [true,false] Power Source S parameter simulation calculate noise parameters input port for noise figure output port for noise figure put characteristic values into dataset save subcircuit characteristic values into dataset S-parameter simulation S parameter file name of the s parameter file data type n-port S parameter file 1-port S parameter file 2-port S parameter file file SPICE netlist file SPICE netlist sim spice ERROR: No file name in SPICE component "%1". ERROR: Cannot open SPICE file "%1". ERROR: Cannot save converted SPICE file "%1". ERROR: Cannot open converted SPICE file "%1". Info Preprocessing SPICE file "%1". ERROR: Cannot save preprocessed SPICE file "%1". ERROR: Cannot execute "%1". COMP ERROR: Cannot start QucsConv! Converting SPICE file "%1". subcircuit name of qucs schematic file Subcircuit port of a subcircuit number of the port within the subcircuit type of the port (for digital simulation only) Subcircuit Port substrate definition relative permittivity thickness in meters thickness of metalization specific resistance of metal rms substrate roughness Substrate switch (time controlled) initial state time when state changes (semicolon separated list possible, even numbered lists are repeated) resistance of "on" state in ohms resistance of "off" state in ohms simulation temperature in degree Celsius (Qucsator only) Max possible switch transition time (transition time 1/100 smallest value in 'time', or this number) Resistance transition shape (Qucsator only) Switch ideal symmetrical transformer voltage transformation ratio of coil 1 voltage transformation ratio of coil 2 symmetric Transformer T flip flop with set and reset verilog device T-FlipFlop w/ SR silicon controlled rectifier (SCR) breakover voltage gate trigger current Thyristor ideal transmission line characteristic impedance attenuation factor per length in 1/m Transmission Line ideal 4-terminal transmission line 4-Terminal Transmission Line transient simulation Transient .SENS analysis with Xyce Analysis mode start time in seconds stop time in seconds simulation time step Transient sensitivity analysis number of simulation time steps perform initial DC (set "no" to activate UIC) Transient simulation ideal transformer voltage transformation ratio Transformer triac (bidirectional thyristor) (bidirectional) gate trigger current Triac resonance tunnel diode peak current valley current valley voltage resonance energy in Ws Fermi energy in Ws resonance width in Ws maximum of transmission fitting factor for electron density fitting factor for voltage drop fitting factor for diode current zero-bias depletion capacitance life-time of electrons Tunnel Diode twisted pair transmission line diameter of conductor diameter of wire (conductor and insulator) physical length of the line twists per length in 1/m dielectric constant of insulator Twisted-Pair Symbol file not found: %1 voltage controlled current source forward transconductance Voltage Controlled Current Source voltage controlled voltage source voltage controlled resistor resistance gain Voltage Controlled Resistor Voltage Controlled Voltage Source Verilog file Name of Verilog file verilog ERROR: No file name in %1 component "%2". ERROR: Cannot open %1 file "%2". exponential voltage source voltage before rising edge maximum voltage of the pulse rise time of the rising edge fall time of the falling edge Exponential Voltage Pulse file based voltage source File Based Voltage Source VHDL file Name of VHDL file vhdl generic variable ideal ac voltage source AC voltage source (SPICE) ac Voltage Source ideal dc voltage source dc Voltage Source noise voltage source voltage power spectral density in V^2/Hz Noise Voltage Source voltage probe Voltage Probe ideal voltage pulse source voltage before and after the pulse voltage of the pulse Voltage Pulse ideal rectangle voltage source voltage of high signal voltage of low signal (SPICE only) Rectangle Voltage Locus Curve <invalid> invalid Polar Polar-Smith Combi Smith-Polar Combi 3D-Cartesian Cartesian Smith Chart Admittance Smith no variables wrong dependency no data Tabular Timing Diagram Truth Table ERROR: Cannot open file "%1". ERROR: Cannot create user library subdirectory ! ERROR: Cannot create file "%1". Overwrite File "%1" already exists. Overwrite ? Export to image Inkscape start error! Successfully exported Disk write error! Unsupported format of graphics file. Use PNG, JPEG or SVG graphics! Error: Wrong time format in "%1". Use positive number with units verilog-a user devices lumped components sources probes RF components transmission lines nonlinear components microelectronics verilog-a devices digital components file components simulations equations SPICE components SPICE netlist sections SPICE simulations XSPICE devices Qucs legacy devices diagrams paintings external sim components Edit Properties Export as image power matching noise matching 2-port matching The ground potential cannot be labeled! Arrow Ellipse filled Ellipse Edit Ellipse Properties Elliptic Arc Edit Arc Properties Line Edit Line Properties Text Rectangle filled Rectangle Edit Rectangle Properties Print Document Cannot create output file! Format Error: 'Painting' field is not closed! Wrong document version: Clipboard Format Error: Unknown field! Cannot save C++ file "%1"! Cannot open Verilog-A file "%1"! Cannot save JSON props file "%1"! No valid osdi file. Re-compile verilog-a file first! Cannot save JSON symbol file "%1"! Cannot save document! Format Error: Wrong property field limiter! Format Error: Unknown property: Format Error: Number expected in property field! Format Error: 'Property' field is not closed! Format Error: 'Component' field is not closed! Format Error: Wrong 'wire' line format! Format Error: 'Wire' field is not closed! Format Error: Unknown diagram! Format Error: Wrong 'diagram' line format! Format Error: 'Diagram' field is not closed! Format Error: Wrong 'painting' line delimiter! Format Error: Unknown painting! Format Error: Wrong 'painting' line format! Cannot load document: Wrong document type: Warning Wrong document version Try to open it anyway? File Format Error: Unknown field! ERROR: Component "%1" has no analog model. ERROR: Component "%1" has no digital model. ERROR: Cannot load subcircuit "%1". WARNING: Skipping library component "%1". ERROR: "%1": Cannot load library component "%2" from "%3" WARNING: Ignore simulation component in subcircuit "%1". WARNING: Equations in "%1" are 'time' typed. ERROR: Only one digital simulation allowed. ERROR: Analog and digital simulations cannot be mixed. ERROR: Digital simulation needs at least one digital source. Part list Filter order = %1 Zeros list Pk=Re+j*Im LPF prototype poles list Pk=Re+j*Im Poles list Pk=Re+j*Im High-impedance is %1 ohms, low-impedance is %2 ohms. To get acceptable results it is recommended to use a substrate with lower permittivity and larger height. Quarter wave filters do not allow low-pass nor high-pass masks Cannot save GUI settings in XYCE script XSPICE generic device PortsList .MODEL definition reference XSPICE XSPICE CodeModel: cfunc.mod and ifspec.ifs files pair XSPICE CodeModel XSPICE precompiled CodeModel library Precompiled CM-library XSPICE precompiled CM-library SPICE V(TRRANDOM): Distribution selector (1 to 4) Duration of each random voltage value Time delay before random voltages output ( for time < Td Vout = 0 V) Changes with different values of Type. Changes with different values of Type V(TRRANDOM) SPICE V(TRNOISE): Rms noise amplitude Gaussian) Time step 1/f exponent (0 < alpha < 2) Amplitude (1/f) Trap capture time Trap emission time V(TRNOISE) SPICE V(PWL): Multiple line ngspice or Xyce V specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. V(PWL) SPICE V(AM): ngspice only. voltage amplitude offset voltage modulation frequency carrier frequency signal delay V(AM) SPICE B (V type): Multiple line ngspice or Xyce B specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. B source (V) SPICE library device. You can attach symbol patterns to it. SpiceLibrary file Subcircuit entry (.SUBCKT) name Extra parameters list Pins assignment SPICE library device SPICE generic device Number of pins SPICE device letter .MODEL definition reference (optional) Parameter string (optional) SPICE .spiceinit file .spiceinit .spiceinit contents Spectrum analysis DC .SENS simulation with Xyce Output expressions Reference parameter for .SENS analysis Parameter for DC sweep start value for DC sweep stop value for DC sweep Simulation step for DC sweep DC sensitivity simulation Pole-Zero simulation Two input nodes list (space separated) Two output nodes list (space separated) Transfer function type (current/voltage) Analysis mode (Pole-Zero, Poles only, Zeros only) .PARAM section .PARAM .PARAM Section .OPTIONS section .OPTIONS Xyce option package name .OPTIONS Section Nutmeg equation Nutmeg Nutmeg Equation Noise simulation Node at which the total output is desired Independent source to which input noise is referred. .NODESET section .NODESET .NODESET Section .MODEL section Multiple line ngspice or Xyce .MODEL allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. .MODEL .MODEL Section .LIB directive .LIB .Lib directive .INCLUDE statement .INCLUDE .INCLUDE statement .IC section .IC .IC Section .GLOBAL_PARAM section .GLOBAL_PARAM .GLOBAL PARAM .GLOBAL_PARAM Section .FUNC new function definition .FUNC .FUNC new function Fourier simulation Distortion simulation Second frequency parameter Nutmeg script SPICE I(SFFM): offset current carrier current amplitude I(SFFM) Include script before simulation .INCLUDE SCRIPT Include script SPICE I(TRNOISE): I(TRNOISE) SPICE I(PWL): Multiple line ngspice or Xyce I specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. I(PWL) SPICE I(AM): ngspice only. I(AM) SPICE G (VOL, VALUE, TABLE, POLY): Multiple line ngspice non-linear G specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. G SPICE E (CUR, VALUE, TABLE, POLY): Multiple line ngspice non-linear E specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. E XSPICE core block: seven line XSPICE specification. core PWL controlled voltage source: Seven line XSPICE specification. XAPWL SPICE U(URC): Multiple line ngspice or Xyce U specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. U(URC) S domain transfer function block: Seven line XSPICE specification. SDTF SPICE W: Multiple line ngspice or Xyce W specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. W(CSW) SPICE V: Multiple line ngspice or Xyce V specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. V Source SPICE S: Multiple line ngspice or Xyce S specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. S(SW) SPICE B (I type): Multiple line ngspice or Xyce B specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. B source (I) SPICE I: Multiple line ngspice or Xyce I specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. I Source SPICE R: Multiple line ngspice or Xyce R specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. R Resistor R Resistor 3 pin Q(PNP) BJT: Multiple line ngspice or Xyce Q model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Q(PNP) BJT M(PMOS) MOS: Multiple line ngspice or Xyce M model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. M(PMOS) Z(PMF) MESFET: Multiple line ngspice or Xyce Z model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Z(PMF) J(PJF) JFET: Multiple line ngspice or Xyce J model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. J(PJF) JFET Q(NPN) BJT: Multiple line ngspice or Xyce Q model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Q(NPN) BJT M(NMOS) MOS: Multiple line ngspice or Xyce M model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. M(NMOS) J(NJF) JFET: Multiple line ngspice or Xyce J model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. J(NJF) JFET Unified (M,X,3-,4-pin) MOS: Multiple line ngspice or Xyce M model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. unified MOSFET (3-4 pin) M(NMOS 3 pin) M(PMOS 3 pin) X(NMOS 3 pin) X(PMOS 3 pin) X(NMOS 4 pin) X(PMOS 4 pin) Z(NMF) MESFET: Multiple line ngspice or Xyce Z model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Z(NMF) SPICE L: Multiple line ngspice or Xyce L specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. L Inductor SPICE O(LTRA): O(LTRA) SPICE K: Enter the names of the coupled inductances and their coupling factor. Coupling factor ( 0 < K <= 1) K coupling XSPICE coupled inductor block: two line XSPICE specification. Icouple SPICE D: Multiple line ngspice or Xyce D model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. D Diode D Diode 3 pin SPICE C: Multiple line ngspice or Xyce C specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. C Capacitor C Capacitor 3 pin Q(NPN) 4 pin Q(PNP) 4 pin Q(NPN) 5 pin Q(PNP) 5 pin The schematic name and dataset/display file name is not matching! This may happen if schematic was copied using the file manager instead of using File->SaveAs. Correct dataset and display names automatically? Schematic file: Dataset file: Display file: Open document Not Specified Qucsator Ngspice SpiceOpus Xyce Save netlist Lossy inductor Inductance Quality factor Frequency at which Q is measured Q frequency profile Inductor with Q Lossy capacitor Capacitance Capacitor with Q The load has not resistive part. It cannot be matched using the quarter wavelength method Reactive loads cannot be matched. Only the real part will be matched Chebyshev weighting for N>7 is not available The load is reactive. It cannot be matched using the quarter wavelength method Exponential Tapered line Characteristic impedance at port 1 Characteristic impedance at port 2 Line length Taper weighting Maximum ripple (Klopfenstein taper only) Tapered line Circular Waveguide Printed loop inductor Radius Circular loop Mechanical length of the line Relative permittivity of dielectric Relative permeability of conductor Loss tangent Specific resistance of conductor Simulation temperature in degree Celsius Material parameter for temperature model Port name Input port name: Planar spiral inductor Spiral type Width of line Inner diameter Spacing between turns Number of turns Spiral inductor .CSPARAM section .CSPARAM .CSPARAM Section QucsActiveFilter &File E&xit &View &Console Enables/disables the filter calculation console Console Enables/disables the filter calculation console &Help Help... &About QucsActiveFilter... About Qt... Passband attenuation, Ap (dB) Stopband attenuation, As (dB) Cutoff frequency, Fc (Hz) Stopband frequency, Fs (Hz) Passband ripple Rp(dB) Passband gain, Kv (dB) Filter order Approximation type: Butterworth Chebyshev Inverse Chebyshev Cauer (Elliptic) Bessel Legendre User defined Manually define transfer function Calculate and copy to clipboard Low Pass General filter amplitude-frequency response Unable to implement filter with such parameters and topology Change parameters and/or topology and try again! Filter calculation was successful Filter calculation terminated with error! Filter calculation terminated with error Lower cutoff frequency, Fl (Hz) Copyright (C) 2014, 2015 by Filter topology Filter type: High Pass Band Pass Band Stop Multifeedback (MFB) Sallen-Key (S-K) Cauer section Filter parameters Transfer function and Topology Filter topology preview Filter calculation console Ready. Upper cutoff frequency of band-pass/band-stop filter is less than lower. Unable to implement such filter. Change parameters and try again. Unable to use Cauer section for Chebyshev or Butterworth frequency response. Try to use another topology. Unable to use MFB filter for Cauer or Inverse Chebyshev frequency response. Try to use another topology. Function will be implemented in future version Upper cutoff frequency, Fu (Hz) Transient bandwidth, TW (Hz) Error! Active filter design About... Active Filter synthesis program About Qt QucsApp Schematic Data Display Qucs Documents VHDL Sources Verilog Sources Verilog-A Sources Octave Scripts Spice Files Any File The schematic search path has been refreshed. Verilog VHDL Open file Document opened in read-only mode! Simulation will not work. Please copy the document to the directory where you have write permission! Simulate schematic DC bias simulation mode is not supported for digital schematic! Schematics New Symbol only QucsatorRF found at: You can specify another location later using Simulation->Simulators Setings NOTE: Only QucsatorRF found. This simulator is not recommended for general purpose schematics. Please install Ngspice. Qucs No simulators found automatically. Please specify simulators in the next dialog window. Main Dock Open Delete Projects content of project directory Content content of current project Search Components Clear Components components and diagrams Libraries system and user component libraries Octave Dock Error Cannot open "%1". Library is corrupt. Info Default icon not found: %1.png -port Copying Qucs document The document contains unsaved changes! Do you want to save the changes before copying? &Save Copy file Enter new name: error Cannot rename an open file! Rename file Cannot delete an open file! Warning This will delete the file permanently! Continue ? unknown Verilog source Verilog-A source VHDL source data file data display schematic symbol VHDL configuration configuration Cannot create work directory ! Cannot create project directory ! Choose Project Directory for Opening No project is selected ! Cannot delete file: %1 Search results Search Lib Components Set simulator Ngspice found at: Show model verilog-a user devices Cannot copy file to identical name: %1 Cannot copy schematic: %1 Enter new filename: Cannot rename file: %1 Cannot access project directory: %1 Project directory name does not end in '_prj'(%1) Project: Project directory name does not end in '_prj' (%1) Cannot delete an open project ! This will destroy all the project files permanently ! Continue ? Cannot remove project directory! Choose Project Directory for Deleting No project is selected! Creating new schematic... Ready. Creating new text editor... Opening file... Enter a Schematic Name Opening aborted Saving file... Saving aborted Qucs Netlist SPICE Netlist Plain Text Subcircuit symbol Enter a Document Name The file ' ' already exists! Saving will overwrite the old one! Continue? Cannot overwrite an open document Saving file under new filename... Saving all files... Closing file... Closing Qucs document Do you want to save the changes before closing? untitled Printing... Exiting application... No simulations found. Tuning not possible. Please add at least one simulation. Tuning not possible for digital simulation. Only analog simulation supported. Tuning has no effect without diagrams. Add at least one diagram on schematic. Symbol editing supported only for schematics and Verilog-A documents! Attaching symbols to Verilog-A sources is deprecated and not recommended for new designs. Use SPICE generic device instead. See the documentation for more details. Schematic not saved! Simulation of unsaved schematic not possible. Save schematic first! Simulation of text document is not possible! This action is supported only for SPICE simulators! Save CDL netlist failed! Save Verilog-A module Build Verilog-A module This schematic is not a subcircuit! Use subcircuit to crete Verilog-A module! The document was modified by another program ! Open example… Select example schematic Open example canceled Do you want to reload or keep this version ? Cannot create No page set ! Cannot start "%1"! Could not load S[1,1]. Could not load S[1,2]. Could not load S[2,1]. Could not load S[2,2]. Wrong dependency! Cutting selection... Copying selection to clipboard... At least two elements must be selected ! Opening aborted, file not found. Cannot start text editor! %1 Show netlist Not a schematic tab! Executable %1 not found! (%2) Cannot start %1 program! (%2) Layouting of display pages is not supported! Cannot write netlist! Digital schematic not supported! Layouting of text documents is not supported! Cannot start Qucs-RFLayout: %1 No project open! Select files to copy No files copied. Cannot open "%1" ! Overwrite File "%1" already exists. Overwrite ? Cannot create "%1" ! Cannot read "%1" ! Cannot write "%1" ! Please open project with subcircuits! Please select a diagram graph! Enter an Output File Name CSV file Output file already exists! Overwrite it? Symbol files not found in: %1 Is the project open? Have you saved the Verilog-A symbols? admsXml Compiler admsXml Dock OpenVAF OpenVAF Dock &New Creates a new document New Creates a new schematic or data display document New &Text Ctrl+Shift+V Creates a new text document New Text Creates a new text document &Open... Opens an existing document Open File Opens an existing document Saves the current document Save File Saves the current document Save as... Saves the current document under a new filename Save As Saves the current document under a new filename Save &All Ctrl+Shift+S Saves all open documents Save All Files Saves all open documents &Close Closes the current document Close File Closes the current document Clear Recent &Examples &Edit Circuit Symbol Edits the symbol for this schematic Edit Circuit Symbol Edits the symbol for this schematic &Document Settings... Ctrl+. Document Settings Settings Sets properties of the file &Print... Prints the current document Print File Prints the current document Print Fit to Page... Ctrl+Shift+P Print Fit to Page Print Fit to Page Print and fit content to the page size E&xit Quits the application Exit Quits the application Application Settings... Ctrl+, Application Settings Qucs Settings Sets properties of the application Refresh Search Path... Refresh Search Path Refresh Path Rechecks the list of paths for subcircuit files. Align top Ctrl+T Align top selected elements Align top Align selected elements to their upper edge Align bottom Align bottom selected elements Align bottom Align selected elements to their lower edge Align left Align left selected elements Align left Align selected elements to their left edge Align right Align right selected elements Align right Align selected elements to their right edge Distribute horizontally Distribute equally horizontally Distribute horizontally Distribute horizontally selected elements Distribute vertically Distribute equally vertically Distribute vertically Distribute vertically selected elements Center horizontally Center horizontally selected elements Center horizontally Center horizontally selected elements Center vertically Center vertically selected elements Center vertically Center vertically selected elements Set on Grid Ctrl+U Sets selected elements on grid Set on Grid Sets selected elements on grid Move Component Text Ctrl+K Moves the property text of components Move Component Text Moves the property text of components Replace... Replace component properties or VHDL code Replace Change component properties or text in VHDL code Cu&t Ctrl+X Cuts out the selection and puts it into the clipboard Cut Cuts out the selection and puts it into the clipboard &Copy Copies the selection into the clipboard Copy Copies the selection into the clipboard &Paste Pastes the clipboard contents to the cursor position Paste Pastes the clipboard contents to the cursor position &Delete Deletes the selected components Delete Deletes the selected components Find... Find a piece of text Find Searches for a piece of text Export as image... Exports the current document to an image file Export as image Exports the current document to an image file &Undo Undoes the last command Undo Makes the last action undone &Redo Redoes the last command Redo Repeats the last action once more &New Project... Ctrl+Shift+N Creates a new project New Project Creates a new project &Open Project... Ctrl+Shift+O Opens an existing project Open Project Opens an existing project &Delete Project... Ctrl+Shift+D Deletes an existing project Delete Project Deletes an existing project &Close Project Ctrl+Shift+W Closes the current project Close Project Closes the current project &Add Files to Project... Ctrl+Shift+A Copies files to project directory Add Files to Project Copies files to project directory Create &Library... Ctrl+Shift+L Create Library from Subcircuits Create Library Create Library from Subcircuits S-parameter Viewer Starts S-parameter viewer S-parameter Viewer Starts S-parameter viewer Tune Tuner Allows to live tune variables and show the result in the dataview Save CDL netlist Show Grid (current document) Alt+G Show or hide the grid for the current document. Show / Hide Grid Show or hide the grid for the current document. &About Qt Convert data file Import/Export Data Convert data file to various file formats Export to &CSV... New symbol Creates a new symbol New Creates a new schematic symbol document Starts file chooser dialog to open one of example schematics Examples Start file chooser dialog and open one of example schematics Ctrl+Shift+C Convert graph data to CSV file Export to CSV Convert graph data to CSV file Build Verilog-A module... Run admsXml and C++ compiler Build Verilog-A module Runs amdsXml and C++ compiler Load Verilog-A module... Select Verilog-A symbols to be loaded Load Verilog-A module Let the user select and load symbols View All Show the whole page View All Shows the whole page content Zoom to selection Z Zoom to selected components Zoom to selection Zoom to selected components View 1:1 Views without magnification View 1:1 Shows the page content without magnification Zoom in Zooms into the current view Zoom in Zooms the current view Zoom out Zooms out the current view Zoom out Zooms out the current view Select Activate select mode Select Activates select mode Select All Ctrl+A Selects all elements Select All Selects all elements of the document Select Markers Ctrl+Shift+M Selects all markers Select Markers Selects all diagram markers of the document Rotate Ctrl+R Rotates the selected component by 90� Rotate Rotates the selected component by 90� counter-clockwise Ctrl+W Power combining Ctrl+7 Starts QucsPowerCombining Power combining Starts power combining calculation program Data files converter Ctrl+8 RF Layout Ctrl+9 Starts Qucs-RFLayout View Data Display/Schematic Changes to data display or schematic page Set Diagram Limits Pick the diagram limits using the mouse. Right click for default. Set Diagram Limits Pick the diagram limits using the mouse. Right click for default. Reset Diagram Limits Ctrl+Shift+E Resets the limits for all axis to auto. Reset Diagram Limits Resets the limits for all axis to auto. Simulators Settings... Mirror about X Axis Ctrl+J Mirrors the selected item about X Axis Mirror about X Axis Mirrors the selected item about X Axis Mirror about Y Axis Ctrl+M Mirrors the selected item about Y Axis Mirror about Y Axis Mirrors the selected item about Y Axis Go into Subcircuit Ctrl+I Goes inside the selected subcircuit Go into Subcircuit Goes inside the selected subcircuit Pop out Ctrl+H Pop outside subcircuit Pop out Goes up one hierarchy level, i.e. leaves subcircuit Deactivate/Activate Ctrl+D Deactivate/Activate selected components Deactivate/Activate Deactivate/Activate the selected components Insert Equation Ctrl+< Inserts an equation Insert Equation Inserts a user defined equation Insert Ground Ctrl+G Inserts a ground symbol Insert Ground Inserts a ground symbol Insert Port Inserts a port symbol Insert Port Inserts a port symbol Wire Inserts a wire Wire Inserts a wire Wire Label Ctrl+L Inserts a wire or pin label Wire Label Inserts a wire or pin label VHDL entity Ctrl+Space Inserts skeleton of VHDL entity VHDL entity Inserts the skeleton of a VHDL entity Text Editor Ctrl+1 Starts the Qucs text editor Text editor Starts the Qucs text editor Filter synthesis Ctrl+2 Starts QucsFilter Filter synthesis Starts QucsFilter Active filter synthesis Ctrl+3 Starts QucsActiveFilter Active filter synthesis Starts QucsActiveFilter Line calculation Ctrl+4 Starts QucsTrans Line calculation Starts transmission line calculator Matching Circuit Ctrl+5 Creates Matching Circuit Matching Circuit Dialog for Creating Matching Circuit Attenuator synthesis Ctrl+6 Starts QucsAttenuator Attenuator synthesis Starts attenuator calculation program Simulate Simulates the current schematic Simulate Simulates the current schematic View Data Display/Schematic Changes to data display or schematic page Calculate DC bias Calculates DC bias and shows it Calculate DC bias Calculates DC bias and shows it Save netlist Set Marker on Graph Sets a marker on a diagram's graph Set Marker Sets a marker on a diagram's graph Show Last Messages Shows last simulation messages Show Last Messages Shows the messages of the last simulation Show Last Netlist Shows last simulation netlist Show Last Netlist Shows the netlist of the last simulation Build Verilog-A module from subcircuit &Dock Window Enables/disables the browse dock window Browse Window Enables/disables the browse dock window &Octave Window Shows/hides the Octave dock window Octave Window Shows/hides the Octave dock window Help Index... Index of Qucs Help Help Index Index of intern Qucs help Getting Started... Getting Started with Qucs Getting Started Short introduction into Qucs &About Qucs-S About the application About About the application About Qt About Qt About Qt by Trolltech &File Open Recent &Edit P&ositioning &Insert &Project &Tools Compact modelling &Simulation &View &Help &Technical Papers Open Open Technical &Reports T&utorials File Edit View Work no warnings Warnings in last simulation! Press F5 QucsAttenuator &File &Quit &Help &About About Qt... Topology Input Attenuation: Pin: Freq: Put into Clipboard R4: Copyright (C) 2024 by dB Zin: Zout: Output R1: -- R2: R3: Qucs Attenuator Help QucsAttenuator is an attenuator synthesis program. To create a attenuator, simply enter all the input parameters and press the calculation button. Immediately, the schematic of the attenuator is calculated and put into the clipboard. Now go to Qucs, open an schematic and press CTRL-V (paste from clipboard). The attenuator schematic can now be inserted. Have lots of fun! About Qt About... Attenuator synthesis program Copyright (C) 2006 by Error: Set Attenuation less than %1 dB QucsFilter &File E&xit &Help Help... &About QucsFilter... About Qt... Filter Realization: Filter type: Filter class: Low pass High pass Band pass Band stop Order: Corner frequency: Stop frequency: Stop band frequency: Pass band ripple: Stop band attenuation: Impedance: Microstrip Substrate Relative permittivity: Substrate height: metal thickness: minimum width: maximum width: Calculate and put into Clipboard About... Filter synthesis program Copyright (C) 2005, 2006 by About Qt Result: Error Stop frequency must be greater than start frequency. Filter order must not be less than two. Bessel filter order must not be greater than 19. Successful Result: -- Start frequency: Pass band frequency: Pass band attenuation: QucsPowerCombiningTool Ready! Use CTRL+V to paste the schematic Error! The network could not be generated Bagley Tree combiner QucsSettingsDialog Edit Qucs Properties Large font size: Document Background Color: Language (set after reload): system language English German French Spanish Italian Polish Romanian Japanese Swedish Hungarian Hebrew Portuguese-BR Portuguese-PT Turkish Ukrainian Russian Czech Catalan Arabic Chinese Schematic font (set after reload): Application font (set after reload): Kazakh Maximum undo operations: Text editor: Set to qucs, qucsedit or the path to your favorite text editor. Start wiring when clicking open node: Load documents from future versions: Try to load also documents created with newer versions of Qucs. Draw diagrams with anti-aliasing feature: Draw text with anti-aliasing feature: Use anti-aliasing for graphs for a smoother appearance. Text document font (set after reload): Use anti-aliasing for text for a smoother appearance. Show trace name prefix on diagrams: Show prefixes for trace names on diagrams like "ngspice/" Settings Grid Color (set after reload): Default graph line thickness: App Style: Appearance Colors for Syntax Highlighting: Comment String Integer Number Real Number Character Data Type Attribute Directive Task Source Code Editor Register filename extensions here in order to open files with an appropriate program. Suffix Program Suffix: Program: Set Remove File Types Edit the standard paths and external applications Qucs Home: Browse AdmsXml Path: ASCO Path: Octave Path: OpenVAF Path: RF Layout Path: Subcircuit Search Path List Add Path Add Path With SubFolders Remove Path Locations OK Apply Cancel Default Values Error This suffix is already registered! Select the home directory Select the admsXml bin directory Select the ASCO bin directory Select the octave executable Select the OpenVAF executable Select the Qucs-RFLayout executable Select a directory QucsTranscalc &File &Load Ctrl+L &Save Ctrl+S &Options Ctrl+O &Quit &Execute &Copy to Clipboard &Analyze &Synthesize &Help About Transmission Line Type Microstrip Line Coplanar Waveguide Grounded Coplanar Rectangular Waveguide Coaxial Line Coupled Microstrip Stripline Substrate Parameters Component Parameters Physical Parameters Analyze Derive Electrical Parameters Synthesize Compute Physical Parameters Electrical Parameters Calculated Results Ready. ErEff Conductor Losses Dielectric Losses Skin Depth TE-Modes TM-Modes ErEff Even ErEff Odd Conductor Losses Even Conductor Losses Odd Dielectric Losses Even Dielectric Losses Odd Relative Permittivity Relative Permeability Height of Substrate Height of Box Top Strip Thickness Strip Conductivity Dielectric Loss Tangent Conductor Roughness Frequency Line Width Line Length Characteristic Impedance Electrical Length Gap Width Conductivity of Metal Magnetic Loss Tangent Width of Waveguide Height of Waveguide Waveguide Length Inner Diameter Outer Diameter Length Even-Mode Impedance Odd-Mode Impedance Conductor thickness Substrate height Width Selected for Calculation Check item for Calculation About... Transmission Line Calculator for Qucs Copyright (C) 2001 by Gopal Narayanan Copyright (C) 2002 by Claudio Girardi Copyright (C) 2005 by Stefan Jahn Copyright (C) 2008 by Michael Margraf Values are consistent. Failed to converge! Values are inconsistent. Loading file... Enter a Filename Transcalc File Error Cannot load file: Loading aborted. Saving file... Cannot save file: Saving aborted. Schematic copied into clipboard. Transmission line type not available. Qucs_S_SPAR_Viewer &File &Quit &Open session file &Save session as ... &Save session &Help &About About Qt... Qucs-S S-parameter Help This is a simple viewer for S-parameter data. It can show several .snp files at a time in the same diagram. Trace markers can also be added so that the user can read the trace value at at an specific frequency. About Qt About... Copyright (C) 2024 by S-Parameter Files (*.s1p *.s2p *.s3p *.s4p);;All Files (*.*) Warning This file is already in the dataset. This trace is already shown The display contains no traces. Error Nothing to save: No data was loaded. Save session Qucs-S snp viewer session (*.spar); Open S-parameter Viewer Session SaveDialog Save the modified files Select files to be saved Modified Files Abort Closing Don't Save Save Selected Untitled Schematic Title Drawn By: Date: Revision: Edit Schematic Edits the schematic Edit Schematic Edits the schematic Edit Circuit Symbol Edits the symbol for this schematic Edit Circuit Symbol Edits the symbol for this schematic generic Error Program admsXml not found: %1 Set the admsXml location on the application settings. Status Netlist error S2Spice warning ERROR: Cannot create library file "%s". SearchDialog Dialog Text to search for Text to replace with Ask before replacing Case sensitive Whole words only Search backwards Next Close Replace Text Search Text SettingsDialog Edit File Properties Data Set: Browse Data Display: open data display after simulation Octave Script: run script after simulation Simulation show Grid horizontal Grid: vertical Grid: Grid no Frame DIN A5 landscape DIN A5 portrait DIN A4 landscape DIN A4 portrait DIN A3 landscape DIN A3 portrait Letter landscape Letter portrait Frame OK Apply Cancel SimMessage Qucs Simulation Messages Progress: Errors and Warnings: Goto display page Abort simulation Starting new simulation on %1 at %2 creating netlist... Error Cannot read netlist! ERROR: Simulator is still running! ERROR: Cannot write netlist file! ERROR: Cannot simulate a text file! ERROR: Cannot open SPICE file "%1". SIM ERROR: Cannot start QucsConv! done. ERROR: Cannot create VHDL directory "%1"! ERROR: Cannot create "%1"! ERROR: Cannot start Starting ERROR: Simulator crashed! Please report this error to qucs-bugs@lists.sourceforge.net Close window Simulation ended on %1 at %2 Ready. Errors occurred during simulation on %1 at %2 Aborted. Output: ------- Errors and Warnings: -------------------- Simulation aborted by the user! SimSettingsDialog Ngspice executable location Xyce executable location SpiceOpus executable location Qucsator executable location Apply changes Cancel Select ... Ngspice compatibility mode Ngspice CLI parameters Xyce CLI parameters SpiceOpus CLI parameters SPICE settings Qucsator settings Setup simulators executable location Select Ngspice executable location Select Xyce executable location Select SpiceOpus executable location Select Qucsator executable location SpiceDialog Edit SPICE Component Properties Name: Browse File: Set SPICE parameters string as a plain text. Example: V0=1.0 I0=2.0 Show SPICE parameters: show file name in schematic Edit include SPICE simulations preprocessor SPICE net nodes: Component ports: Add >> << Remove OK Apply Cancel Select a file SPICE netlist All Files Info Preprocessing SPICE file "%1". Error Cannot save preprocessed SPICE file "%1". Cannot execute "%1". SPICE Preprocessor Error Converting SPICE file "%1". QucsConv Error SpiceFile Converting SPICE file "%1". SpiceLibCompDialog Open Automatic symbol Symbol from template Symbol from file Show OK Apply Cancel No symbol files found at the following path: Check you installation! SPICE model Edit SPICE library device Failed open file: SPICE library parse error. No SUBCKT directive found in library SPICE library parse error Error Failed to open file: No symbol loaded Failed to load symbol file! Open SPICE library SPICE files (*.cir +.ckt *.sp *.lib) Open symbol file Schematic symbol (*.sym) Warning All pins must be assigned Set a valid symbol file name There were library file parse error! Cannot apply changes. SweepDialog Bias Points Close SymbolWidget Symbol: ! Drag n'Drop me ! Warning: Symbol '%1' missing in Qucs Library. Drag and Drop may still work. Please contact the developers. Error Cannot open "%1". Library is corrupt. TextBoxDialog Component: Apply Cancel OK Editor TextDoc Edit Text Symbol Edits the symbol for this text document Edit Text Symbol Edits the symbol for this text document VHDL entity Inserts skeleton of VHDL entity VHDL entity Inserts the skeleton of a VHDL entity Verilog module Inserts skeleton of Verilog module Verilog module Inserts the skeleton of a Verilog module Octave function Inserts skeleton of Octave function Octave function Inserts the skeleton of a Octave function Find... Cannot find target: %1 Replace... Replace occurrence ? TransferFuncDialog Define filter transfer function Numerator b[i]= Denominator a[i]= a[i] b[i] Accept Cancel TunerDialog Tuner Close Update Values Reset Values Please select a component to tune Add component Adding components from different schematics is not supported! VASettingsDialog Document Settings Code Creation Settings Browse Output file: Recreate Icon description: Description: unspecified device NPN/PNP polarity NMOS/PMOS polarity analog only digital only both Ok Cancel PNG files Any file Enter an Icon File Name fillFromSpiceDialog Insert .MODEL text here OK Cancel Convert number notation Import SPICE model No .MODEL directive found Device type doesn't match the model type. Model found: Models expected: SPICE model parse error Subcircuit model (.SUBCKT) found Modelcard (.MODEL) expected Model LEVEL=%1 is not allowed for unified MOS device Use red SPICE device from Microelectronics group Allowed LEVELS are: 1,2,3,4,5,6,9 Error main display this help and exit convert Qucs schematic into netlist print Qucs schematic to file (eps needs inkscape) set print page size (default A4) set dpi value (default 96) set color mode (default RGB) set orientation (default portraid) use file as input schematic use file as output netlist create Ngspice netlist create CDL netlist Xyce netlist execute Ngspice/Xyce immediately create component icons under ./bitmaps_generated dump data for documentation: * file with of categories: categories.txt * one directory per category (e.g. ./lumped components/) - CSV file with component data ([comp#]_data.csv) - CSV file with component properties. ([comp#]_props.csv) list component entry formats for schematic and netlist write netlist to console tunerElement Max.: Min.: Val.: Step ERROR Entered step is not correct Value not correct