AboutDialog About Qucs Version Copyright (C) GUI programmer, Verilog-A dynamic loader project maintainer, simulator interface and GUI design component models, documentation Xyce integration Testing, examples Qt6 support, general improvements Digital simulation, general improvements CI setup, build system, MacOS support testing, general bugfixes testing, modelling and documentation, tutorial contributor testing, modelling, Octave. bondwire and rectangular waveguide model implementation GUI programmer, release filter synthesis (qucs-activefilter), SPICE integration (NGSPICE, Xyce) testing, general fixes refactoring, modularity RF design tools Schematic rendering engine, refactoring Documentation Refactoring, general improvements founder of the project, GUI programmer Programmer of simulator webpages and translator tester and applyer of Stefan's patches, author of documentation coplanar line and filter synthesis code, documentation contributor some filter synthesis code and attenuator synthesis GUI programmer, Qt4 porter programmer of the Verilog-AMS interface equation solver contributions, exponential sources, author of documentation temperature model for rectangular waveguide GUI programmer German by Polish by Romanian by French by Portuguese by Spanish by Japanese by Italian by Hebrew by Swedish by Turkish by Hungarian by Russian by Czech by Catalan by Ukrainian by Arabic by Kazakh by Chinese by Home Page Documentation start page Bugtracker page Forum Qucs-S project team: Based on Qucs project developed by: Authors Translations Support License &OK 确定 Previous Developers GUI translations : AbstractSpiceKernel Simulate 仿真 Failed to create dataset file 无法创建数据集文件 Check write permission of the directory 检查目录的写入权限 ArrowDialog Edit Arrow Properties 编辑箭头属性 Head Length: 头宽度 Head Width: 头宽度 Line color: 线颜色 Line Width: 线宽 Line style: 线型 solid line 实线 dash line 虚线 dot line 点线 dash dot line 点划线 dash dot dot line 两点划线 Arrow head: 箭头 two lines 双线 filled 已填充 OK 确定 Cancel 取消 AuxFilesDialog Select 选择 Cancel 取消 ChangeDialog Change Component Properties 改变元件属性 Components: 元件 all components 所有元件 resistors 电阻 capacitors 电容 inductors 电感 transistors 晶体管 Component Names: 元件名 Property Name: 属性名 New Value: 新值 Replace 替换 Cancel 取消 Error 错误 Regular expression for component name is invalid. 无效的元件名正则表达式 Found Components 找到的元件 Change properties of 更改属性 these components ? 是这些元件吗？ Yes 确定 ComponentDialog Edit Component Properties 编辑元件属性 Equation Editor Put result in dataset Sweep 扫描 display in schematic 在原理图中显示 Simulation: 仿真 Sweep Parameter: 参数扫描 Type: 类型 linear 线型 logarithmic 指数型 list 列表 constant 常数 Values: 值 Start: 开始值 Stop: 结束值 Step: 步进值 Number: 点数 Properties 属性 Name: 名称： Name 名称 Simulation 仿真 Sweep Parameter Type 类型 Values Start Stop 停止 Step Step Number Populate parameters from SPICE file... Value 值 Show display 显示 Description 描述 Edit 编辑 Browse 浏览 Add 添加 Remove 删除 Move Up 上移 Move Down 下移 OK 确定 Apply 应用 Cancel 取消 yes 是 no 否 Select a file 选择文件 All Files 所有文件 Touchstone files S参数文件 CSV files CSV文件 SPICE files SPICE文件 VHDL files VHDL文件 Verilog files Verilog文件 Points per decade: 每十倍频程的点数： CustomSimDialog Edit SPICE code 编辑SPICE代码 Component: 元件： display in schematic 在原理图中显示 Variables to plot (semicolon separated) 要绘制的变量(以分号作为分隔符) Extra outputs (semicolon separated; raw-SPICE or XYCE-STD format) 额外输出(分号分隔;raw-SPICE或XYCE-STD格式) Extra outputs (semicolon separated; raw-SPICE or XYCE-STD or scalars print format) Apply 应用 Cancel 取消 OK 确定 Find all variables 查找所有变量 Find all outputs 查找所有输出 SPICE code editor SPICE代码编辑器 DiagramDialog Edit Diagram Properties 编辑图表属性 left Axis 左轴 right Axis 右轴 y-Axis Y轴 smith Axis 史密斯圆图坐标轴 polar Axis 极轴 z-Axis Z轴 Graph Input 图表输入 Plot Vs. Plot Vs. Number Notation: 数字表示法： real/imaginary 实部/虚部 magnitude/angle (degree) 幅度/角度(角度制) magnitude/angle (radian) 幅度/角度(弧度制) Precision: 精度 Color: 颜色 Style: 风格 solid line 实线 dash line 虚线 dot line 点线 long dash line 长虚线 stars 星形 circles 圆形 arrows 箭头 Thickness: 粗细 y-Axis: Y轴 Dataset 数据设置 Data from simulator: 仿真数据： Name 名称 Type 类型 Size 尺寸 Graph 图表 New Graph 新图表 Delete Graph 删除图表 Data 数据 x-Axis Label: X轴标签 Label: 标签 <b>Label text</b>: Use LaTeX style for special characters, e.g. \tau <b>Label text</b>:特殊字符请使用 LaTeX，如 \tau show Grid 显示网格 Grid Color: 网格颜色 Grid Style: 网格风格 dash dot line 点划线 dash dot dot line 两点划线 Number notation: 数字表示法： scientific notation 科学计数法 engineering notation 工程计数法 logarithmic X Axis Grid 对数X轴刻度 logarithmical X Axis Grid 对数X轴刻度 logarithmical 对数 Grid 网格 logarithmic 对数 hide invisible lines 隐藏不可见的线 Rotation around x-Axis: 绕x轴旋转： Rotation around y-Axis: 绕y轴旋转： Rotation around z-Axis: 绕z轴旋转： 2D-projection: 2D投影 Properties 属性 x-Axis X轴 manual 手动 start 开始值 step 步进值 stop 结束值 number 点数 Limits 限制值 OK 确定 Apply 应用 Cancel 取消 DigiSettingsDialog Document Settings 文档设置 Digital Simulation Settings 数字电路仿真设置 Simulation 仿真 Duration of Simulation: 仿真持续时间： Precompile Module 预编译模块 Library Name: 元件库名 Libraries: 元件库 Ok 确定 Cancel 取消 Error 错误 DisplayDialog Analogue 模拟 VHDL VHDL Verilog Verilog SPICE SPICE Qucs Qucs Close 关闭 ExportDialog Export graphics 导出图像 Save to file (Graphics format by extension) 保存到文件(图像格式由扩展名决定) Height in pixels 高度像素值 Scale factor: 缩放比例 Image format: 图像格式 Export 导出 Cancel 取消 Width in pixels 宽度像素值 Browse 浏览 Colour 颜色 Monochrome 单色 Grayscale 灰度图 Original width to height ratio 原始宽高比 Original size 原始尺寸 Export selected only 只导出已选部分 Export schematic to raster or vector image 导出原理图为位图或矢量图 Export Schematic to Image 导出原理图为图像 Export diagram to raster or vector image 导出图表为位图或矢量图 ExternSimDialog Stop 停止 Save netlist 保存网表 Exit 退出 Simulation console 在控制台中仿真 Simulate with external simulator 使用外部仿真器仿真 There were simulation errors. Please check log. 仿真出错，请检查日志 There were simulation warnings. Please check log. Simulation finished. Now place diagram on schematic to plot the result. Simulation successful. Now place diagram on schematic to plot the result. 仿真成功，请将图表放在原理图上以绘制结果 started... 启动... Simulation started on: 仿真开始于： Failed to start simulator! 无法启动仿真器！ Simulator crashed! 仿真器崩溃！ Simulator error! 仿真器错误！ error... 错误... FillDialog Line Width: 线宽 Line Color: 线颜色 Line Style: 线型 solid line 实线 dash line 虚线 dot line 点线 dash dot line 点划线 dash dot dot line 两点划线 Line Style 线型 enable filling 启用填充功能 Fill Color: 填充颜色 Fill Style: 填充风格 no filling 不填充 solid 纯色 dense 1 (densest) 密度 1 dense 2 密度 2 dense 3 密度 3 dense 4 密度 4 dense 5 密度 5 dense 6 密度 6 dense 7 (least dense) 密度 7 horizontal line 水平线 vertical line 垂直线 crossed lines 交叉线 hatched backwards 左斜线 hatched forwards 右斜线 diagonal crossed 交叉线 Filling Style 填充样式 OK 确定 Cancel 取消 FilterDialog E&xit 退出 &About Qucs Filter... 关于Qucs Filter About Qt... 关于Qt Cutoff/Center 截止频率/中心频率 Hz Hz kHz kHz MHz MHz GHz GHz Ripple 纹波 dB dB Angle 角度 Ohm Ω Bandwidth 带宽 Attenuation 衰减 dual 双 Optimize C C 最佳值 Cmin C 最小值 Cmax C 最大值 noC 忽略 C Optimize L L 最佳值 Lmin L 最小值 Lmax L 最大值 noL 忽略 L LC Filters LC 滤波器 Microstrip Filters 微带线滤波器 Active Filters 有源滤波器 Exit 退出 Calculate 计算 About... 关于 Filter synthesis program 滤波器综合程序 About Qt 关于Qt GraphicTextDialog Edit Text Properties 编辑文本属性 Use LaTeX style for special characters, e.g. \tau 特殊字符使用LaTeX风格，如\tau Use _{..} and ^{..} for sub- and super-positions. 使用 _{..} 和 ^{..} 用于下标和上标 &OK 确定 &Cancel 取消 Text color: 文字颜色 Text size: 字号： Rotation angle: 旋转角度： Error 错误 The text must not be empty! 该段文字不能为空 HelpDialog QucsActiveFilter is a active filter synthesis program. Butterworth, Chebyshev, Inverse Chebyshev, Cauer, Bessel and User defined transfer function are supported.To create a filter, simply enter all parameters and press the big button at the bottom of the main window. Immediatly, the schematic of the filter is calculated and put into the clipboard. Now go to Qucs, open an empty schematic and press CTRL-V (paste from clipboard). The filter schematic can now be inserted and simulated. Have lots of fun! QucsActiveFilter可生成巴特沃斯、切比雪夫、反切比雪夫、椭圆、贝赛尔以及用户自定义的各种有源滤波器。输入参数并点击窗口下方的按钮即可生成有源滤波器。与此同时，生成的滤波器自动保存于剪切板中。在Qucs中打开一个空原理图文件并按下Ctrl-V(从剪切板中粘贴热键)，滤波器电路就被拷贝至该原理图中了。 QucsFilter is a filter synthesis program. To create a filter, simply enter all parameters and press the big button at the bottom of the main window. Immediately, the schematic of the filter is calculated and put into the clipboard. Now go to Qucs, open an empty schematic and press CTRL-V (paste from clipboard). The filter schematic can now be inserted and simulated. Have lots of fun! QucsFilter是一个滤波器合成程序。输入参数并点击窗口下方的按钮即可生成有源滤波器。与此同时，生成的滤波器自动保存于剪切板中。在Qucs中打开一个空原理图文件并按下Ctrl-V(从剪切板中粘贴热键)，滤波器电路就被拷贝至该原理图中了。 Close 关闭 Help 帮助 QucsTranscalc is an analysis and synthesis tool for calculating the electrical and physical properties of different kinds of RF and microwave transmission lines. QucsTranscalc是用于分析与生成RF与微波电路中各种传输线的电参数和物理参数的工具 For each type of transmission line, using dialog boxes, you can enter values for the various parameters, and either calculate its electrical properties, or use the given electrical requirements to synthesize physical parameters of the required transmission line. 对于每种类型的传输线，您可以使用对话框输入各种参数的值，并计算其电气特性，或使用给定的电气要求来合成所需传输线的物理参数。 Dismiss 关闭 QucsActiveFilter is a active filter synthesis program. Butterworth, Chebyshev, Inverse Chebyshev, Cauer, Bessel and User defined transfer function are supported.To create a filter, simply enter all parameters and press the big button at the bottom of the main window. Immediately, the schematic of the filter is calculated and put into the clipboard. Now go to Qucs, open an empty schematic and press CTRL-V (paste from clipboard). The filter schematic can now be inserted and simulated. Have lots of fun! QucsActiveFilter可生成巴特沃斯、切比雪夫、反切比雪夫、椭圆、贝赛尔以及用户自定义的各种有源滤波器。输入参数并点击窗口下方的按钮即可生成有源滤波器。与此同时，生成的滤波器自动保存于剪切板中。在Qucs中打开一个空原理图文件并按下Ctrl-V(从剪切板中粘贴热键)，滤波器电路就被拷贝至该原理图中了。 ID_Dialog Edit Subcircuit Properties 编辑子电路属性 Prefix: 前缀： Parameters 参数 display 显示 Name 名称 Default 默认 Description 描述 Type 类型 yes 是 no 否 display in schematic 在原理图中显示 Name: 名称： Default Value: 默认值： Description: 描述： Type: 类型 Add 添加 Remove 删除 OK 确定 Apply 应用 Cancel 取消 Error 错误 Parameter must not be named "File"! 参数不能命名为"File"！ Parameter "%1" already in list! 参数"%1"已在列表中！ ImportDialog Convert Data File... 转换数据文件 File specification 指定文件 Input File: 输入文件： Browse 浏览 Output File: 输出文件： Output Data: 输出数据： Qucs dataset Qucs数据集 Touchstone Touchstone CSV CSV Input Format: SPICE netlist SPICE网表 VCD dataset Citi ZVR MDL Output Format: Qucs library Qucs library Qucs netlist Qucs netlist Matlab Matlab Library Name: 元件库名 Messages 消息 Convert 转换 Abort 中止 Close 关闭 All known 所有已知的文件类型 Touchstone files S参数文件 CSV files CSV文件 CITI files CITI文件 ZVR ASCII files ZVR ASCII文件 IC-CAP model files IC-CAP model文件 VCD files VCD文件 Qucs dataset files Qucs dataset文件 SPICE files SPICE文件 Any file 任何文件 Error 错误 Cannot open file: Enter a Data File Name 输入数据文件名 Qucsator netlist Info 信息 Output file already exists! 输出文件已存在！ Overwrite it? 要覆盖它吗？ ERROR: Unknown file format! Please check file name extension! 错误：未知的文件格式！请检查文件扩展名！ Running command line: 运行命令行： ERROR: Cannot start converter! 错误：无法启动转换器！ Successfully converted file! 文件转换成功！ Converter ended with errors! 转换器以错误结束！ LabelDialog Insert Nodename 插入节点 Enter the label: 输入节点标签： Initial node voltage: 节点初始电压： Less... Less... Ok 确定 Cancel 取消 More... 更多 SPICE checker SPICE检查器 Node name "%1" is Nutmeg reserved keyword! Please select another node name! Node name will not be changed. 节点名称"%1"是保留的关键字！ 请选择其它的节点名称！ 节点名称将不会被更改 LibraryDialog Create Library 新建元件库 Library Name: 元件库名 Choose subcircuits: 选择子电路 Add subcircuit description 添加子电路描述 Analog models only Select All 全选 Deselect All 取消全选 Cancel 取消 Next >> 下一个 >> Enter description for: 描述的对象： Description: 描述： Previous 上一个 Create 创建 Message: 信息： Close 关闭 No projects! 没有项目！ Error 错误 Please insert a library name! 请插入库名称！ Please choose at least one subcircuit! 请至少选择一个子电路！ Warning 警告 Cannot create user library directory ! 无法创建用户库目录！ A library with this name already exists! Rewrite? A system library with this name already exists! 相同名称的系统库文件已存在 A library with this name already exists! 相同名称的库文件已存在 Next... 下一个... Saving library... 保存库... Error: Cannot create library! 错误：无法创建库文件 Loading subcircuit "%1". 加载子电路"%1" Error: Cannot load subcircuit "%1". 错误：无法加载子电路"%1" Creating Qucs netlist. 创建Qucs网表 Error: Cannot create netlist for "%1". 错误：无法创建网表"%1". Creating SPICE netlist. 创建SPICE网表. Creating Verilog netlist. 创建Verilog网表. Creating VHDL netlist. 创建VHDL网表. Error creating library. 创建库时遇到了错误 Successfully created library. 已成功创建库 Delete 删除 Rename 重命名 LoadDialog Load Verilog-A symbols 加载Verilog-A符号 Choose Verilog-A symbol files: 选择Verilog-A符号文件： Select All 全选 Deselect All 取消全选 Cancel 取消 Ok 确定 Change Icon 改变图标 auto-load selected 已选择auto-load Load the selected symbols when opening the project. 打开项目时加载选定的符号 Info 信息 Icon not found: %1.png 找不到图标： %1.png Open File 打开文件 Icon image (*.png) Icon image (*.png) Error 错误 File not found: %1 找不到文件：%1 MarkerDialog Edit Marker Properties 编辑标记属性 Precision: 精度： real/imaginary 实部/虚部 magnitude/angle (degree) 幅度/角度(角度制) magnitude/angle (radian) 幅度/角度(弧度制) Number Notation: 数字表示法： X-axis position: X轴位置： Off Square Triangle Marker Indicator Z0: Z0： transparent 透明 OK 确定 Cancel 取消 MatchDialog Create Matching Circuit 创建匹配网络 calculate two-port matching 计算二端口匹配 Reference Impedance 参考阻抗 Port 1 Port 1 ohms Ω Port 2 Port 2 S Parameter S Parameter Input format 输入格式 real/imag 实部/虚部 Implementation Microstrip Substrate 微带线基底 Relative Permitivity Substrate height 基板高度 Metal thickness Minimum width Maximum width tanD Resistivity Method L-section Single stub Double stub Multistage Open stub Short circuit stub Number of sections Weighting Binomial Chebyshev Chebyshev Maximum ripple Use balanced stubs Calculate two-port matching Add S-Parameter simulation Synthesize microstrip lines Real/Imag mag/deg mag/deg S11 S11 S21 S21 S12 S12 S22 S22 Frequency: 频率： Create 创建 Cancel 取消 Reflexion Coefficient 反射系数 Impedance (Ohms) The device is not unconditionally stable: K = %1 |%2| = %3 It is not possible to synthesize a matching network. Consider adding resistive losses and/or feedback to reach unconditional stability (K > 1 and |%2| < 1) It is not possible to match this load using the double stub method Impedance (ohms) 阻抗(Ω) Error 错误 Real part of impedance must be greater zero, but is %1 ! 阻抗的实部必须大于零， 但 是 %1 ！ MessageDock admsXml admsXml Compiler Compiler admsXml Dock admsXml Dock MyWidget E&xit 退出 About... 关于 About Qt 关于Qt NewProjDialog Create new project 创建新项目 Project name: 项目名称： open new project 打开新项目 Create 创建 Cancel 取消 Ngspice Problem with SaveNetlist 保存网表时出现了位图 OctaveWindow ERROR: Failed to execute "%1" 错误：无法执行"%1" OptimizeDialog Edit Optimization Properties 编辑优化属性 Name: 名称： Simulation: 仿真 General 常规 Method: 方法： Maximum number of iterations: 最大迭代次数： Output refresh cycle: 输出刷新周期： Number of parents: 父级数： Constant F: 常数F: Crossing over factor: 重叠因子： Pseudo random number seed: 伪随机数种子： Minimum cost variance: 最小代价方差： Cost objectives: 代价目标： Cost constraints: 代价约束： Algorithm 算法 Name 名称 active 激活 initial 初始 min 最小 max 最大 Type 类型 initial: 初始： min: 最小: max: 最大: linear double 线性双精度 logarithmic double 对数双精度 linear integer 线性整数 logarithmic integer 对数整数 E3 series E3系列 E6 series E6系列 E12 series E12系列 E24 series E24系列 E48 series E48系列 E96 series E96系列 E192 series E192系列 Add 添加 Delete 删除 Type: 类型 Copy current values to equation 将电流值复制到方程式中 Variables 变量 Value 值 Value: 值： minimize 最小化 maximize 最大化 less 少于 greater 多于 equal 等于 monitor 监视 Goals 目标 OK 确定 Apply 应用 Cancel 取消 yes 是 no 否 Error 错误 Every text field must be non-empty! 每个文本字段必须为非空！ Variable "%1" aleardy in list! 变量"%1" 已经在列表中！ Goal "%1" already in list! 目标"%1" 已经在列表中！ Set precision 设置精度 Precision: 精度 OptionsDialog Options 选项 Units 单位 Frequency 频率 Length 长度 Resistance 电阻 Angle 角度 Save as Default 保存作为默认值 Dismiss 关闭 PackageDialog Create Project Package 创建项目包 Package: 包 Browse 浏览 include user libraries 包括用户库 Choose projects: 选择项目： Create 创建 Cancel 取消 No projects! 没有项目！ Extract Project Package 提取项目包 Close 关闭 Qucs Packages Qucs包 Any File 任何文件 Enter a Package File Name 输入包文件名 Error 错误 Cannot open "%1"! 无法打开"%1"！ Please insert a package name! 请输入包的名称！ Please choose at least one project! 请选择至少一个项目 Info 信息 Output file already exists! 输出文件已存在！ Overwrite it? 要覆盖它吗？ Cannot create package! 无法创建包！ Successfully created Qucs package! 成功创建Qucs包！ ERROR: Cannot open package! 错误：无法打开包！ ERROR: File contains wrong header! 错误：文件包含错误的标头！ ERROR: Wrong version number! 错误：版本号错误！ ERROR: Checksum mismatch! 错误：校验和不匹配！ Leave directory "%1" 离开目录"%1" ERROR: Package is corrupt! 错误：包已损坏！ Successfully extracted package! 成功解压包！ ERROR: Project directory "%1" already exists! 错误：项目目录"%1"已存在！ ERROR: Cannot create directory "%1"! 错误：无法创建目录"%1"！ Create and enter directory "%1" 创建并输入目录"%1" ERROR: Cannot create file "%1"! 错误：无法创建文件"%1"！ Create file "%1" 创建文件"%1" ERROR: User library "%1" already exists! 错误：用户库"%1"已存在！ ERROR: Cannot create library "%1"! 错误：无法创建库"%1"！ Create library "%1" 创建库"%1" ProjectView Content of %1 Content of %1 Note Note Datasets Datasets Data Displays Data Displays Verilog Verilog Verilog-A Verilog-A VHDL VHDL Octave Octave Schematics Schematics Symbols SPICE SPICE XSPICE XSPICE Others Others -port -端口 QObject ac simulation 交流仿真 AC sensitivity simulation 交流灵敏度仿真 Output variable 输出变量 sweep type 扫描类型 start frequency in Hertz 开始频率(Hz) stop frequency in Hertz 停止频率(Hz) number of simulation steps 仿真点数 calculate noise voltages 计算噪声电压 ac voltage source with amplitude modulator 带调幅器的交流电压源 AM AM peak voltage in Volts 峰值电压(V) frequency in Hertz 频率(Hz) initial phase in degrees 初始相位(deg) offset voltage (SPICE only) delay time (SPICE only) modulation level 调制电平 AM modulated Source AM调置源 ideal ac current source 理想交流电流源 peak current in Ampere 峰值电流(A) offset current (SPICE only) damping factor (transient simulation only) 阻尼系数(仅限瞬态模拟) ac Current Source 交流电流源 ideal dc current source 理想直流电流源 current in Ampere 电流(A) dc Current Source 直流电流源 noise current source 噪声电流源 current power spectral density in A^2/Hz 电流功率谱密度(A^2/Hz) frequency exponent 频率指数 frequency coefficient 频率系数 additive frequency term 加性频率项 Noise Current Source 噪声电流源 ideal amplifier 理想放大器 voltage gain 电压增益 reference impedance of input port 输入阻抗 reference impedance of output port 输出阻抗 noise figure 噪声系数 Amplifier 放大器 4x2 andor verilog device verilog 4x2 andor 设备 transfer function high scaling factor 传递函数高比例因子 output delay 输出延迟 s s 4x2 AndOr 4x2 AndOr 4x3 andor verilog device verilog 4x3 andor 设备 4x3 AndOr 4x3 AndOr 4x4 andor verilog device verilog 4x4 andor 设备 4x4 AndOr 4x4 AndOr attenuator 衰减器 power attenuation 功率衰减 reference impedance 参考阻抗 simulation temperature in degree Celsius 仿真温度(摄氏度) Attenuator 衰减器 bias t bias t for transient simulation: inductance in Henry 用于瞬态仿真：电感(H) for transient simulation: capacitance in Farad 用于瞬态仿真：电容(F) Bias T Bias T 4bit binary to Gray converter verilog device verilog 4位二进制码转格雷码转换器 设备 transfer function scaling factor 传递函数比例因子 4Bit Bin2Gray 4位Bin2Gray bipolar junction transistor 双极结型晶体管 npn transistor npn三极管 pnp transistor pnp三极管 polarity 极性 saturation current 饱和电流 forward emission coefficient 正向发射系数 reverse emission coefficient 反向发射系数 high current corner for forward beta 正向β高电流拐点 high current corner for reverse beta 反向β高电流拐点 forward early voltage 正向厄利电压 reverse early voltage 反向厄利电压 base-emitter leakage saturation current 基极-发射极泄漏饱和电流 base-emitter leakage emission coefficient 基极-发射极泄漏发射系数 base-collector leakage saturation current 基极-集电极漏电流饱和电流 base-collector leakage emission coefficient 基极-集电极泄漏发射系数 forward beta 正向β reverse beta 反向β minimum base resistance for high currents 大电流的最小基极电阻 current for base resistance midpoint 基极电阻中点的电流 collector ohmic resistance 集电极电阻 emitter ohmic resistance 发射极电阻 zero-bias base resistance (may be high-current dependent) 零偏置基极电阻(可能与大电流相关) base-emitter zero-bias depletion capacitance 基极-发射极零偏置耗尽电容 base-emitter junction built-in potential 基极-发射极结内置电位 base-emitter junction exponential factor 基极-发射极结指数因子 base-collector zero-bias depletion capacitance 基极集电极零偏置耗尽电容 base-collector junction built-in potential 基极-集电极结内置电位 base-collector junction exponential factor 基极-集电极结指数因子 fraction of Cjc that goes to internal base pin 进入内部基极引脚的Cjc分数 zero-bias collector-substrate capacitance 零偏置集电极-衬底电容 substrate junction built-in potential 衬底结内置电位 substrate junction exponential factor 衬底结指数因子 forward-bias depletion capacitance coefficient 正向偏置耗尽电容系数 ideal forward transit time 理想正向传输时间 coefficient of bias-dependence for Tf Tf的偏置依赖系数 voltage dependence of Tf on base-collector voltage Tf对基极-集电极电压的电压依赖性 high-current effect on Tf 大电流对晶体管Tf的影响 ideal reverse transit time 理想反向传输时间 flicker noise coefficient 闪烁噪声系数 flicker noise exponent 闪烁噪声指数 flicker noise frequency exponent 闪烁噪声频率指数 burst noise coefficient 突发噪声系数 burst noise exponent 突发噪声指数 burst noise corner frequency in Hertz 噪声转折频率(Hz) excess phase in degrees 相位位移(角度) temperature exponent for forward- and reverse beta 正向和反向β的温度指数 saturation current temperature exponent 饱和电流温度指数 energy bandgap in eV 能量带隙(eV) temperature at which parameters were extracted 提取参数的温度 default area for bipolar transistor 双极晶体管的默认区域 bipolar junction transistor with substrate 带衬底的双极结型晶体管 bond wire 键合线 length of the wire 线长 diameter of the wire 线直径 height above ground plane 离地平面高度 specific resistance of the metal 金属电阻率 relative permeability of the metal 金属相对磁导率 bond wire model 键合线模型 substrate 衬底 Bond Wire 键合线 simulation temperature 仿真温度 capacitor 电容 capacitance in Farad 电容(F) initial voltage for transient simulation 瞬态仿真的初始电压 schematic symbol 原理图符号 Capacitor 电容 current controlled current source 电流控制电流源 forward transfer factor 前向传递因子 delay time (Qucsator only) delay time 延迟 Current Controlled Current Source 电流控制电流源 current controlled voltage source 电流控制电压源 Current Controlled Voltage Source 电流控制电压源 circulator 环行器 reference impedance of port 1 端口1的参考阻抗 reference impedance of port 2 端口2的参考阻抗 reference impedance of port 3 端口3的参考阻抗 Circulator 环行器 coaxial transmission line 同轴传输线 relative permittivity of dielectric 电介质的相对介电常数 specific resistance of conductor 导体电阻率 relative permeability of conductor 导体相对磁导率 inner diameter of shield 屏蔽内径 diameter of inner conductor 内导体直径 mechanical length of the line 线的机械长度 loss tangent 损耗角正切值 Coaxial Line 同轴线 1bit comparator verilog device verilog 1位比较器 设备 1Bit Comparator 1位比较器 2bit comparator verilog device verilog 2位比较器 设备 2Bit Comparator 2位比较器 4bit comparator verilog device verilog 4位比较器 设备 4Bit Comparator 2位比较器 number of input ports 输入端口数 voltage of high level 高电平电压 Error 错误 Format Error: Wrong line start! 格式错误： 错误的行开始！ Format Error: Unknown component! %1 Do you want to load schematic anyway? Unknown components will be replaced by dummy subcircuit placeholders. 格式错误： 未知组件！ %1 您仍然要加载原理图吗？ 未知组件将被替换 通过虚拟子电路占位符。 Format Error: Wrong 'component' line format! 格式错误： 错误的'组件'行格式！ coplanar line 共面线 name of substrate definition 基板名称定义 width of the line 线宽 width of a gap 间隙宽度 length of the line 线长 material at the backside of the substrate 基板背面材料 use approximation instead of precise equation 使用近似值而不是精确方程 Coplanar Line 共面线 ideal coupler 理想耦合器 coupling factor 耦合系数 phase shift of coupling path in degree 耦合路径相移(角度) Coupler 耦合器 coplanar gap 共面间隙 width of gap between the two lines 两条线之间的间隙宽度 Coplanar Gap 共面间隙 coplanar open 共面开放 width of gap at end of line 线尾间隙宽度 Coplanar Open 共面开放 coplanar short 共面短 Coplanar Short 共面短 coplanar step 共面阶跃 width of line 1 线1的宽度 width of line 2 线2的宽度 distance between ground planes 接地平面之间的距离 Coplanar Step 共面阶跃 coupled transmission lines 耦合传输线 characteristic impedance of even mode 特性阻抗(偶模) characteristic impedance of odd mode 特性阻抗(奇模) electrical length of the line 电气长度 relative dielectric constant of even mode 相对介电常数(偶模) relative dielectric constant of odd mode 相对介电常数(奇模) attenuation factor per length of even mode 单位长度衰减系数(偶模) attenuation factor per length of odd mode 单位长度衰减系数(奇模) Coupled Transmission Line 耦合传输线 D flip flop with asynchronous reset 带异步复位的D触发器 D-FlipFlop D触发器 dc simulation 直流仿真 relative tolerance for convergence 收敛相对容差 absolute tolerance for currents 电流绝对容差 absolute tolerance for voltages 电压绝对容差 put operating points into dataset 将操作点放入数据集中 maximum number of iterations until error 错误前的最大迭代次数 save subcircuit nodes into dataset 将子电路节点保存到数据集中 preferred convergence algorithm 首选收敛算法 method for solving the circuit matrix 求解电路矩阵的方法 dc block 直流隔离 dc Block 直流隔离 dc feed 直流导通 dc Feed 直流导通 D flip flop with set and reset verilog device verilog 带置位和复位的D触发器 设备 cross coupled gate transfer function high scaling factor 交叉耦合栅极传递函数的高比例因子 cross coupled gate transfer function low scaling factor 交叉耦合栅极传递函数的低比例因子 cross coupled gate delay 交叉耦合栅极延迟 D-FlipFlop w/ SR 带置位和复位的D触发器 diac (bidirectional trigger diode) 双向触发二极管 (bidirectional) breakover voltage (双向)击穿电压 (bidirectional) breakover current (双向)击穿电流 parasitic capacitance 寄生电容 emission coefficient 发射系数 intrinsic junction resistance 固有结电阻 Diac 双向触发二极管 digital simulation 数字仿真 type of simulation 仿真类型 duration of TimeList simulation TimeList仿真的持续时间 netlist format 网表格式 digital source 数字源 number of the port 端口数 initial output value 初始输出值 list of times for changing output value 更改输出值的时间列表 diode 二极管 zero-bias junction capacitance 零偏置结电容 grading coefficient 分级系数 junction potential 结电位 linear capacitance 线性电容 recombination current parameter 复合电流参数 emission coefficient for Isr Isr发射系数 ohmic series resistance 串联电阻 transit time 传输时间 high-injection knee current (0=infinity) 高注入拐点电流(0=无穷大) reverse breakdown voltage 反向击穿电压 current at reverse breakdown voltage 反向击穿电压下的电流 Bv linear temperature coefficient Bv线性温度系数 Rs linear temperature coefficient Rs线性温度系数 Tt linear temperature coefficient Tt线性温度系数 Tt quadratic temperature coefficient Tt二次温度系数 M linear temperature coefficient M线性温度系数 M quadratic temperature coefficient M二次温度系数 default area for diode 二极管的默认面积 Diode 二极管 data voltage level shifter (digital to analogue) verilog device verilog 数据电压电平转换器(数模) 设备 voltage level 电平 time delay 延迟 D2A Level Shifter DA电平转换器 data voltage level shifter (analogue to digital) verilog device verilog 数据电压电平转换器(模数) 设备 V V A2D Level Shifter AD电平转换器 2to4 demultiplexer verilog device verilog 2to4解复用器 设备 2to4 Demux 2to4解复用器 3to8 demultiplexer verilog device verilog 3to8解复用器 设备 3to8 Demux 3to8解复用器 4to16 demultiplexer verilog device verilog 4to16解复用器 设备 4to16 Demux 4to16解复用器 externally controlled voltage source 外部控制电压源 voltage in Volts 电压(V) Externally Controlled Voltage Source 外部控制电压源 m m transconductance parameter 跨导参数 A/V**2 A/V**2 1/V 1/V HICUM Level 2 v2.22 verilog device HICUM Level 2 v2.22 verilog 设备 GICCR constant GICCR常数 A^2s A^2s Zero-bias hole charge 零偏置空穴电荷 Coul 库伦 High-current correction for 2D and 3D effects 2D和3D效应的大电流校正 Emitter minority charge weighting factor in HBTs HBTs中的发射极少数电荷加权因子 Collector minority charge weighting factor in HBTs HBT中的集电极少数电荷加权因子 B-E depletion charge weighting factor in HBTs HBTs中的B-E耗尽电荷加权因子 B-C depletion charge weighting factor in HBTs HBTs中的B-C耗尽电荷加权因子 Internal B-E saturation current 内部B-E饱和电流 Internal B-E current ideality factor 内部B-E电流理想因子 Internal B-E recombination saturation current 内部B-E复合饱和电流 Internal B-E recombination current ideality factor 内部B-E复合电流理想因子 Peripheral B-E saturation current 外设B-E饱和电流 Peripheral B-E current ideality factor 外设B-E电流理想因子 Peripheral B-E recombination saturation current 外周B-E复合饱和电流 Peripheral B-E recombination current ideality factor 外周B-E复合电流理想因子 Non-ideality factor for III-V HBTs III-V族HBTs的非理想因子 Base current recombination time constant at B-C barrier for high forward injection B-C势垒处的基极电流复合时间常数(用于高正向注入) Internal B-C saturation current 内部B-C饱和电流 Internal B-C current ideality factor 内部B-C电流理想因子 External B-C saturation current 外部B-C饱和电流 External B-C current ideality factor 外部B-C电流理想因子 B-E tunneling saturation current B-E隧道饱和电流 Exponent factor for tunneling current 隧穿电流的指数因子 Specifies the base node connection for the tunneling current 指定隧穿电流的基极节点连接 Avalanche current factor 雪崩电流系数 Exponent factor for avalanche current 雪崩电流的指数因子 Relative TC for FAVL FAVL的相对TC 1/K 1/K Relative TC for QAVL QAVL的相对TC Zero bias internal base resistance 零偏置内部基极电阻 External base series resistance 外部基极串联电阻 Factor for geometry dependence of emitter current crowding 发射极电流拥挤的几何依赖性系数 Correction factor for modulation by B-E and B-C space charge layer B-E和B-C空间电荷层调制的校正因子 Ratio of HF shunt to total internal capacitance (lateral NQS effect) 高频分流器与总内部电容之比(横向NQS效应) Ration of internal to total minority charge 内部电荷与总少数电荷的比值 Emitter series resistance 发射极串联电阻 External collector series resistance 外部集电极串联电阻 Substrate transistor transfer saturation current 衬底晶体管传输饱和电流 Forward ideality factor of substrate transfer current 衬底传输电流的正向理想因子 C-S diode saturation current C-S二极管饱和电流 Ideality factor of C-S diode current C-S二极管电流理想因子 Transit time for forward operation of substrate transistor 衬底晶体管正向操作的传输时间 Substrate series resistance 衬底串联电阻 Substrate shunt capacitance 衬底分流电容 Internal B-E zero-bias depletion capacitance 内部B-E零偏置耗尽电容 Internal B-E built-in potential 内部B-E内置电位 Internal B-E grading coefficient 内部B-E分级系数 Ratio of maximum to zero-bias value of internal B-E capacitance 内部B-E电容的最大偏置值与零偏置值之比 Peripheral B-E zero-bias depletion capacitance 外周B-E零偏置耗尽电容 Peripheral B-E built-in potential 外周B-E内置电位 Peripheral B-E grading coefficient 外周B-E分级系数 Ratio of maximum to zero-bias value of peripheral B-E capacitance 外周B-E电容的最大值与零偏置值之比 Internal B-C zero-bias depletion capacitance 内部B-C零偏置耗尽电容 Internal B-C built-in potential 内部B-C内置电位 Internal B-C grading coefficient 内部B-C分级系数 Internal B-C punch-through voltage 内部B-C穿通电压 External B-C zero-bias depletion capacitance 外部B-C零偏置耗尽电容 External B-C built-in potential 外部B-C内置电位 External B-C grading coefficient 外部B-C分级系数 External B-C punch-through voltage 外部B-C穿通电压 Partitioning factor of parasitic B-C cap 寄生B-C电容的分配因子 Partitioning factor of parasitic B-E cap 寄生B-E电容的分配因子 C-S zero-bias depletion capacitance C-S零偏置耗尽电容 C-S built-in potential C-S内置电位 C-S grading coefficient C-S分级系数 C-S punch-through voltage C-S穿通电压 Low current forward transit time at VBC=0V VBC=0V时的低电流正向传输时间 Time constant for base and B-C space charge layer width modulation 基极和B-C空间电荷层宽度调制的时间常数 Time constant for modelling carrier jam at low VCE 在低VCE下模拟载波干扰的时间常数 Neutral emitter storage time 中性发射极存储时间 Exponent factor for current dependence of neutral emitter storage time 中性发射极存储时间电流依赖性的指数因子 Saturation time constant at high current densities 高电流密度下的饱和时间常数 Smoothing factor for current dependence of base and collector transit time 基极和集电极传输时间的电流依赖性平滑因子 Partitioning factor for base and collector portion 基极和集电极部分的分配系数 Internal collector resistance at low electric field 低电场下的内部集电极电阻 Voltage separating ohmic and saturation velocity regime 电压分离欧姆和饱和速度状态 Internal C-E saturation voltage 内部C-E饱和电压 Collector punch-through voltage 集电极穿通电压 Storage time for inverse operation 反向操作的存储时间 Total parasitic B-E capacitance 总寄生B-E电容 Total parasitic B-C capacitance 总寄生B-C电容 Factor for additional delay time of minority charge 少数充电的额外延迟时间因子 Factor for additional delay time of transfer current 传输电流额外延迟时间的因子 Flag for turning on and off of vertical NQS effect 用于打开和关闭垂直NQS效应的标志 Flicker noise coefficient 闪烁噪声系数 Flicker noise exponent factor 闪烁噪声指数因子 Flag for determining where to tag the flicker noise source 用于确定标记闪烁噪声源的位置的标志 Scaling factor for collector minority charge in direction of emitter width 集电极少数电荷随发射极宽度方向的比例因子 Scaling factor for collector minority charge in direction of emitter length 集电极少数电荷随发射极长度方向的比例因子 Bandgap voltage extrapolated to 0 K 0K的带隙电压 First order relative TC of parameter T0 参数T0的一级分量的TC Second order relative TC of parameter T0 参数T0的二级分量的TC Temperature exponent for RCI0 RCI0的温度指数 Relative TC of saturation drift velocity 饱和漂移速度的相对TC Relative TC of VCES VCES的相对TC Temperature exponent of internal base resistance 内部基极电阻的温度指数 Temperature exponent of external base resistance 外部基极电阻的温度指数 Temperature exponent of external collector resistance 外部集电极电阻的温度指数 Temperature exponent of emitter resistance 发射极电阻的温度指数 Temperature exponent of mobility in substrate transistor transit time 基板晶体管传输时间中迁移率的温度指数 Effective emitter bandgap voltage 有效发射极带隙电压 Effective collector bandgap voltage 有效集电极带隙电压 Effective substrate bandgap voltage 有效衬底带隙电压 Coefficient K1 in T-dependent band-gap equation T相关带隙方程中的系数K1 Coefficient K2 in T-dependent band-gap equation T相关带隙方程中的系数K2 Exponent coefficient in transfer current temperature dependence 传输电流温度依赖性指数系数 Exponent coefficient in B-E junction current temperature dependence B-E结电流温度依赖性指数系数 Relative TC of forward current gain for V2.1 model V2.1型模型正向电流增益的相对TC Flag for turning on and off self-heating effect 用于打开和关闭自加热效果的标志 Thermal resistance 热电阻 K/W K/W Thermal capacitance 热电容 J/W J/W Flag for compatibility with v2.1 model (0=v2.1) 与V2.1模型兼容的标志(0=V2.1) Temperature at which parameters are specified 指定参数的温度 C C Temperature change w.r.t. chip temperature for particular transistor 特定晶体管的芯片温度随关系的温度变化 K K HICUM L2 v2.22 HICUM L2 v2.22 Ohm Ω F/m F/m A A F F diode relative area 二极管相对面积 parameter measurement temperature 参数测量温度 Celsius 摄氏度 equation defined device 方程定义设备 type of equations 方程类型 number of branches 分支数 current equation 电流方程 charge equation 电荷方程 Equation Defined Device 方程定义设备 equation 方程 Equation 方程 put result into dataset 将结果放入数据集 Qucsator equation Qucs legacy equation Qucslegacy方程 externally driven transient simulation 外部驱动的瞬态仿真 integration method 积分方法 order of integration method 积分方法顺序 initial step size in seconds 初始步长(秒) minimum step size in seconds 最小步长(秒) relative tolerance of local truncation error 局部截断误差的相对容差 absolute tolerance of local truncation error 局部截断误差的绝对容差 overestimation of local truncation error 局部截断误差的过估计值 relax time step raster 松弛时间步长网格 perform an initial DC analysis 执行初始直流分析 maximum step size in seconds 最大步长(秒) External transient simulation 外部瞬态仿真 1bit full adder verilog device verilog 1位全加器 设备 1Bit FullAdder 1位全加器 2bit full adder verilog device verilog 2位全加器 设备 2Bit FullAdder 2位全加器 gated D latch verilog device verilog门控D锁存器 Gated D-Latch 门控D锁存器 4bit Gray to binary converter verilog device verilog 4位格雷码转二进制码转换器 设备 4Bit Gray2Bin 4位Gray2Bin ground (reference potential) 地(参考电位) Ground 地 gyrator (impedance inverter) 阻抗转换器 gyrator ratio 阻抗比 Gyrator 阻抗转换器 1bit half adder verilog device verilog 1位半加器 设备 1Bit HalfAdder 1位半加器 Harmonic balance simulation 谐波平衡仿真 number of harmonics 谐波阶数 Harmonic balance 谐波平衡 4bit highest priority encoder (binary form) verilog device verilog 4位最高优先级编码器(二进制形式) 设备 4Bit HPRI-Bin 4位HPRI-Bin hybrid (unsymmetrical 3dB coupler) 混合(非对称 3dB 耦合器) phase shift in degree 相移(角度) Hybrid 混合 exponential current source 指数电流源 current before rising edge 上升沿前的电流 maximum current of the pulse 脉冲的最大电流 start time of the exponentially rising edge 指数上升沿的开始时间 start of exponential decay 指数下降沿的开始时间 time constant of the rising edge 上升沿的时间常数 time constant of the falling edge 下降沿的时间常数 Exponential Current Pulse 指数电流脉冲 file based current source 基于文件的电流源 name of the sample file 样本文件名 interpolation type 插值类型 repeat waveform 重复波形 current gain 电流增益 File Based Current Source 基于文件的电流源 inductor 电感 inductance in Henry 电感(H) initial current for transient simulation 瞬态仿真的初始电流 Inductor 电感 current probe 电流探针 Current Probe 电流探针 ideal current pulse source 理想脉冲电流源 current before and after the pulse 脉冲前后的电流 current of the pulse 脉冲的电流 start time of the pulse 脉冲的开始时间 ending time of the pulse 脉冲的结束时间 rise time of the leading edge 上升沿上升时间 fall time of the trailing edge 下降沿下降时间 Current Pulse 电流脉冲 ideal rectangle current source 理想矩形电流源 current at high pulse 高脉冲电流 duration of high pulses 高脉冲的持续时间 duration of low pulses 低脉冲的持续时间 initial delay time 初始延迟时间 Rectangle Current 矩形电流 isolator 绝缘体 Isolator 绝缘体 junction field-effect transistor 结型场效应晶体管 threshold voltage 阈值电压 channel-length modulation parameter 沟道长度调制参数 parasitic drain resistance 寄生漏极电阻 parasitic source resistance 寄生源极电阻 gate-junction saturation current 栅结饱和电流 gate-junction emission coefficient 栅结发射系数 gate-junction recombination current parameter 栅结复合电流参数 Isr emission coefficient Isr发射系数 zero-bias gate-source junction capacitance 零偏置栅极-源极结电容 zero-bias gate-drain junction capacitance 零偏置栅极-漏极结电容 gate-junction potential 栅极结电位 forward-bias junction capacitance coefficient 正向偏置结电容系数 gate P-N grading coefficient 栅极P-N分级系数 Vt0 temperature coefficient Vt0温度系数 Beta exponential temperature coefficient Beta指数温度系数 default area for JFET JFET的默认面积 n-JFET n-JFET p-JFET p-JFET JK flip flop with asynchronous set and reset 带异步置位和复位的JK触发器 JK-FlipFlop JK触发器 jk flip flop with set and reset verilog device verilog 带置位和复位的JK触发器 设备 JK-FlipFlop w/ SR 带SR端的JK触发器 Component taken from Qucs library 取自Qucs库的元件 name of qucs library file qucs库文件名 name of component in library 库中元件的名称 Logarithmic Amplifier verilog device verilog 对数放大器设备 scale factor 比例因子 scale factor error 比例因子误差 % % input I1 bias current 输入I1偏置电流 input reference bias current 输入基准偏置电流 number of decades 每十倍频程的数量 conformity error 匹配错误 output offset error 输出偏移误差 amplifier input resistance 放大器输入电阻 amplifier 3dB frequency 放大器3dB频率 Hz Hz amplifier output resistance 放大器输出电阻 conformity error temperature coefficient 匹配误差温度系数 %/Celsius %/摄氏度 offset temperature coefficient 温度偏移系数 V/Celsius V/摄氏度 scale factor error temperature coefficient 比例因子误差温度系数 input I1 bias current temperature coefficient 输入I1偏置电流温度系数 A/Celsius A/摄氏度 input reference bias current temperature coefficient 输入基准偏置电流温度系数 Logarithmic Amplifier 对数放大器 I I R R logic 0 verilog device verilog 逻辑0 设备 logic 0 voltage level 逻辑0 (低电平) Logic 0 逻辑0 logic 1 verilog device verilog 逻辑1 设备 logic 1 voltage level 逻辑1 (高电平) Logic 1 逻辑1 logical AND 逻辑 AND n-port AND n端口 AND logical buffer 逻辑传输门 Buffer 传输门 logical inverter 逻辑反相器 Inverter 反相器 logical NAND 逻辑 NAND n-port NAND n端口 NAND logical NOR 逻辑 NOR n-port NOR n端口 NOR logical OR 逻辑 OR n-port OR n端口 OR logical XNOR 逻辑 XNOR n-port XNOR n端口 XNOR logical XOR 逻辑 XOR n-port XOR n端口 XOR MESFET verilog device verilog MESFET 设备 model selector 模型选择 pinch-off voltage 夹断电压 A/(V*V) A/(V*V) saturation voltage parameter 饱和电压参数 channel length modulation parameter 沟道长度调制参数 doping profile parameter 掺杂曲线参数 power law exponent parameter 功率指数参数 power feedback parameter 功率反馈参数 1/W 1/W maximum junction voltage limit before capacitance limiting 电容限制前的最大结电压极限 capacitance saturation transition voltage 电容饱和转换电压 capacitance threshold transition voltage 电容阈值转换电压 dc drain pull coefficient 直流漏极牵引系数 subthreshold conductance parameter 亚阈值电导参数 diode saturation current 二极管饱和电流 diode emission coefficient 二极管发射系数 built-in gate potential 内置栅极电位 gate-drain junction reverse bias breakdown voltage 栅极-漏极结反向偏置击穿电压 diode saturation current temperature coefficient 二极管饱和电流温度系数 transit time under gate 栅极下传输时间 channel resistance 沟道电阻 area factor 面积系数 gate reverse breakdown current 栅极反向击穿电流 energy gap 能隙 eV eV zero bias gate-drain junction capacitance 零偏置栅极-漏极结电容 zero bias gate-source junction capacitance 零偏置栅极-源极结电容 zero bias drain-source junction capacitance Beta temperature coefficient Beta温度系数 Alpha temperature coefficient Alpha温度系数 Gamma temperature coefficient Gamma温度系数 Subthreshold slope gate parameter 亚阈值斜率栅极参数 subthreshold drain pull parameter 亚阈值漏极牵引参数 gate-source current equation selector 栅极-源极电流方程选择器 gate-drain current equation selector 栅极-漏极电流方程选择器 gate-source charge equation selector 栅极-源极电荷方程选择器 gate-drain charge equation selector 栅极-漏极电荷方程选择器 drain-source charge equation selector 漏极-源极电荷方程选择器 Vto temperature coefficient Vto温度系数 gate resistance 栅极电阻 Ohms Ω drain resistance 漏极电阻 source resistance 源极电阻 gate resistance temperature coefficient 栅极电阻温度系数 1/Celsius 1/摄氏度 drain resistance temperature coefficient 漏极电阻温度系数 source resistance temperature coefficient 源极电阻温度系数 forward bias slope resistance 正向偏置斜率电阻 breakdown slope resistance 击穿斜率电阻 shot noise coefficient 散粒噪声系数 MESFET MESFET Modular Operational Amplifier verilog device verilog 模块化运算放大器 设备 Gain bandwidth product (Hz) 增益带宽乘积(Hz) Open-loop differential gain at DC (dB) 直流时的开环差分增益(dB) Second pole frequency (Hz) 第二极点频率 Output resistance (Ohm) 输出电阻(Ω) Differential input capacitance (F) 差分输入电容(F) Differential input resistance (Ohm) 差分输入电阻(Ω) Input offset current (A) 输入偏移电流(A) Input bias current (A) 输入偏置电流(A) Input offset voltage (V) 输入偏移电压(V) Common-mode rejection ratio at DC (dB) 直流时的共模抑制比(dB) Common-mode zero corner frequency (Hz) 共模零点转折频率(Hz) Positive slew rate (V/s) 正压摆率(V/s) Negative slew rate (V/s) 负压摆率(V/s) Positive output voltage limit (V) 正输出电压极限(V) Negative output voltage limit (V) 负输出电压极限(V) Maximum DC output current (A) 最大直流输出电流(A) Current limit scale factor 电流限制比例系数 Modular OpAmp 模块化运算放大器 MOS field-effect transistor MOS场效应晶体管 n-MOSFET n-MOSFET p-MOSFET p-MOSFET depletion MOSFET 耗尽型MOSFET zero-bias threshold voltage 零偏置阈值电压 transconductance coefficient in A/V^2 跨导系数(A/V^2) bulk threshold in sqrt(V) 体阈值(sqrt(V)) surface potential 表面电位 channel-length modulation parameter in 1/V 沟道长度调制参数(1/V) drain ohmic resistance 漏极电阻 source ohmic resistance 源极电阻 gate ohmic resistance 栅极电阻 bulk junction saturation current 体结饱和电流 bulk junction emission coefficient 体结发射系数 channel width 沟道宽度 channel length 沟道长度 lateral diffusion length 横向扩散长度 oxide thickness 氧化物厚度 gate-source overlap capacitance per meter of channel width in F/m 每米长度沟道宽度的栅源重叠电容(F/m) gate-drain overlap capacitance per meter of channel width in F/m 每米沟道宽度的栅漏重叠电容(F/m) gate-bulk overlap capacitance per meter of channel length in F/m 每米沟道长度的栅极-体重叠电容(F/m) zero-bias bulk-drain junction capacitance 零偏置体-漏极结电容 zero-bias bulk-source junction capacitance 零偏置体-源极结电容 bulk junction potential 体结电位 bulk junction bottom grading coefficient 体结底级配系数 bulk junction forward-bias depletion capacitance coefficient 体结正向偏置耗尽电容系数 zero-bias bulk junction periphery capacitance per meter of junction perimeter in F/m 每米结周长的零偏置体结周外周电容(F/m) bulk junction periphery grading coefficient 体结周配系数 bulk transit time 体传递时间 substrate bulk doping density in 1/cm^3 衬底体掺杂密度(1/cm^3) surface state density in 1/cm^2 表面状态密度(1/cm^3) gate material type: 0 = alumina; -1 = same as bulk; 1 = opposite to bulk 栅极材料类型：0 = 氧化铝；-1 = 与体相同；1 = 与体相反 surface mobility in cm^2/Vs 表面迁移率(cm^2/Vs) drain and source diffusion sheet resistance in Ohms/square 漏极和源极扩散片电阻(Ω/square) number of equivalent drain squares 等效漏极方数 number of equivalent source squares 等效源极方数 zero-bias bulk junction bottom capacitance per square meter of junction area in F/m^2 每平方米结面积的零偏置体结底电容(F/m^2) bulk junction saturation current per square meter of junction area in A/m^2 每平方米结面积的体结饱和电流(A/m^2) drain diffusion area in m^2 漏极扩散面积(m^2) source diffusion area in m^2 源极扩散面积(m^2) drain junction perimeter 漏结周长 source junction perimeter 源结周长 Use global SPICE temperature MOS field-effect transistor with substrate 带衬底的MOS场效应晶体管 microstrip corner 微带角形 width of line 线宽 Microstrip Corner 微带角形 coupled microstrip line 耦合微带线 spacing between the lines 线之间的间距 microstrip model 微带模型 microstrip dispersion model 微带色散模型 Coupled Microstrip Line 耦合微带线 microstrip cross 微带四通 width of line 3 线3的宽度 width of line 4 线4的宽度 quasi-static microstrip model 准静态微带模型 show port numbers in symbol or not 是否以符号显示端口号 Microstrip Cross 微带四通 microstrip gap 微带间隙 width of the line 1 线1的宽度 width of the line 2 线2的宽度 spacing between the microstrip ends 微带两端之间的间距 Microstrip Gap 微带间隙 microstrip lange coupler Lange微带耦合器 Microstrip Lange Coupler Lange微带耦合器 microstrip line 微带线 Microstrip Line 微带线 microstrip mitered bend 微带弯曲 Microstrip Mitered Bend 微带弯曲 microstrip open 微带开放 microstrip open end model 微带开放模型 Microstrip Open 微带开放 microstrip radial stub 微带扇形 inner radius 内半径 outer radius 外半径 feeding line width stub angle 角度 Effective dimension Model degrees deg Microstrip Radial Stub 微带扇形 microstrip impedance step 微带阶跃阻抗 width 1 of the line 线1的宽度 width 2 of the line 线2的宽度 Microstrip Step 微带阶跃 microstrip tee 微带三通 temperature in degree Celsius 温度(摄氏度) Microstrip Tee 微带三通 microstrip via 微带过孔 diameter of round via conductor 圆形过孔导体直径 Microstrip Via 微带过孔 two mutual inductors 两个线圈的互感器 inductance of coil 1 线圈1的电感 inductance of coil 2 线圈2的电感 coupling factor between coil 1 and 2 线圈1和线圈2之间的耦合系数 Mutual Inductors 互感器 three mutual inductors 3线圈的互感器 inductance of coil 3 线圈3的电感 coupling factor between coil 1 and 3 线圈1和线圈3之间的耦合系数 coupling factor between coil 2 and 3 线圈2和线圈3之间的耦合系数 3 Mutual Inductors 3线圈互感器 several mutual inductors 多个线圈的互感器 number of mutual inductances 互感数 inductance of coil 线圈电感 coupling factor between coil %1 and coil %2 线圈%1和线圈%2之间的耦合系数 N Mutual Inductors N线圈互感器 2to1 multiplexer verilog device verilog 2to1多路复用器 设备 2to1 Mux 2to1多路复用器 4to1 multiplexer verilog device verilog 4to1多路复用器 设备 4to1 Mux 4to1多路复用器 8to1 multiplexer verilog device verilog 8to1多路复用器 设备 8to1 Mux 8to1多路复用器 NIGBT verilog device verilog NIGBT 设备 gate-drain overlap area 栅极-漏极重叠区域 m**2 m**2 area of the device 器件面积 MOS transconductance MOS跨导 ambipolar recombination lifetime 双极复合寿命 metallurgical base width 金属衬底宽度 avalanche uniformity factor 雪崩均匀系数 avalanche multiplication exponent 雪崩倍增率 gate-source capacitance per unit area 每单位面积栅源电容 F/cm**2 F/cm**2 gate-drain oxide capacitance per unit area 单位面积栅漏氧化物电容 emitter saturation current density 发射极饱和电流密度 A/cm**2 A/cm**2 triode region factor 三极管区系数 electron mobility 电子迁移率 cm**2/Vs cm**2/Vs hole mobility 空穴迁移率 base doping 基区掺杂 1/cm**3 1/cm**3 transverse field factor 横向场系数 gate-drain overlap depletion threshold 栅极-漏极重叠耗尽阈值 NIGBT NIGBT correlated current sources 相关电流源 current power spectral density of source 1 电流源1的功率谱密度 current power spectral density of source 2 电流源2的功率谱密度 normalized correlation coefficient 归一化相关系数 Correlated Noise Sources 相关噪声源 voltage power spectral density of source 2 电压源2的功率谱密度 voltage power spectral density of source 1 电压源1的功率谱密度 operational amplifier 运算放大器 absolute value of maximum and minimum output voltage 最大和最小输出电压的绝对值 OpAmp 运算放大器 Optimization 优化 optimization 优化 2bit pattern generator verilog device verilog 2位测试信号发生器 设备 pad output value 测试信号发生器的输出值 2Bit Pattern 2位测试信号发生器 3bit pattern generator verilog device verilog 3位测试信号发生器 设备 3Bit Pattern 3位测试信号发生器 4bit pattern generator verilog device verilog 4位测试信号发生器 设备 4Bit Pattern 4位测试信号发生器 Parameter sweep 参数扫描 simulation to perform parameter sweep on 仿真以执行参数扫描 parameter to sweep 要扫描的参数 start value for sweep 扫描的开始值 stop value for sweep 扫描的结束值 Simulation step phase shifter 移相器 Phase Shifter 移相器 Photodiode verilog device verilog 光电二极管 设备 photodiode emission coefficient 光电二极管发射系数 series lead resistance 串联引线电阻 diode dark current 二极管暗电流 responsivity 响应度 A/W A/W shunt resistance 分流电阻 quantum efficiency 量子效率 light wavelength 光波长 nm nm responsivity calculator selector 响应度计算选择器 Photodiode 光电二极管 Phototransistor verilog device verilog 光电二极管 设备 dark current 暗电流 collector series resistance 集电极串联电阻 emitter series resistance 发射极串联电阻 base series resistance 基极串联电阻 responsivity at relative selectivity=100% 相对选择性下的灵敏度=100% relative selectivity polynomial coefficient 相对选择性多项式系数 Phototransistor 光电晶体管 ac voltage source with phase modulator 带调相器的交流电压源 PM PM SPICE V(SFFM): SPICE V(SFFM)： offset volage 偏移电压 carrier amplitude 载波振幅 carrier signal frequency 载波频率 modulation index 调制指数 modulating signal frequency 调制信号频率 V(SFFM) V(SFFM) PM modulated Source PM调置源 Potentiometer verilog device verilog 电位器 设备 nominal device resistance 器件标称电阻 shaft/wiper arm rotation 旋钮/滑块旋转 resistive law taper coefficient 电阻律锥度系数 device type selector 设备类型选择器 maximum shaft/wiper rotation 旋钮/滑块的最大值 linearity error 线性误差 wiper arm contact resistance 滑块接触电阻 resistance temperature coefficient 电阻温度系数 PPM/Celsius PPM/摄氏度 Potentiometer 电位计 B B SPICE T: SPICE T： Characteristic impedance 特性阻抗 Transmission delay 传输延迟 Frequency 频率 Normalised length at given frequency 给定频率下的归一化长度 Initial voltage at end 1 末端1的初始电压 Initial current at end 1 末端1的初始电流 Initial voltage at end 2 末端2的初始电压 Initial current at end 2 末端2的初始电流 T T Rectangular Waveguide 矩形波导 widest side 最宽边 shortest side 最短边 material parameter for temperature model 温度模式的材料参数 relay 继电器 threshold voltage in Volts 阈值电压(V) hysteresis voltage in Volts 滞后电压(V) resistance of "on" state in Ohms 导通状态的电阻(Ω) resistance of "off" state in Ohms 关断状态的电阻(Ω) Relay 继电器 resistor 电阻 ohmic resistance in Ohms 电阻(Ω) first order temperature coefficient 第一温度系数 second order temperature coefficient 第二温度系数 temperature at which parameters were extracted (Qucsator only) Resistor 电阻 Resistor US 电阻(美标) equation defined RF device 方程定义的RF器件 type of parameters 参数类型 number of ports 端口数 representation during DC analysis 直流分析的图像 parameter equation 参数方程 Equation Defined RF Device 方程定义的RF器件 RF RF equation defined 2-port RF device 方程定义的2端RF器件 Equation Defined 2-port RF Device 方程定义的2端RF器件 RLCG transmission line RLCG传输线 RLCG RLCG resistive load 阻性负载 Ohm/m Ω/m inductive load 感性负载 H/m H/m capacitive load 容性负载 conductive load 导体负载 S/m S/m RLCG Transmission Line RLCG传输线 RS flip flop RS触发器 RS-FlipFlop RS触发器 ac power source 交流功率源 port impedance 端口阻抗 (available) ac power in dBm (available) ac power in Watts (可用)交流功率(W) enable transient model as sine source [true,false] Power Source 功率源 S parameter simulation S参数仿真 calculate noise parameters 计算噪声参数 input port for noise figure 噪声图表的输入端口 output port for noise figure 噪声图表的输出端口 put characteristic values into dataset 将特征值存入数据集中 save subcircuit characteristic values into dataset 将子电路特征值保存到数据集中 S-parameter simulation S参数仿真 S parameter file S参数文件 name of the s parameter file S参数文件名 data type 数据类型 n-port S parameter file n端口S参数文件 1-port S parameter file 1端口S参数文件 2-port S parameter file 2端口S参数文件 file 文件 SPICE netlist file SPICE网表文件 SPICE netlist SPICE网表 sim sim spice spice ERROR: No file name in SPICE component "%1". 错误：SPICE元件中没有文件名"%1" ERROR: Cannot open SPICE file "%1". 错误：无法打开SPICE文件"%1" ERROR: Cannot save converted SPICE file "%1". 错误：无法保存转换后的SPICE文件"%1" ERROR: Cannot open converted SPICE file "%1". 错误：无法转换SPICE文件"%1" Info 信息 Preprocessing SPICE file "%1". 正在预处理SPICE文件"%1" ERROR: Cannot save preprocessed SPICE file "%1". 错误：无法保存预处理过的SPICE文件"%1" ERROR: Cannot execute "%1". 错误：无法执行"%1" COMP ERROR: Cannot start QucsConv! COMP ERROR：无法启动QucsConv！ Converting SPICE file "%1". 转换SPICE文件"%1" subcircuit 子电路 name of qucs schematic file Qucs原理图文件名 Subcircuit 子电路 port of a subcircuit 子电路端口 number of the port within the subcircuit 子电路内的端口号 type of the port (for digital simulation only) 端口类型(仅用于数字模拟) Conjugated port for XSPICE differential ports XSPICE差分端口的关联端口 Subcircuit Port 子电路端口 substrate definition 基板定义 relative permittivity 相对介电常数 thickness in meters 厚度(m) thickness of metalization 金属层厚度 specific resistance of metal 金属电阻率 rms substrate roughness 基板粗糙度均方根值 Substrate 基板 switch (time controlled) 开关(时间控制) initial state 初始状态 time when state changes (semicolon separated list possible, even numbered lists are repeated) 状态更改的时间(可以使用分号分隔列表，偶数编号列表重复) resistance of "on" state in ohms "打开"状态的电阻(Ω) resistance of "off" state in ohms "关闭"状态的电阻(Ω) simulation temperature in degree Celsius (Qucsator only) Max possible switch transition time (transition time 1/100 smallest value in 'time', or this number) 最大可能的开关转换时间(转换时间是'time'中最小值的1/100，或此数字) Resistance transition shape (Qucsator only) Resistance transition shape 电阻过渡形状 Switch 开关 ideal symmetrical transformer 理想对称变压器 voltage transformation ratio of coil 1 线圈电压变比1 voltage transformation ratio of coil 2 线圈电压变比2 symmetric Transformer 对称变压器 T flip flop with set and reset verilog device verilog 带置位和复位的T触发器 设备 T-FlipFlop w/ SR 带SR端的T触发器 silicon controlled rectifier (SCR) 可控硅整流器(SCR) breakover voltage 击穿电压 gate trigger current 栅极触发电流 Thyristor 晶闸管 ideal transmission line 理想传输线 characteristic impedance 特性阻抗 attenuation factor per length in 1/m 单位长度衰减系数 (1/m) Transmission Line 传输线 ideal 4-terminal transmission line 理想4端子传输线 4-Terminal Transmission Line 4端子传输线 transient simulation 瞬态仿真 Transient .SENS analysis with Xyce 瞬态仿真(XYCE) Analysis mode 分析模式 start time in seconds 开始时间(秒) stop time in seconds 结束时间(秒) simulation time step 仿真时间步 Transient sensitivity analysis 瞬态灵敏度分析 number of simulation time steps 时间步个数 perform initial DC (set "no" to activate UIC) 执行初始DC(设置为"否"以激活UIC) Transient simulation 瞬态仿真 ideal transformer 变压器 voltage transformation ratio 变压比 Transformer 变压器 triac (bidirectional thyristor) 可控硅(双向晶闸管) (bidirectional) gate trigger current (双向)栅极触发电流 Triac 可控硅 resonance tunnel diode 谐振隧道二极管 peak current 峰值电流 valley current 谷值电流 valley voltage 谷值电压 resonance energy in Ws 谐振能量(Ws) Fermi energy in Ws 费米能量(Ws) resonance width in Ws 谐振宽度(Ws) maximum of transmission 最大传输量 fitting factor for electron density 电子密度的拟合系数 fitting factor for voltage drop 压降的拟合系数 fitting factor for diode current 电流拟合系数 zero-bias depletion capacitance 零偏置耗尽电容 life-time of electrons 电子的IFE时间 Tunnel Diode 隧道二极管 twisted pair transmission line 双绞线传输线 diameter of conductor 导体直径 diameter of wire (conductor and insulator) 导线(导体和绝缘体)直径 physical length of the line 导线的物理长度 twists per length in 1/m 单位长度的捻数(1/m) dielectric constant of insulator 绝缘体的介电常数 Twisted-Pair 双绞线 Symbol file not found: %1 找不到符号文件：%1 voltage controlled current source 电压控制电流源 forward transconductance 正向跨导 Voltage Controlled Current Source 电压控制电流源 voltage controlled voltage source 电压控制电压源 voltage controlled resistor 压控电阻 resistance gain 跨阻增益 Voltage Controlled Resistor 压控电阻 Voltage Controlled Voltage Source 电压控制电压源 Verilog file Verilog文件 Name of Verilog file Verilog文件名 verilog Verilog ERROR: No file name in %1 component "%2". 错误：%1元件中没有文件名"%2" ERROR: Cannot open %1 file "%2". 错误：无法打开%1文件"%2" exponential voltage source 指数电压源 voltage before rising edge 上升沿前的电压 maximum voltage of the pulse 脉冲的最大电压 rise time of the rising edge 上升沿的上升时间 fall time of the falling edge 下降沿的下降时间 Exponential Voltage Pulse 指数电压脉冲 file based voltage source 基于文件的电压源 File Based Voltage Source 基于文件的电压源 VHDL file VHDL文件 Name of VHDL file VHDL文件名 vhdl VHDL generic variable 通用变量 ideal ac voltage source 理想交流电压源 AC voltage source (SPICE) 交流电压源(SPICE) ac Voltage Source 交流电压源 ideal dc voltage source 理想直流电压源 dc Voltage Source 直流电压源 noise voltage source 噪声电压源 voltage power spectral density in V^2/Hz 电压功率谱密度(V^2/Hz) Noise Voltage Source 噪声电压源 voltage probe 电压探针 Voltage Probe 电压探针 ideal voltage pulse source 理想脉冲电压源 voltage before and after the pulse 脉冲前后的电压 voltage of the pulse 脉冲的电压 Voltage Pulse 电压脉冲 ideal rectangle voltage source 理想矩形电压源 voltage of high signal 高信号电压 voltage of low signal (SPICE only) 低信号电压(仅限SPICE) Rectangle Voltage 方波电压 Locus Curve 轨迹图 <invalid> <无效> invalid 无效 Polar 极坐标图 Polar-Smith Combi 极坐标-Smith混合图 Smith-Polar Combi Smith-极坐标混合图 3D-Cartesian 3D-笛卡尔坐标图 Cartesian 笛卡尔坐标图 Smith Chart Smith阻抗圆图 Admittance Smith Smith导纳圆图 no variables 无变量 wrong dependency 错误的依赖 no data 无数据 Tabular 数据表格 Timing Diagram 时序图 Truth Table 真值表 ERROR: Cannot open file "%1". 错误：无法打开文件"%1" ERROR: Cannot create user library subdirectory ! 错误：无法无法创建用户库子目录！ ERROR: Cannot create file "%1". 错误：无法创建文件"%1" Overwrite 覆盖 File "%1" already exists. Overwrite ? 文件"%1"已存在！ 要覆盖它吗？ Export to image 导出为图像 Inkscape start error! Inkscape启动错误！ Successfully exported Successfully exported Disk write error! 磁盘写入错误！ Unsupported format of graphics file. Use PNG, JPEG or SVG graphics! 不支持的图形文件格式。 使用PNG、JPEG或SVG格式！ Error: Wrong time format in "%1". Use positive number with units 错误："%1"中的时间格式错误。使用正数和单位 verilog-a user devices verilog-a用户元件 lumped components 集总参数元件 sources 源 probes 探针 RF components transmission lines 传输线 nonlinear components 非线性元件 microelectronics verilog-a devices verilog-a设备 digital components 数字元件 file components 外部文件元件 simulations 仿真 equations 求解 SPICE components SPICE元件 SPICE netlist sections SPICE specific sections SPICE特定部分 SPICE simulations SPICE仿真 XSPICE devices XSPICE设备 Qucs legacy devices Qucslegacy设备 diagrams 图表 paintings 绘图 external sim components 外部信号元件 Edit Properties 编辑属性 Export as image 导出为图像 power matching 功率匹配 noise matching 噪声匹配 2-port matching 2端口匹配 The ground potential cannot be labeled! 接地电位无法标记！ Arrow 箭头 Ellipse 椭圆 filled Ellipse 椭圆(实心) Edit Ellipse Properties 编辑椭圆属性 Elliptic Arc 椭圆弧 Edit Arc Properties 编辑椭圆弧属性 Line 线 Edit Line Properties 编辑线属性 Text 文本 Rectangle 矩形 filled Rectangle 矩形(实心) Edit Rectangle Properties 编辑矩形属性 Print Document 打印文档 Cannot create output file! 无法创建输出文件！ Format Error: 'Painting' field is not closed! 格式错误： '绘画'字段没有关闭！ Wrong document version: 错误的文档版本： Clipboard Format Error: Unknown field! 剪贴板格式错误： 未知的内容！ Cannot save C++ file "%1"! 无法保存C++文件"%1"！ Cannot open Verilog-A file "%1"! 无法打开Verilog-A文件"%1"！ Cannot save JSON props file "%1"! 无法保存JSON属性文件"%1"！ No valid osdi file. Re-compile verilog-a file first! Cannot save JSON symbol file "%1"! 无法保存JSON符号文件"%1"！ Cannot save document! 无法保存文档！ Format Error: Wrong property field limiter! 格式错误： 错误的属性字段限制！ Format Error: Unknown property: 格式错误： 未知的属性： Format Error: Number expected in property field! 格式错误： 预期数字类型 Format Error: 'Property' field is not closed! 格式错误： '属性'字段未闭合！ Format Error: 'Component' field is not closed! 格式错误： '元件'字段未闭合！ Format Error: Wrong 'wire' line format! 格式错误： 错误的'导线'行格式！ Format Error: 'Wire' field is not closed! 格式错误： '导线'字段未闭合！ Format Error: Unknown diagram! 格式错误： 未知的图表！ Format Error: Wrong 'diagram' line format! 格式错误： 错误的'图表'行格式！ Format Error: 'Diagram' field is not closed! 格式错误： '图表'字段未闭合！ Format Error: Wrong 'painting' line delimiter! 格式错误： 错误的'绘图' 行分隔符！ Format Error: Unknown painting! 格式错误： 未知的绘图！ Format Error: Wrong 'painting' line format! 格式错误： 错误的'绘图'行格式！ Cannot load document: 无法加载文档： Wrong document type: 错误的文档类型： Warning 警告 Wrong document version 错误的文档版本 Try to open it anyway? 尝试继续打开它吗？ File Format Error: Unknown field! 文件格式错误： 未知的字段！ ERROR: Component "%1" has no analog model. 错误：组件"%1"没有模拟模型 ERROR: Component "%1" has no digital model. 错误：组件"%1"没有数字模型 ERROR: Cannot load subcircuit "%1". 错误：无法加载子电路"%1" WARNING: Skipping library component "%1". 警告：跳过库元件"%1" ERROR: "%1": Cannot load library component "%2" from "%3" 错误："%1"：无法从"%3"中加载库元件"%2" WARNING: Ignore simulation component in subcircuit "%1". 警告：警告：忽略子电路中的仿真元件"%1" WARNING: Equations in "%1" are 'time' typed. 警告："%1"中的等式是'时间'类型的 ERROR: Only one digital simulation allowed. 错误：只允许进行一个数字仿真 ERROR: Analog and digital simulations cannot be mixed. 错误：模拟和数字仿真不能混合使用 ERROR: Digital simulation needs at least one digital source. 错误：数字仿真至少需要一个数字源 Part list 组件列表 Filter order = %1 滤波器顺序 = %1 Zeros list Pk=Re+j*Im 零点列表 Pk=Re+j*Im LPF prototype poles list Pk=Re+j*Im LPF原型极点列表 Pk=Re+j*Im Poles list Pk=Re+j*Im 极点列表 Pk=Re+j*Im High-impedance is %1 ohms, low-impedance is %2 ohms. To get acceptable results it is recommended to use a substrate with lower permittivity and larger height. 高阻抗为 %1 Ω，低阻抗为 %2 Ω。 为了获得可接受的结果，建议使用 介电常数较低且高度较大的衬底 Quarter wave filters do not allow low-pass nor high-pass masks 四分之一波滤波器不允许使用低通或高通掩模 Cannot save GUI settings in 无法保存GUI设置 XYCE script XYCE脚本 XSPICE generic device XSPICE通用设备 PortsList 端口列表 .MODEL definition reference .MODEL定义参考 XSPICE XSPICE XSPICE CodeModel: cfunc.mod and ifspec.ifs files pair XSPICE CodeModel XSPICE CodeModel XSPICE precompiled CodeModel library XSPICE预编译的CodeModel库 Precompiled CM-library 预编译的CM-库 XSPICE precompiled CM-library XSPICE预编译的CM-库 SPICE V(TRRANDOM): SPICE V(TRRANDOM)： Distribution selector (1 to 4) 分布选择(1至4) Duration of each random voltage value 每个随机电压值的持续时间 Time delay before random voltages output ( for time < Td Vout = 0 V) 随机电压输出前的时间延迟( for time < Td Vout = 0 V) Changes with different values of Type. 随Type值的不同而变化 Changes with different values of Type 随Type值的不同而变化 V(TRRANDOM) V(TRRANDOM) SPICE V(TRNOISE): SPICE V(TRNOISE)： Rms noise amplitude Gaussian) Rms 噪声幅度 Gaussian) Time step 时间步长 1/f exponent (0 < alpha < 2) 1/f指数(0 < alpha < 2) Amplitude (1/f) 振幅(1/f) Trap capture time 陷阱捕获时间 Trap emission time 陷阱发射时间 V(TRNOISE) V(TRNOISE) SPICE V(PWL): Multiple line ngspice or Xyce V specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. V(PWL) V(PWL) SPICE V(AM): ngspice only. SPICE V(AM)：仅ngspice可用 voltage amplitude 电压振幅 offset voltage 偏移电压 modulation frequency 调制频率 carrier frequency 载波频率 signal delay 信号延迟 V(AM) V(AM) SPICE B (V type): Multiple line ngspice or Xyce B specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. B source (V) B 源 (V) SPICE library device. You can attach symbol patterns to it. SPICE库设备。您可以将符号附加到它上面 SpiceLibrary file SpiceLibrary文件 Subcircuit entry (.SUBCKT) name 子电路入口 (.SUBCKT) 名称 Extra parameters list 额外参数列表 Pins assignment SPICE library device SpiceLibComp SpiceLibComp SPICE generic device SPICE通用设备 Number of pins 引脚数 SPICE device letter SPICE字母设备 .MODEL definition reference (optional) .MODEL 定义参考(可选) Parameter string (optional) 参数字符串(可选) SPICE SPICE .spiceinit file .spiceinit文件 .spiceinit .spiceinit .spiceinit contents .spiceinit内容 Spectrum analysis 频谱分析 DC .SENS simulation with Xyce 直流灵敏度仿真(XYCE) Output expressions 输出表达式 Reference parameter for .SENS analysis 灵敏度仿真分析的参考参数 Parameter for DC sweep 直流扫描参数 start value for DC sweep 直流扫描的开始值 stop value for DC sweep 直流扫描的结束值 Simulation step for DC sweep 直流扫描的仿真点数 DC sensitivity simulation 直流灵敏度仿真 Pole-Zero simulation 零极点仿真 Two input nodes list (space separated) 两个输入节点列表(空格分隔) Two output nodes list (space separated) 两个输出节点列表(空格分隔) Transfer function type (current/voltage) 传递函数类型(电流/电压) Analysis mode (Pole-Zero, Poles only, Zeros only) 分析模式(零极点、仅极点、仅零点) .PARAM section .PARAM部分 .PARAM .PARAM .PARAM Section .PARAM部分 .OPTIONS section .OPTIONS部分 .OPTIONS .OPTIONS Xyce option package name Xyce选项包名称 .OPTIONS Section .OPTIONS部分 Nutmeg equation Nutmeg方程 Nutmeg Nutmeg Nutmeg Equation Nutmeg方程 Noise simulation 噪声仿真 Node at which the total output is desired 需要总输出的节点 Independent source to which input noise is referred. 输入噪声所指向的独立源 .NODESET section .NODESET部分 .NODESET .NODESET .NODESET Section .NODESET部分 .MODEL section Multiple line ngspice or Xyce .MODEL allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. .MODEL .MODEL .MODEL Section .MODEL部分 .LIB directive .LIB指令 .LIB .LIB .Lib directive .LIB指令 .INCLUDE statement .INCLUDE部分 .INCLUDE .INCLUDE .INCLUDE statement .INCLUDE部分 .IC section .IC部分 .IC .IC .IC Section .IC部分 .GLOBAL_PARAM section .GLOBAL_PARAM部分 .GLOBAL_PARAM .GLOBAL_PARAM .GLOBAL PARAM .GLOBAL PARAM .GLOBAL_PARAM Section .GLOBAL_PARAM部分 .FUNC new function definition 新函数定义.FUNC .FUNC .FUNC .FUNC new function .FUNC新函数 Fourier simulation 傅里叶仿真 Distortion simulation 畸变模拟 Second frequency parameter 第二频率参数 Nutmeg script Nutmeg脚本 SPICE I(SFFM): SPICE I(SFFM)： offset current 偏移电流 carrier current amplitude 载波电流振幅 I(SFFM) I(SFFM) Include script before simulation 在仿真之前包含脚本 .INCLUDE SCRIPT .INCLUDE SCRIPT Include script 包含脚本 SPICE I(TRNOISE): SPICE I(TRNOISE)： I(TRNOISE) I(TRNOISE) SPICE I(PWL): Multiple line ngspice or Xyce I specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. I(PWL) I(PWL) SPICE I(AM): ngspice only. I(AM) I(AM) SPICE G (VOL, VALUE, TABLE, POLY): Multiple line ngspice non-linear G specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. G G SPICE E (CUR, VALUE, TABLE, POLY): Multiple line ngspice non-linear E specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. E E XSPICE core block: seven line XSPICE specification. core 核心 PWL controlled voltage source: Seven line XSPICE specification. XAPWL XAPWL SPICE U(URC): Multiple line ngspice or Xyce U specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. U(URC) U(URC) S domain transfer function block: Seven line XSPICE specification. SDTF SDTF SPICE W: Multiple line ngspice or Xyce W specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. W(CSW) W(CSW) SPICE V: Multiple line ngspice or Xyce V specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. V Source V 源 SPICE S: Multiple line ngspice or Xyce S specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. S(SW) S(SW) SPICE B (I type): Multiple line ngspice or Xyce B specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. B source (I) B 源 (I) SPICE I: Multiple line ngspice or Xyce I specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. I Source I 源 SPICE R: Multiple line ngspice or Xyce R specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. R Resistor R 电阻 R Resistor 3 pin Q(PNP) BJT: Multiple line ngspice or Xyce Q model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Q(PNP) BJT Q(PNP) BJT M(PMOS) MOS: Multiple line ngspice or Xyce M model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. M(PMOS) M(PMOS) Z(PMF) MESFET: Multiple line ngspice or Xyce Z model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Z(PMF) Z(PMF) J(PJF) JFET: Multiple line ngspice or Xyce J model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. J(PJF) JFET J(PJF) JFET Q(NPN) BJT: Multiple line ngspice or Xyce Q model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Q(NPN) BJT Q(NPN) BJT M(NMOS) MOS: Multiple line ngspice or Xyce M model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. M(NMOS) M(NMOS) J(NJF) JFET: Multiple line ngspice or Xyce J model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. J(NJF) JFET J(NJF) JFET Unified (M,X,3-,4-pin) MOS: Multiple line ngspice or Xyce M model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. unified MOSFET (3-4 pin) unified MOSFET (3-4 脚) M(NMOS 3 pin) M(NMOS 3 pin) M(PMOS 3 pin) M(PMOS 3 pin) X(NMOS 3 pin) X(NMOS 3 pin) X(PMOS 3 pin) X(PMOS 3 pin) X(NMOS 4 pin) X(NMOS 4 pin) X(PMOS 4 pin) X(PMOS 4 pin) Z(NMF) MESFET: Multiple line ngspice or Xyce Z model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. Z(NMF) Z(NMF) SPICE L: Multiple line ngspice or Xyce L specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. L Inductor L 电感 SPICE O(LTRA): SPICE O(LTRA)： O(LTRA) O(LTRA) SPICE K: Enter the names of the coupled inductances and their coupling factor. Coupling factor ( 0 < K <= 1) K coupling K 耦合 XSPICE coupled inductor block: two line XSPICE specification. Icouple SPICE D: Multiple line ngspice or Xyce D model specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. D Diode D 二极管 D Diode 3 pin SPICE C: Multiple line ngspice or Xyce C specifications allowed using "+" continuation lines. Leave continuation lines blank when NOT in use. C Capacitor C 电容 C Capacitor 3 pin Q(NPN) 4 pin Q(NPN) 4 pin Q(PNP) 4 pin Q(PNP) 4 pin Q(NPN) 5 pin Q(NPN) 5 pin Q(PNP) 5 pin Q(PNP) 5 pin The schematic name and dataset/display file name is not matching! This may happen if schematic was copied using the file manager instead of using File->SaveAs. Correct dataset and display names automatically? 原理图名称与数据集/显示器文件名不匹配！如果使用文件管理器而不是使用 文件->另存为 复制原理图，则可能会发生这种情况。自动更正数据集和显示名称吗？ Schematic file: 原理图文件： Dataset file: 数据集文件： Display file: 显示器文件： Open document 打开文档 Not Specified 未指定 Qucsator Qucsator Ngspice Ngspice SpiceOpus SpiceOpus Xyce Xyce Save netlist 保存网表 Lossy inductor 损耗电感 Inductance 电感 Quality factor 品质因数 Frequency at which Q is measured 测量的Q频率 Q frequency profile Inductor with Q 带Q的电感器 Lossy capacitor 损耗电容 Capacitance 电容 Capacitor with Q 带Q的电容器 The load has not resistive part. It cannot be matched using the quarter wavelength method Reactive loads cannot be matched. Only the real part will be matched Chebyshev weighting for N>7 is not available N>7的Chebyshev权重不可用 The load is reactive. It cannot be matched using the quarter wavelength method Exponential Tapered line 指数锥形线 Characteristic impedance at port 1 端口1处的特性阻抗 Characteristic impedance at port 2 端口2处的特性阻抗 Line length 线长 Taper weighting 锥度权重 Maximum ripple (Klopfenstein taper only) 最大纹波(仅限Klopfenstein锥度) Tapered line 锥形线 Circular Waveguide 圆形波导 Printed loop inductor Radius 半径 Circular loop Mechanical length of the line 线的机械长度 Relative permittivity of dielectric 电介质相对介电常数 Relative permeability of conductor 导体相对磁导率 Loss tangent 损耗角正切值 Specific resistance of conductor 导体电阻率 Simulation temperature in degree Celsius 模拟温度(摄氏度) Material parameter for temperature model 温度模型的材料参数 Port name Input port name: Planar spiral inductor Spiral type Width of line Inner diameter Spacing between turns Number of turns Spiral inductor .CSPARAM section .CSPARAM .CSPARAM Section QucsActiveFilter &File 文件 E&xit 退出 &View 视图 &Console 控制台 Enables/disables the filter calculation console 启用/停用滤波器计算控制台 Console Enables/disables the filter calculation console 控制台 启用/停用滤波器计算控制台 &Help 帮助 Help... 帮助... &About QucsActiveFilter... 关于QucsActiveFilter About Qt... 关于Qt Passband attenuation, Ap (dB) 通带衰减, Ap (dB) Stopband attenuation, As (dB) 阻带衰减, As (dB) Cutoff frequency, Fc (Hz) 截止频率, Fc (Hz) Stopband frequency, Fs (Hz) 阻带频率, Fs (Hz) Passband ripple Rp(dB) 通带纹波, Rp (dB) Passband gain, Kv (dB) 通带增益, Kv (dB) Filter order 滤波器顺序 Approximation type: 近似类型： Butterworth Butterworth Chebyshev Chebyshev Inverse Chebyshev Inverse Chebyshev Cauer (Elliptic) Cauer (Elliptic) Bessel Bessel Legendre Legendre User defined 用户定义 Manually define transfer function 手动定义传递函数 Calculate and copy to clipboard 计算并复制到剪切板 Low Pass 低通 General filter amplitude-frequency response 一般滤波器的幅频响应 Unable to implement filter with such parameters and topology Change parameters and/or topology and try again! 无法使用此类参数和拓扑实现滤波器 更改参数和/或拓扑，然后重试！ Filter calculation was successful 滤波器计算成功 Filter calculation terminated with error! 滤波器计算因错误而中止！ Filter calculation terminated with error 滤波器计算因错误而中止 Lower cutoff frequency, Fl (Hz) 低截止频率, Fl (Hz) Copyright (C) 2014, 2015 by Copyright (C) 2014, 2015 by Filter topology 滤波器拓扑 Filter type: 滤波器形式： High Pass 高通 Band Pass 带通 Band Stop 带阻 Multifeedback (MFB) 多重反馈 (MFB) Sallen-Key (S-K) Sallen-Key (S-K) Cauer section Cauer section Filter parameters 滤波器参数 Transfer function and Topology 传递函数和拓扑 Filter topology preview 滤波器拓扑预览 Filter calculation console 滤波器计算控制台 Ready. 准备 Upper cutoff frequency of band-pass/band-stop filter is less than lower. Unable to implement such filter. Change parameters and try again. 带通/带阻滤波器的截止频率上限小于下限。 无法实现此类过滤器。 更改参数，然后重试 Unable to use Cauer section for Chebyshev or Butterworth frequency response. Try to use another topology. 无法将Cauer section用于Chebyshev或Butterworth的 频率响应。尝试使用其他拓扑 Unable to use MFB filter for Cauer or Inverse Chebyshev frequency response. Try to use another topology. 无法将MFB滤波器用于Cauer或Inverse Chebyshev的 频率响应。尝试使用其他拓扑 Function will be implemented in future version 功能将在以后的版本中实现 Upper cutoff frequency, Fu (Hz) 截止频率上限，Fu (Hz) Transient bandwidth, TW (Hz) 瞬态带宽，TW (Hz) Error! 错误！ Active filter design 有源滤波器设计 About... 关于 Active Filter synthesis program 有源滤波器设计程序 About Qt 关于Qt QucsApp Schematic 原理图 Data Display 数据显示器 Qucs Documents Qucs文档 VHDL Sources VHDL源代码 Verilog Sources Verilog源代码 Verilog-A Sources Verilog-A源代码 Octave Scripts Octave脚本 Spice Files SPICE文件 Any File 任何文件 The schematic search path has been refreshed. 原理图搜索路径已刷新 Verilog Verilog VHDL VHDL Open file 打开文件 Document opened in read-only mode! Simulation will not work. Please copy the document to the directory where you have write permission! 文档以只读模式打开！仿真器将无法工作。请将文档复制到您有写入权限的目录！ Simulate schematic 仿真原理图 DC bias simulation mode is not supported for digital schematic! 数字原理图不支持直流偏置仿真模式！ Schematics 原理图 New 新建 Symbol only QucsatorRF found at: You can specify another location later using Simulation->Simulators Setings NOTE: Only QucsatorRF found. This simulator is not recommended for general purpose schematics. Please install Ngspice. Qucs Qucs No simulators found automatically. Please specify simulators in the next dialog window. Main Dock 主窗口 Open 打开 Delete 删除 Projects 项目 content of project directory 项目目录内容 Content 文档 content of current project 当前项目内容 Search Components 搜索元件 Clear 清除 Components 元件 components and diagrams 元件和图标 Libraries 库 system and user component libraries 系统和用户元件库 Octave Dock Octave窗口 Error 错误 Cannot open "%1". 无法打开"%1" Library is corrupt. 库已损坏 Info 信息 Default icon not found: %1.png 默认图标未找到： %1.png -port -端口 Copying Qucs document 复制Qucs文档 The document contains unsaved changes! 文档包含未保存的更改！ Do you want to save the changes before copying? 是否要在复制之前保存更改？ &Save 保存 Copy file 复制文件 Enter new name: 输入新名称： error 错误 Cannot rename an open file! 无法重命名文件一个打开的文件！ Rename file 重命名文件 Cannot delete an open file! 无法删除一个打开的文件！ Warning 警告 This will delete the file permanently! Continue ? 这将永久删除该文件！继续吗？ Yes 确定 unknown 未知 Verilog source Verilog源代码 Verilog-A source Verilog-A源代码 VHDL source VHDL源代码 data file 数据文件 data display 数据显示器 schematic 原理图 symbol 符号 VHDL configuration VHDL配置 configuration 配置 Cannot create work directory ! 无法创建工作目录！ Cannot create project directory ! 无法创建项目目录！ Choose Project Directory for Opening 选择要打开的项目的目录 No project is selected ! 未选择项目！ Cannot delete file: %1 无法删除文件：%1 Search results 搜索结果 Search Lib Components 搜索库元件 Set simulator 设置仿真器 Ngspice found at: 找到Ngspice位于： You can specify another location later using Simulation->Simulators Setings 您可以稍后使用 仿真->仿真器设置 指定另一个位置 Ngspice not found automatically. Please specify simulators in the next dialog window. 未找到Ngspice。请在指定仿真器的位置 Show model 显示模型 verilog-a user devices verilog-a用户设备 Cannot copy file to identical name: %1 无法将文件复制到相同的名称：%1 Cannot copy schematic: %1 无法复制原理图：%1 Enter new filename: 输入新的文件名： Cannot rename file: %1 无法重命名文件：%1 Cannot access project directory: %1 无法访问项目目录：%1 Project directory name does not end in '_prj'(%1) 项目目录名称不以'_prj'结尾(%1) Project: 项目： No project 无项目 Project directory name does not end in '_prj' (%1) 项目目录的名称不应以'_prj'结尾 (%1) Cannot delete an open project ! 无法删除一个打开的项目！ This will destroy all the project files permanently ! Continue ? 这将永久销毁所有项目文件！继续吗？ Cannot remove project directory! 无法移除项目目录！ Choose Project Directory for Deleting 选择要删除的项目的目录 No project is selected! 未选择项目 Creating new schematic... 创建新的原理图... Ready. 准备 Creating new text editor... 创建新的文本编辑器... Opening file... 打开文件... Enter a Schematic Name 输入原理图名称 Opening aborted 中止打开 Saving file... 保存文件... Saving aborted 中止保存 Qucs Netlist Qucs网表 SPICE Netlist Plain Text 纯文本 Subcircuit symbol Enter a Document Name 输入文件名 The file ' 文件 ' ' already exists! ' 文件已存在！ Saving will overwrite the old one! Continue? 保存将覆盖旧的文件！继续吗？ Cancel 取消 Cannot overwrite an open document 无法覆盖打开的文档 Saving file under new filename... 以新文件名保存文件... Saving all files... 保存所有文件... Closing file... 关闭文件... Closing Qucs document 关闭Qucs文档 Do you want to save the changes before closing? 是否要在关闭之前保存更改？ Open examples directory... 打开示例目录... untitled untitled Printing... 打印... Exiting application... 退出应用程序... No simulations found. Tuning not possible. Please add at least one simulation. 未找到仿真器。无法进行调整。请至少添加一个仿真器 Tuning not possible for digital simulation. Only analog simulation supported. 无法进行数字仿真调整。仅支持模拟仿真 Tuning has no effect without diagrams. Add at least one diagram on schematic. 在没有图表的情况下调整将没有效果。在原理图上添加至少一个图表 Symbol editing supported only for schematics and Verilog-A documents! Attaching symbols to Verilog-A sources is deprecated and not recommended for new designs. Use SPICE generic device instead. See the documentation for more details. Schematic not saved! Simulation of unsaved schematic not possible. Save schematic first! 原理图未保存！无法仿真未保存的原理图。请先保存原理图！ Simulation of text document is not possible! 无法仿真文本文档！ This action is supported only for SPICE simulators! 此操作仅支持SPICE仿真器！ Save CDL netlist failed! Save Verilog-A module 保存Verilog-A模块 Build Verilog-A module 构建Verilog-A模块 This schematic is not a subcircuit! Use subcircuit to crete Verilog-A module! 这个原理图不是子电路！ 使用子电路来构建Verilog-A模块！ The document was modified by another program ! 该文档被另一个程序修改了！ Open example… Select example schematic Open example canceled Do you want to reload or keep this version ? 重新加载还是保留此版本？ Cannot create 无法创建 No page set ! 没有页面设置！ Cannot start "%1"! 无法启动"%1"！ Could not load S[1,1]. 无法加载 S[1,1] Could not load S[1,2]. 无法加载 S[1,2] Could not load S[2,1]. 无法加载 S[2,1] Could not load S[2,2]. 无法加载 S[2,2] Wrong dependency! 错误的依赖！ Cutting selection... 切割选择... Copying selection to clipboard... 正在将所选内容复制到剪贴板... At least two elements must be selected ! 必须至少选择两个元素！ Opening aborted, file not found. 打开中止，找不到文件 Cannot start text editor! %1 无法启动文本编辑器！ %1 Show netlist 显示网表 Not a schematic tab! 不是原理图的选项卡！ Executable %1 not found! (%2) Cannot start %1 program! (%2) 无法启动程序 %1 ！ (%2) Layouting of display pages is not supported! Cannot write netlist! Digital schematic not supported! Layouting of text documents is not supported! Cannot start Qucs-RFLayout: %1 No project open! 未打开项目 Select files to copy 选择要复制的文件 No files copied. 未复制任何文件 Cannot open "%1" ! 无法打开"%1"！ Overwrite 覆盖 File "%1" already exists. Overwrite ? 文件"%1"已存在 要覆盖它吗？ Cannot create "%1" ! 无法创建"%1"！ Cannot read "%1" ! 无法读取"%1"！ Cannot write "%1" ! 无法写入"%1"！ Please open project with subcircuits! 请打开带有子电路的项目！ Please open project first! 请先打开项目！ Please select a diagram graph! 请选择一个图表！ Enter an Output File Name 输入输出文件的文件名 CSV file CSV文件 Output file already exists! 输出文件已存在！ Overwrite it? 要覆盖它吗？ Symbol files not found in: %1 Is the project open? Have you saved the Verilog-A symbols? 在以下位置找不到符号文件：%1 项目是否已经打开？ 您是否保存了Verilog-A符号？ admsXml admsXml Compiler Compiler admsXml Dock admsXml窗口 OpenVAF OpenVAF OpenVAF Dock OpenVAF窗口 &New 新建 Creates a new document 创建新的文档 New Creates a new schematic or data display document 新建 创建新的原理图或数据显示器文档 New &Text 新建文本文档 Ctrl+Shift+V Ctrl+Shift+V Creates a new text document 创建新的文本文档 New Text Creates a new text document 新建文本文档 创建新的文本文档 &Open... 打开... Opens an existing document 打开现有文档 Open File Opens an existing document 打开文件 打开现有文档 Saves the current document 保存当前文档 Save File Saves the current document 保存文件 保存当前文档 Save as... 另存为... Saves the current document under a new filename 将当前文档使用新文件名保存 Save As Saves the current document under a new filename 另存为 将当前文档使用新文件名保存 Save &All 保存全部 Ctrl+Shift+S Ctrl+Shift+S Saves all open documents 保存所有打开的文档 Save All Files Saves all open documents 保存所有文件 保存所有打开的文档 &Close 关闭 Closes the current document 关闭当前文档 Close File Closes the current document 关闭文件 关闭当前文档 Clear Recent 清除最近 &Examples 示例 Opens a file explorer with example documents 打开包含示例文档的文件资源管理器 Examples Opens a file explorer with example documents 示例 打开包含示例文档的文件资源管理器 &Edit Circuit Symbol 编辑电路符号 Edits the symbol for this schematic 编辑此原理图的符号 Edit Circuit Symbol Edits the symbol for this schematic 编辑电路符号 编辑此原理图的符号 &Document Settings... 文档设置... Ctrl+. Ctrl+. Document Settings 文档设置 Settings Sets properties of the file 设置 设置文件的属性 &Print... 打印... Prints the current document 打印当前文档 Print File Prints the current document 打印 打印当前文档 Print Fit to Page... 打印适合页面... Ctrl+Shift+P Ctrl+Shift+P Print Fit to Page 打印适合页面 Print Fit to Page Print and fit content to the page size 打印适合页面 打印内容并使其适合页面大小 E&xit 退出 Quits the application 退出应用程序 Exit Quits the application 退出 退出应用程序 Application Settings... 应用程序设置... Ctrl+, Ctrl+, Application Settings 应用程序设置 Qucs Settings Sets properties of the application Qucs设置 设置应用程序的属性 Refresh Search Path... 刷新搜索路径... Refresh Search Path 刷新搜索路径 Refresh Path Rechecks the list of paths for subcircuit files. 刷新搜索路径 重新检查子电路文件的路径列表 Align top 向上对齐 Ctrl+T Ctrl+T Align top selected elements 向上对齐所选元素 Align top Align selected elements to their upper edge 向上对齐 将所选元素与其上边缘对齐 Align bottom 向下对齐 Align bottom selected elements 向下对齐所选元素 Align bottom Align selected elements to their lower edge 向下对齐 将所选元素与其下边缘对齐 Align left 向左对齐 Align left selected elements 向左对齐选定元素 Align left Align selected elements to their left edge 向左对齐 将所选元素与其左边缘对齐 Align right 向右对齐 Align right selected elements 向右对齐选定元素 Align right Align selected elements to their right edge 向右对齐 将所选元素与其右边缘对齐 Distribute horizontally 横向等间距 Distribute equally horizontally 横向等间距 Distribute horizontally Distribute horizontally selected elements 横向等间距 横向等间距分布所选元素 Distribute vertically 纵向等间距 Distribute equally vertically 纵向等间距 Distribute vertically Distribute vertically selected elements 纵向等间距 纵向等间距分布所选元素 Center horizontally 垂直中心对齐 Center horizontally selected elements 垂直中心对齐所选元素 Center horizontally Center horizontally selected elements 垂直中心对齐 垂直中心对齐所选元素 Center vertically 水平中心对齐 Center vertically selected elements 水平中心对齐所选元素 Center vertically Center vertically selected elements 水平中心对齐 水平中心对齐所选元素 Set on Grid 设置在网格上 Ctrl+U Ctrl+U Sets selected elements on grid 设置所选元素在网格上 Set on Grid Sets selected elements on grid 设置在网格上 设置所选元素在网格上 Move Component Text 移动元件文本 Ctrl+K Ctrl+K Moves the property text of components 移动元件的属性文本 Move Component Text Moves the property text of components 移动元件文本 移动元件的属性文本 Replace... 替换... Replace component properties or VHDL code 替换元件属性或VHDL代码 Replace Change component properties or text in VHDL code 替换 替换元件属性 或 VHDL代码 Cu&t 剪切 Ctrl+X Ctrl+X Cuts out the selection and puts it into the clipboard 将所选内容剪切到剪贴板中 Cut Cuts out the selection and puts it into the clipboard 剪切 将所选内容剪切到剪贴板中 &Copy 复制 Copies the selection into the clipboard 将所选内容复制到剪贴板中 Copy Copies the selection into the clipboard 复制 将所选内容复制到剪贴板中 &Paste 粘贴 Pastes the clipboard contents to the cursor position 将剪贴板内容粘贴到光标位置 Paste Pastes the clipboard contents to the cursor position 粘贴 将剪贴板内容粘贴到光标位置 &Delete 删除 Deletes the selected components 删除所选元素 Delete Deletes the selected components 删除 删除所选元素 Find... 查找... Find a piece of text 查找一段文本 Find Searches for a piece of text 查找 查找一段文本 Export as image... 导出为图像... Exports the current document to an image file 将当前文档导出为图像文件 Export as image Exports the current document to an image file 导出为图像 将当前文档导出为图像文件 &Undo 撤消 Undoes the last command 撤消上一个命令 Undo Makes the last action undone 撤消 撤消上一个命令 &Redo 重做 Redoes the last command 重做上一个命令 Redo Repeats the last action once more 重做 重做上一个命令 &New Project... 新建项目... Ctrl+Shift+N Ctrl+Shift+N Creates a new project 创建新项目 New Project Creates a new project 新建项目 创建新项目 &Open Project... 打开项目... Ctrl+Shift+O Ctrl+Shift+O Opens an existing project 打开现有项目 Open Project Opens an existing project 打开项目 打开现有项目 &Delete Project... 删除项目... Ctrl+Shift+D Ctrl+Shift+D Deletes an existing project 删除现有项目 Delete Project Deletes an existing project 删除项目 删除现有项目 &Close Project 关闭项目 Ctrl+Shift+W Ctrl+Shift+W Closes the current project 关闭当前项目 Close Project Closes the current project 关闭项目 关闭当前项目 &Add Files to Project... 向项目添加文件... Ctrl+Shift+A Ctrl+Shift+A Copies files to project directory 复制文件到项目目录 Add Files to Project Copies files to project directory 向项目添加文件 复制文件到项目目录 Create &Library... 创建库... Ctrl+Shift+L Ctrl+Shift+L Create Library from Subcircuits 从子电路创建库 Create Library Create Library from Subcircuits 创建库 从子电路创建库 S-parameter Viewer Starts S-parameter viewer S-parameter Viewer Starts S-parameter viewer Tune Tuner Allows to live tune variables and show the result in the dataview Save CDL netlist Show Grid (current document) Alt+G Show or hide the grid for the current document. Show / Hide Grid Show or hide the grid for the current document. &About Qt Create &Package... 创建包... Ctrl+Shift+Y Ctrl+Shift+Y Create compressed Package from Projects 从项目创建压缩包 Create Package Create compressed Package from complete Projects 创建包 从项目创建压缩包 E&xtract Package... 提取包... Ctrl+Shift+X Ctrl+Shift+X Install Content of a Package 安装包的内容 Extract Package Install Content of a Package 提取包 安装包的内容 &Import/Export Data... 导入/导出数据... Ctrl+Shift+I Ctrl+Shift+I Convert data file 转换数据文件 Import/Export Data Convert data file to various file formats 导入/导出数据 将数据文件转换为各种文件格式 Export to &CSV... 导出为CSV... New symbol Creates a new symbol New Creates a new schematic symbol document Starts file chooser dialog to open one of example schematics Examples Start file chooser dialog and open one of example schematics Ctrl+Shift+C Ctrl+Shift+C Convert graph data to CSV file 转换图表数据为CSV文件 Export to CSV Convert graph data to CSV file 导出为CSV 转换图表数据为CSV文件 Build Verilog-A module... 构建Verilog-A模块... Run admsXml and C++ compiler 运行admsXml和C++编译器 Build Verilog-A module Runs amdsXml and C++ compiler 构建Verilog-A模块 >运行admsXml和C++编译器 Load Verilog-A module... 加载Verilog-A模块 Select Verilog-A symbols to be loaded 选择要加载的Verilog-A符号 Load Verilog-A module Let the user select and load symbols 加载 Verilog-A 模块 允许用户选择和加载符号 View All 查看全部 Show the whole page 显示整个页面 View All Shows the whole page content 查看全部 显示整个页面 Zoom to selection Z Zoom to selected components Zoom to selection Zoom to selected components View 1:1 1:1视图 Views without magnification 没有缩放的视图 View 1:1 Shows the page content without magnification 1:1视图 没有缩放的视图 Zoom in 放大 Zooms into the current view 放大当前视图 Zoom in Zooms the current view 放大 放大当前视图 Zoom out 缩小 Zooms out the current view 缩小 Zoom out Zooms out the current view 缩小 缩小当前视图 Select 选择 Activate select mode 激活选择模式 Select Activates select mode 选择 激活选择模式 Select All 全选 Ctrl+A Ctrl+A Selects all elements 选择全部元素 Select All Selects all elements of the document 全选 选择文档中的全部元素 Select Markers 选择标记 Ctrl+Shift+M Ctrl+Shift+M Selects all markers 选择全部标记 Select Markers Selects all diagram markers of the document 选择标记 选择文档中的所有图表标记 Rotate 旋转 Ctrl+R Ctrl+R Rotates the selected component by 90� 将所选元件旋转90度 Rotate Rotates the selected component by 90� counter-clockwise 旋转 将所选元件旋转90度 Ctrl+W Power combining 功率合成器 Ctrl+7 Ctrl+7 Starts QucsPowerCombining 打开Qucs功率合成器 Power combining Starts power combining calculation program 功率合成器 打开功率合成器计算程序 Data files converter Ctrl+8 RF Layout Ctrl+9 Starts Qucs-RFLayout View Data Display/Schematic Changes to data display or schematic page 数据显示器视图/原理图 切换数据显示器视图或原理图页面 Set Diagram Limits Pick the diagram limits using the mouse. Right click for default. Set Diagram Limits Pick the diagram limits using the mouse. Right click for default. Reset Diagram Limits Ctrl+Shift+E Resets the limits for all axis to auto. Reset Diagram Limits Resets the limits for all axis to auto. Simulators Settings... 仿真器设置... &About Qucs-S... 关于Qucs-S... Mirror about X Axis 垂直翻转 Ctrl+J Ctrl+J Mirrors the selected item about X Axis 将所选元素关于X轴镜像 Mirror about X Axis Mirrors the selected item about X Axis 垂直翻转 将所选元素关于X轴镜像 Mirror about Y Axis 水平翻转 Ctrl+M Ctrl+M Mirrors the selected item about Y Axis 将所选元素关于Y轴镜像 Mirror about Y Axis Mirrors the selected item about Y Axis 水平翻转 将所选元素关于Y轴镜像 Go into Subcircuit 进入子电路 Ctrl+I Ctrl+I Goes inside the selected subcircuit 进入选择的子电路 Go into Subcircuit Goes inside the selected subcircuit 进入子电路 进入选择的子电路 Pop out 退出子电路 Ctrl+H Ctrl+H Pop outside subcircuit 退出子电路 Pop out Goes up one hierarchy level, i.e. leaves subcircuit 退出子电路 返回上一级电路，即离开子电路 Deactivate/Activate 停用/激活 Ctrl+D Ctrl+D Deactivate/Activate selected components 停用/激活所选的元素 Deactivate/Activate Deactivate/Activate the selected components 停用/激活 停用/激活所选的元素 Insert Equation 插入方程 Ctrl+< Ctrl+< Inserts an equation 插入方程 Insert Equation Inserts a user defined equation 插入方程 插入用户定义的方程 Insert Ground 插入地 Ctrl+G Ctrl+G Inserts a ground symbol 插入地符号 Insert Ground Inserts a ground symbol 插入地 插入地符号 Insert Port 插入端口 Inserts a port symbol 插入端口符号 Insert Port Inserts a port symbol 插入端口 插入端口 Wire 导线 Ctrl+E Ctrl+E Inserts a wire 绘制导线 Wire Inserts a wire 导线 绘制导线 Wire Label 导线标签 Ctrl+L Ctrl+L Inserts a wire or pin label 插入导线标签或引脚标签 Wire Label Inserts a wire or pin label 导线标签 插入导线标签或引脚标签 VHDL entity VHDL实体 Ctrl+Space Ctrl+Space Inserts skeleton of VHDL entity 插入VHDL实体的框架 VHDL entity Inserts the skeleton of a VHDL entity VHDL实体 插入VHDL实体的框架 Text Editor 文本编辑器 Ctrl+1 Ctrl+1 Starts the Qucs text editor 启动Qucs文本编辑器 Text editor Starts the Qucs text editor 文本编辑器 启动Qucs文本编辑器 Filter synthesis 滤波器设计 Ctrl+2 Ctrl+2 Starts QucsFilter 启动QucsFilter Filter synthesis Starts QucsFilter 滤波器设计 启动QucsFilter Active filter synthesis 有源滤波器设计 Ctrl+3 Ctrl+3 Starts QucsActiveFilter 启动QucsActiveFilter Active filter synthesis Starts QucsActiveFilter 有源滤波器设计 启动QucsActiveFilter Line calculation 传输线计算器 Ctrl+4 Ctrl+4 Starts QucsTrans 启动QucsTrans Line calculation Starts transmission line calculator 传输线计算器 启动传输线计算器 Matching Circuit 匹配网络 Ctrl+5 Ctrl+5 Creates Matching Circuit 创建匹配网络 Matching Circuit Dialog for Creating Matching Circuit 匹配网络 创建匹配网络 Attenuator synthesis 衰减器设计 Ctrl+6 Ctrl+6 Starts QucsAttenuator 启动QucsAttenuator衰减器设计程序 Attenuator synthesis Starts attenuator calculation program 衰减器设计 启动QucsAttenuator衰减器设计程序 Simulate 仿真 Simulates the current schematic 仿真当前原理图 Simulate Simulates the current schematic 仿真 仿真当前原理图 View Data Display/Schematic 数据显示器视图/原理图 Changes to data display or schematic page 切换数据显示器视图或原理图页面 Calculate DC bias 计算直流偏置 Calculates DC bias and shows it 计算直流偏置并显示 Calculate DC bias Calculates DC bias and shows it 计算直流偏置 计算直流偏置并显示 Save netlist 保存网表 Save netlist to file 保存网表到文件 Set Marker on Graph 在图表上设置标记 Sets a marker on a diagram's graph 在图表上设置标记 Set Marker Sets a marker on a diagram's graph 设置标记 在图表上设置标记 Show Last Messages 显示最后一次信息 Shows last simulation messages 显示最后一次仿真信息 Show Last Messages Shows the messages of the last simulation 显示最后一次信息 显示最后一次仿真信息 Show Last Netlist 显示最后一次网表 Shows last simulation netlist 显示最后一仿真次网表 Show Last Netlist Shows the netlist of the last simulation 显示最后一次网表 显示最后一仿真次网表 Build Verilog-A module from subcircuit 从子电路构建Verilog-A模块 Tool&bar 工具栏 Enables/disables the toolbar 启用/停用工具栏 Toolbar Enables/disables the toolbar 工具栏 启用/禁用工具栏 &Statusbar 状态栏 Enables/disables the statusbar 启用/停用状态栏 Statusbar Enables/disables the statusbar 状态栏 启用/禁用状态栏 &Dock Window 停靠窗口 Enables/disables the browse dock window 启用/停用停靠窗口 Browse Window Enables/disables the browse dock window 浏览窗口 启用/停用浏览窗口 &Octave Window Octave窗口 Shows/hides the Octave dock window 显示/隐藏Octave窗口 Octave Window Shows/hides the Octave dock window Octave窗口 显示/隐藏Octave窗口 Help Index... 帮助索引.. Index of Qucs Help Qucs的帮助索引 Help Index Index of intern Qucs help 帮助索引 Qucs的帮助索引 Getting Started... 开始使用... Getting Started with Qucs 学习并开始使用Qucs Getting Started Short introduction into Qucs 开始使用 学习并开始使用Qucs &About Qucs-S About the application 关于应用程序 About About the application 关于 关于应用程序 About Qt... 关于Qt About Qt 关于Qt About Qt About Qt by Trolltech 关于Qt About Qt by Trolltech &File 文件 Open Recent 最近打开 &Edit 编辑 P&ositioning 对齐 &Insert 插入 &Project 项目 &Tools 工具 Compact modelling 紧凑型模型 &Simulation 仿真 &View 视图 &Help 帮助 &Technical Papers 技术论文 Open 打开 Open 打开 Technical &Reports 技术报告 T&utorials 教程 File 文件 Edit 编辑 View 视图 Work 工作 no warnings 无警告 Warnings in last simulation! Press F5 上次模拟中的警告！按F5 QucsAttenuator &File 文件 &Quit 退出 &Help 帮助 &About 关于 About Qt... 关于Qt Topology 拓扑 Input 输入 Attenuation: 衰减： Pin: Freq: Put into Clipboard R4: Copyright (C) 2024 by 1 1 dB dB Zin: Zin： 50 50 Ohm Ω Zout: Zout： Calculate and put into Clipboard 计算并复制到剪切板 Output 输出 R1: R1： -- -- R2: R2： R3: R3： Result: 结果: Qucs Attenuator Help Qucs Attenuator帮助 QucsAttenuator is an attenuator synthesis program. To create a attenuator, simply enter all the input parameters and press the calculation button. Immediately, the schematic of the attenuator is calculated and put into the clipboard. Now go to Qucs, open an schematic and press CTRL-V (paste from clipboard). The attenuator schematic can now be inserted. Have lots of fun! About Qt 关于Qt About... 关于 Attenuator synthesis program 衰减器设计程序 Copyright (C) 2006 by Copyright (C) 2006 by Success! 成功！ Error: Set Attenuation less than %1 dB 错误：设置衰减小于 %1 dB QucsEdit About... 关于 Error 错误 QucsFilter &File 文件 E&xit 退出 &Help 帮助 Help... 帮助... &About QucsFilter... 关于QucsFilter... About Qt... 关于Qt Filter 滤波器 Realization: 实现方式 Filter type: 滤波器形式： Filter class: 滤波器类型： Low pass 低通 High pass 高通 Band pass 带通 Band stop 带阻 Order: 阶数 Corner frequency: 拐点频率 Stop frequency: 截止频率 Stop band frequency: 阻带频率 Pass band ripple: 带内纹波 Stop band attenuation: 带外衰减 Impedance: 阻抗 Microstrip Substrate 微带线基底 Relative permittivity: 相对介电常数 Substrate height: 基底厚度 metal thickness: 金属厚度 minimum width: 最小线宽 maximum width: 最大线宽 Calculate and put into Clipboard 计算并复制到剪切板 About... 关于 Filter synthesis program 滤波器综合程序 Copyright (C) 2005, 2006 by Copyright (C) 2005, 2006 by About Qt 关于Qt Result: 结果: Error 错误 Stop frequency must be greater than start frequency. 截止频率必须高于起始频率 Filter order must not be less than two. 滤波器阶数必须大于等于2 Bessel filter order must not be greater than 19. 贝塞尔滤波器阶数不能大于19 Successful 成功 Result: -- 结果: -- Start frequency: 起始频率 Pass band frequency: 通带频率 Pass band attenuation: 阻带衰减 QucsHelp Qucs Help System Qucs帮助文档系统 QucsLib About... 关于 Error 错误 QucsPowerCombiningTool Ready! Use CTRL+V to paste the schematic 使用CTRL+V粘贴原理图 Error! The network could not be generated 错误！无法生成网络 Bagley Tree combiner QucsSettingsDialog Edit Qucs Properties 编辑Qucs属性 Large font size: 大字体字号： Document Background Color: 文档背景颜色： Language (set after reload): 语言(重启后生效)： system language 系统语言 English German French Spanish Italian Polish Romanian Japanese Swedish Hungarian Hebrew Portuguese-BR Portuguese-PT Turkish Ukrainian Russian Czech Catalan Arabic Chinese Schematic font (set after reload): 原理图字体(重启后生效)： Application font (set after reload): 应用程序字体(重启后生效)： Kazakh Maximum undo operations: 最大撤消操作次数： Text editor: 文本编辑器： Set to qucs, qucsedit or the path to your favorite text editor. 设置为qucs、qucsedit或您喜欢的文本编辑器的路径 Start wiring when clicking open node: 单击打开节点时开始接线： Load documents from future versions: 从未来版本加载文档： Try to load also documents created with newer versions of Qucs. 尝试加载使用较新版本的Qucs创建的文档 Draw diagrams with anti-aliasing feature: 绘制具有抗锯齿功能的图表： Draw text with anti-aliasing feature: 使用抗锯齿功能绘制文本： Use anti-aliasing for graphs for a smoother appearance. 对图形使用抗锯齿以获得更平滑的外观。 Text document font (set after reload): Use anti-aliasing for text for a smoother appearance. 对文本使用抗锯齿以获得更平滑的外观。 Show trace name prefix on diagrams: 在图表上显示跟踪名称前缀： Show prefixes for trace names on diagrams like "ngspice/" 在图表上显示跟踪名称的前缀，例如 "ngspice/" Panel icons theme (set after reload): 面板图标主题(重启后生效)： Components icons theme (set after reload): 元件图标主题(重启后设置)： Settings 设置 Grid Color (set after reload): Default graph line thickness: App Style: Appearance Colors for Syntax Highlighting: 语法突出显示的颜色： Comment 评论 String 文本 Integer Number 整数 Real Number 实数 Character 字符 Data Type 数据类型 Attribute 属性 Directive 方向 Task 任务 Source Code Editor 源代码编辑器 Register filename extensions here in order to open files with an appropriate program. 在此处注册文件扩展名，以便 使用适当的程序打开文件 Suffix 后缀 Program 程序 Suffix: 后缀： Program: 程序： Set 设置 Remove 删除 File Types 文件类型 Edit the standard paths and external applications 编辑标准路径和外部应用程序 Qucs Home: Qucs Home： Browse 浏览 AdmsXml Path: AdmsXml路径： ASCO Path: ASCO路径： Octave Path: Octave路径： OpenVAF Path: OpenVAF路径： RF Layout Path: Subcircuit Search Path List 子电路搜索路径列表 Add Path Add Path With SubFolders Remove Path Locations 位置 OK 确定 Apply 应用 Cancel 取消 Default Values 默认值 Error 错误 This suffix is already registered! 此后缀已经被注册！ Select the home directory 选择主目录 Select the admsXml bin directory 选择admsXml的bin目录 Select the ASCO bin directory 选择ASCO的bin目录 Select the octave executable 选择octave可执行文件 Select the OpenVAF executable 选择OpenVAF可执行文件 Select the Qucs-RFLayout executable Select a directory 选择一个目录 QucsTranscalc &File 文件 &Load 加载 Ctrl+L Ctrl+L &Save 保存 Ctrl+S Ctrl+S &Options 选项 Ctrl+O Ctrl+O &Quit 退出 &Execute 执行 &Copy to Clipboard 复制到剪切板 &Analyze 分析 &Synthesize 设计 &Help 帮助 About 关于 Transmission Line Type 传输线类型 Microstrip Line 微带线 Coplanar Waveguide 共面波导 Grounded Coplanar 共面波导与接地层 Rectangular Waveguide 矩形波导 Coaxial Line 同轴线 Coupled Microstrip 耦合微带线 Stripline 带状线 Substrate Parameters 基板参数 Component Parameters 元件参数 Physical Parameters 物理参数 Analyze 分析 Derive Electrical Parameters 推导电气参数 Synthesize 实现 Compute Physical Parameters 计算物理参数 Electrical Parameters 电气参数 Calculated Results 计算结果 Ready. 准备 ErEff ErEff Conductor Losses 导体损耗 Dielectric Losses 介电损耗 Skin Depth 趋肤深度 TE-Modes TE-模式 TM-Modes TM-模式 ErEff Even ErEff(偶模) ErEff Odd ErEff(奇模) Conductor Losses Even 导体损耗(偶模) Conductor Losses Odd 导体损耗(奇模) Dielectric Losses Even 介电损耗(偶模) Dielectric Losses Odd 介电损耗(奇模) Relative Permittivity 相对介电常数 Relative Permeability 相对渗透率 Height of Substrate 基板高度 Height of Box Top 箱顶高度 Strip Thickness 微带厚度 Strip Conductivity 微带材料电导率 Dielectric Loss Tangent 介电损耗角正切值 Conductor Roughness 导体粗糙度 Frequency 频率 Line Width 线宽 Line Length 线长 Characteristic Impedance 特性阻抗 Electrical Length 电气长度 Gap Width 间隙宽度 Conductivity of Metal 金属电导率 Magnetic Loss Tangent 磁损耗角正切值 Width of Waveguide 波导宽度 Height of Waveguide 波导高度 Waveguide Length 波导长度 Inner Diameter 内径 Outer Diameter 外径 Length 长度 Even-Mode Impedance 偶模阻抗 Odd-Mode Impedance 奇模阻抗 Conductor thickness 导体厚度 Substrate height 基板高度 Width 宽度 Selected for Calculation 选择进行计算 Check item for Calculation 检查需要计算的项目 About... 关于 Transmission Line Calculator for Qucs Qucs传输线计算器 Copyright (C) 2001 by Gopal Narayanan Copyright (C) 2001 by Gopal Narayanan Copyright (C) 2002 by Claudio Girardi Copyright (C) 2002 by Claudio Girardi Copyright (C) 2005 by Stefan Jahn Copyright (C) 2005 by Stefan Jahn Copyright (C) 2008 by Michael Margraf Copyright (C) 2008 by Michael Margraf Values are consistent. 这些值是一致的 Failed to converge! 转换失败 Values are inconsistent. 这些值是不一致的 Loading file... 加载文件 Enter a Filename 输入文件名 Transcalc File Transcalc文件 Error 错误 Cannot load file: 无法加载文件： Loading aborted. 加载中止 Saving file... 保存文件... Cannot save file: 无法保存文件： Saving aborted. 保存中止 Schematic copied into clipboard. 原理图已复制到剪切板 Transmission line type not available. 传输线类型不可用 Qucs_S_SPAR_Viewer &File 文件 &Quit 退出 &Open session file &Save session as ... &Save session &Help 帮助 &About 关于 About Qt... 关于Qt Qucs-S S-parameter Help This is a simple viewer for S-parameter data. It can show several .snp files at a time in the same diagram. Trace markers can also be added so that the user can read the trace value at at an specific frequency. About Qt 关于Qt About... 关于 Copyright (C) 2024 by S-Parameter Files (*.s1p *.s2p *.s3p *.s4p);;All Files (*.*) Warning 警告 This file is already in the dataset. This trace is already shown The display contains no traces. Error 错误 Nothing to save: No data was loaded. Save session Qucs-S snp viewer session (*.spar); Open S-parameter Viewer Session SaveDialog Save the modified files 保存修改后的文件 Select files to be saved 选择要保存的文件 Modified Files 修改后的文件 Abort Closing 关闭 Don't Save 不保存 Save Selected 保存 Untitled Untitled Schematic Title 标题 Drawn By: 绘制者： Date: 日期： Revision: 修订： Edit Text 编辑文本 Edits the Text 编辑文本 Edit Text Edits the text file 编辑文本 编辑文本文件 Edit Schematic 编辑原理图 Edits the schematic 编辑原理图 Edit Schematic Edits the schematic 编辑原理图 编辑原理图 Edit Circuit Symbol 编辑电路符号 Edits the symbol for this schematic 编辑此原理图的电路符号 Edit Circuit Symbol Edits the symbol for this schematic 编辑电路符号 编辑此原理图的电路符号 generic 通用 Error 错误 Program admsXml not found: %1 Set the admsXml location on the application settings. 未找到程序admsXml： %1 在&应用程序设置&中设置admsXml位置 Status 状态 Netlist error 网表错误 S2Spice warning ERROR: Cannot create library file "%s". 错误：无法创建库文件"%s" SearchDialog Dialog 对话框 Text to search for 要搜索的文本 Text to replace with 要替换的文本 Ask before replacing 替换后的文本 Case sensitive 区分大小写 Whole words only 全字匹配 Search backwards 向后查找 Next 下一个 Close 关闭 Replace Text 替换文本 Search Text 搜索文本 SettingsDialog Edit File Properties 编辑文件属性 Data Set: 数据集： Browse 浏览 Data Display: 数据显示器： open data display after simulation 仿真结束后打开数据显示器视图 Octave Script: Octave脚本： run script after simulation 仿真结束后运行脚本 Simulation 仿真 show Grid 显示网格 horizontal Grid: 水平网格： vertical Grid: 垂直网格： Grid 网格 no Frame 无版式 DIN A5 landscape A5 横向 DIN A5 portrait A5 纵向 DIN A4 landscape A4 横向 DIN A4 portrait A4 纵向 DIN A3 landscape A3 横向 DIN A3 portrait A3 纵向 Letter landscape 信纸 横向 Letter portrait 信纸 纵向 Frame 版式 OK 确定 Apply 应用 Cancel 取消 SimMessage Qucs Simulation Messages Qucs仿真器信息 Progress: 进度： Errors and Warnings: 错误和警告： Goto display page 转到显示页面 Abort simulation 中止仿真 Starting new simulation on %1 at %2 在 %2 处的 %1 上开始新的仿真 creating netlist... 创建网表... Error 错误 Cannot read netlist! 无法读取网表 ERROR: Simulator is still running! 错误：仿真器仍在运行！ ERROR: Cannot write netlist file! 错误：无法写入网表文件！ ERROR: Cannot simulate a text file! 错误：无法仿真文本文件！ ERROR: Cannot open SPICE file "%1". 错误：无法打开SPICE文件"%1" SIM ERROR: Cannot start QucsConv! SIM错误：无法启动 QucsConv！ done. 结束 ERROR: Cannot create VHDL directory "%1"! 错误：无法创建 VHDL 目录"%1"！ ERROR: Cannot create "%1"! 错误：无法创建"%1"！ ERROR: Cannot start 错误：无法启动 Starting 启动中... ERROR: Simulator crashed! 错误：仿真器崩溃！ Please report this error to qucs-bugs@lists.sourceforge.net 请将此错误报告给 qucs-bugs@lists.sourceforge.ne Close window 关闭窗口 Simulation ended on %1 at %2 仿真在 %1 的 %2 处结束 Ready. 准备 Errors occurred during simulation on %1 at %2 在 %2 的 %1 上进行仿真期间发生错误 Aborted. 中止 Output: ------- 输出： ------- Errors and Warnings: -------------------- 错误和警告： -------------------- Simulation aborted by the user! 仿真被用户中止！ SimSettingsDialog Ngspice executable location Ngspice可执行文件位置 Xyce executable location Xyce可执行文件位置 SpiceOpus executable location SpiceOpus可执行文件位置 Qucsator executable location Qucsator可执行文件位置 Directory to store netlist and simulator output 用于存储网表和模拟器输出的目录 Extra simulator parameters 额外的仿真器参数 Apply changes 应用变更 Cancel 取消 Select ... 选择... Ngspice compatibility mode Ngspice CLI parameters Xyce CLI parameters SpiceOpus CLI parameters SPICE settings SPICE设置 Qucsator settings Qucsator设置 Setup simulators executable location 设置仿真器可执行文件位置 Select Ngspice executable location 选择Ngspice可执行文件位置 Select Xyce executable location 选择Xyce可执行文件位置 Select SpiceOpus executable location 选择SpiceOpus可执行文件位置 Select Qucsator executable location 选择Qucsator可执行文件位置 Select directory to store netlist and simulator output 选择存储网表和仿真器输出的目录 SpiceDialog Edit SPICE Component Properties 编辑SPICE元件属性 Name: 名称： Browse 浏览 File: 文件： Set SPICE parameters string as a plain text. Example: V0=1.0 I0=2.0 Show SPICE parameters: show file name in schematic 在原理图中显示文件名 Edit 编辑 include SPICE simulations 包含SPICE仿真 preprocessor 预处理器 SPICE net nodes: SPICe网络节点： Component ports: 元件端口： Add >> 添加 >> << Remove << 移除 OK 确定 Apply 应用 Cancel 取消 Select a file 选择文件 SPICE netlist SPICE网表 All Files 所有文件 Info 信息 Preprocessing SPICE file "%1". 预处理SPICE文件"%1" Error 错误 Cannot save preprocessed SPICE file "%1". 无法保存预处理过的SPICE文件"%1" Cannot execute "%1". 无法执行"%1" SPICE Preprocessor Error SPICE预处理器错误 Converting SPICE file "%1". 转换SPICE文件"%1" QucsConv Error QucsConv错误 SpiceFile Converting SPICE file "%1". 转换SPICE文件"%1" SpiceLibCompDialog Open 打开 Automatic symbol Symbol from template Symbol from file Show OK 确定 Apply Cancel 取消 No symbol files found at the following path: Check you installation! SPICE model Edit SPICE library device Failed open file: SPICE library parse error. No SUBCKT directive found in library SPICE library parse error Error 错误 Failed to open file: No symbol loaded Failed to load symbol file! Open SPICE library SPICE files (*.cir +.ckt *.sp *.lib) Open symbol file Schematic symbol (*.sym) Warning 警告 All pins must be assigned Set a valid symbol file name There were library file parse error! Cannot apply changes. SweepDialog Bias Points 偏置点 Close 关闭 SymbolWidget Symbol: 符号： ! Drag n'Drop me ! Warning: Symbol '%1' missing in Qucs Library. Drag and Drop may still work. Please contact the developers. 警告：Qucs 库中缺少符号 '%1' 拖放可能仍然有效 请联系开发人员 Error 错误 Cannot open "%1". 无法打开"%1" Library is corrupt. 库已损坏 TextBoxDialog Component: 元件： Apply 应用 Cancel 取消 OK 确定 Editor 编辑器 TextDoc Edit Text Symbol 编辑文本符号 Edits the symbol for this text document 编辑此文本文档的符号 Edit Text Symbol Edits the symbol for this text document 编辑文本符号 编辑此文本文档的符号 VHDL entity VHDL实体 Inserts skeleton of VHDL entity 插入VHDL实体的框架 VHDL entity Inserts the skeleton of a VHDL entity VHDL实体 插入VHDL实体的框架 Verilog module Verilog模块 Inserts skeleton of Verilog module 插入Verilog模块的框架 Verilog module Inserts the skeleton of a Verilog module Verilog模块 插入Verilog模块的框架 Octave function Octave函数 Inserts skeleton of Octave function 插入Octave函数的框架 Octave function Inserts the skeleton of a Octave function Octave函数 插入Octave函数的框架 Find... 查找... Cannot find target: %1 无法找到目标：%1 Replace... 替换... Replace occurrence ? 替换实例？ TransferFuncDialog Define filter transfer function 定义滤波器传递函数 Numerator b[i]= 分子 b[i]= Denominator a[i]= 分母 a[i]= a[i] a[i] b[i] b[i] Accept 确定 Cancel 取消 TunerDialog Tuner Close 关闭 Update Values Reset Values Please select a component to tune Add component 添加元件 Adding components from different schematics is not supported! 不支持从不同的原理图添加元件！ VASettingsDialog Document Settings 文档设置 Code Creation Settings 代码创建设置 Browse 浏览 Output file: 输出文件： Recreate 重建 Icon description: 图标描述： Description: 描述： unspecified device 未指定的设备 NPN/PNP polarity NPN/PNP 极性 NMOS/PMOS polarity NMOS/PMOS 极性 analog only 仅模拟 digital only 仅数字 both 两者都 Ok 确定 Cancel 取消 PNG files PNG文件 Any file 任何文件 Enter an Icon File Name 输入图标文件名 fillFromSpiceDialog Insert .MODEL text here OK 确定 Cancel 取消 Convert number notation Import SPICE model No .MODEL directive found Device type doesn't match the model type. Model found: Models expected: SPICE model parse error Subcircuit model (.SUBCKT) found Modelcard (.MODEL) expected Model LEVEL=%1 is not allowed for unified MOS device Use red SPICE device from Microelectronics group Allowed LEVELS are: 1,2,3,4,5,6,9 Error 错误 main display this help and exit convert Qucs schematic into netlist print Qucs schematic to file (eps needs inkscape) set print page size (default A4) set dpi value (default 96) set color mode (default RGB) set orientation (default portraid) use file as input schematic use file as output netlist create Ngspice netlist create CDL netlist Xyce netlist execute Ngspice/Xyce immediately create component icons under ./bitmaps_generated dump data for documentation: * file with of categories: categories.txt * one directory per category (e.g. ./lumped components/) - CSV file with component data ([comp#]_data.csv) - CSV file with component properties. ([comp#]_props.csv) list component entry formats for schematic and netlist write netlist to console tunerElement Max.: Max.: Min.: Min.: Val.: Val.: Step Step ERROR Entered step is not correct Value not correct