mirror of
https://github.com/ra3xdh/qucs_s
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QList, std::vector etc. has front and back so this changes will reduce refactoring effort.
208 lines
8.1 KiB
C++
208 lines
8.1 KiB
C++
/***************************************************************************
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andor4x4
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----------
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begin : December 2008
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copyright : (C) 2008 by Mike Brinson
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email : mbrin72043@yahoo.co.uk
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***************************************************************************/
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/*
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* andor4x4.cpp - device implementations for andor4x4 module
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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*/
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#include "andor4x4.h"
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#include "node.h"
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#include "misc.h"
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andor4x4::andor4x4()
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{
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Type = isComponent; // Analogue and digital component.
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Description = QObject::tr ("4x4 andor verilog device");
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Props.append (new Property ("TR", "6", false,
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QObject::tr ("transfer function high scaling factor")));
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Props.append (new Property ("Delay", "1 ns", false,
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QObject::tr ("output delay")
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+" ("+QObject::tr ("s")+")"));
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createSymbol ();
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tx = x1 + 19;
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ty = y2 + 4;
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Model = "andor4x4";
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Name = "Y";
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icon_dy = 20;
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}
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Component * andor4x4::newOne()
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{
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andor4x4 * p = new andor4x4();
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p->Props.front()->Value = Props.front()->Value;
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p->recreate(0);
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return p;
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}
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Element * andor4x4::info(QString& Name, char * &BitmapFile, bool getNewOne)
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{
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Name = QObject::tr("4x4 AndOr");
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BitmapFile = (char *) "andor4x4";
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if(getNewOne) return new andor4x4();
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return 0;
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}
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void andor4x4::createSymbol()
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{
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Rects.append(new qucs::Rect(-30, -60, 60, 200, QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::FlatCap, Qt::MiterJoin)));
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Lines.append(new qucs::Line(-30, -10, 0,-10,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line(-30, 40, 0, 40,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line(-30, 90, 0, 90,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line( 0, -60, 0,140,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line(-50,-50,-30,-50,QPen(Qt::darkBlue,2))); //A11
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Lines.append(new qucs::Line(-50,-40,-30,-40,QPen(Qt::darkBlue,2))); //A12
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Lines.append(new qucs::Line(-50,-30,-30,-30,QPen(Qt::darkBlue,2))); //A13
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Lines.append(new qucs::Line(-50,-20,-30,-20,QPen(Qt::darkBlue,2))); //A14
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Lines.append(new qucs::Line(-50, 0,-30, 0,QPen(Qt::darkBlue,2))); //A21
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Lines.append(new qucs::Line(-50, 10,-30, 10,QPen(Qt::darkBlue,2))); //A22
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Lines.append(new qucs::Line(-50, 20,-30, 20,QPen(Qt::darkBlue,2))); //A23
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Lines.append(new qucs::Line(-50, 30,-30, 30,QPen(Qt::darkBlue,2))); //A24
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Lines.append(new qucs::Line(-50, 50, -30, 50,QPen(Qt::darkBlue,2))); //A31
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Lines.append(new qucs::Line(-50, 60, -30, 60,QPen(Qt::darkBlue,2))); //A32
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Lines.append(new qucs::Line(-50, 70,-30, 70,QPen(Qt::darkBlue,2))); //A33
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Lines.append(new qucs::Line(-50, 80, -30, 80,QPen(Qt::darkBlue,2))); //A34
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Lines.append(new qucs::Line(-50, 100,-30,100,QPen(Qt::darkBlue,2))); //A41
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Lines.append(new qucs::Line(-50, 110,-30,110,QPen(Qt::darkBlue,2))); //A42
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Lines.append(new qucs::Line(-50, 120,-30,120,QPen(Qt::darkBlue,2))); //A43
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Lines.append(new qucs::Line(-50, 130,-30,130,QPen(Qt::darkBlue,2))); //A44
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Lines.append(new qucs::Line( 30, 40, 50, 40,QPen(Qt::darkBlue,2))); //Y
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Texts.append(new Text( -20, -60, "&", Qt::darkBlue, 12.0));
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Texts.append(new Text( -20, -10, "&", Qt::darkBlue, 12.0));
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Texts.append(new Text( -20, 40, "&", Qt::darkBlue, 12.0));
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Texts.append(new Text( -20, 90, "&", Qt::darkBlue, 12.0));
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Polylines.append(new qucs::Polyline(
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std::vector<QPointF>{{7, -45}, {17, -40}, {7, -35}}, QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::FlatCap, Qt::MiterJoin)));
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Lines.append(new qucs::Line( 7, -30, 17, -35,QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::FlatCap)));
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Lines.append(new qucs::Line( 22, -30, 22, -45,QPen(Qt::darkBlue,2)));
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Ports.append(new Port(-50,-50)); // A11
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Ports.append(new Port(-50,-40)); // A12
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Ports.append(new Port(-50,-30)); // A13
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Ports.append(new Port(-50,-20)); // A14
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Ports.append(new Port(-50, 0)); // A21
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Ports.append(new Port(-50, 10)); // A22
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Ports.append(new Port(-50, 20)); // A23
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Ports.append(new Port(-50, 30)); // A24
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Ports.append(new Port(-50, 50)); // A31
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Ports.append(new Port(-50, 60)); // A32
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Ports.append(new Port(-50, 70)); // A33
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Ports.append(new Port(-50, 80)); // A34
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Ports.append(new Port(-50,100)); // A41
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Ports.append(new Port(-50,110)); // A42
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Ports.append(new Port(-50,120)); // A43
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Ports.append(new Port(-50,130)); // A44
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Ports.append(new Port( 50, 40)); // Y
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x1 = -50; y1 = -64;
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x2 = 50; y2 = 144;
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}
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QString andor4x4::vhdlCode( int )
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{
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QString s="";
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QString td = Props.at(1)->Value; // delay time
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if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
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td += ";\n";
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QString a11 = Ports.at(0)->Connection->Name;
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QString a12 = Ports.at(1)->Connection->Name;
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QString a13 = Ports.at(2)->Connection->Name;
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QString a14 = Ports.at(3)->Connection->Name;
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QString a21 = Ports.at(4)->Connection->Name;
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QString a22 = Ports.at(5)->Connection->Name;
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QString a23 = Ports.at(6)->Connection->Name;
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QString a24 = Ports.at(7)->Connection->Name;
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QString a31 = Ports.at(8)->Connection->Name;
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QString a32 = Ports.at(9)->Connection->Name;
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QString a33 = Ports.at(10)->Connection->Name;
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QString a34 = Ports.at(11)->Connection->Name;
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QString a41 = Ports.at(12)->Connection->Name;
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QString a42 = Ports.at(13)->Connection->Name;
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QString a43 = Ports.at(14)->Connection->Name;
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QString a44 = Ports.at(15)->Connection->Name;
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QString y = Ports.at(16)->Connection->Name;
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s = "\n " + Name + ":process (" +
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a11 + ", " + a12 + ", " + a13 + ", " + a14 + ", " +
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a21 + ", " + a22 + ", " + a23 + ", " + a24 + ", " +
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a31 + ", " + a32 + ", " + a33 + ", " + a34 + ", " +
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a41 + ", " + a42 + ", " + a43 + ", " + a44 + ")\n" +
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" begin\n " +
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y + " <= " + "(" + a11 + " and " + a12 + " and " + a13 + " and " + a14 + ") or " +
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"(" + a21 + " and " + a22 + " and " + a23 + " and " + a24 + ") or\n" +
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" (" + a31 + " and " + a32 + " and " + a33 + " and " + a34 + ") or " +
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"(" + a41 + " and " + a42 + " and " + a43 + " and " + a43 + ")" + td +
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" end process;\n";
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return s;
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}
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QString andor4x4::verilogCode( int )
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{
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QString td = Props.at(1)->Value; // delay time
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if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
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QString a11 = Ports.at(0)->Connection->Name;
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QString a12 = Ports.at(1)->Connection->Name;
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QString a13 = Ports.at(2)->Connection->Name;
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QString a14 = Ports.at(3)->Connection->Name;
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QString a21 = Ports.at(4)->Connection->Name;
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QString a22 = Ports.at(5)->Connection->Name;
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QString a23 = Ports.at(6)->Connection->Name;
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QString a24 = Ports.at(7)->Connection->Name;
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QString a31 = Ports.at(8)->Connection->Name;
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QString a32 = Ports.at(9)->Connection->Name;
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QString a33 = Ports.at(10)->Connection->Name;
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QString a34 = Ports.at(11)->Connection->Name;
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QString a41 = Ports.at(12)->Connection->Name;
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QString a42 = Ports.at(13)->Connection->Name;
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QString a43 = Ports.at(14)->Connection->Name;
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QString a44 = Ports.at(15)->Connection->Name;
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QString y = Ports.at(16)->Connection->Name;
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QString l = "";
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QString v = "net_reg" + Name + y;
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l = "\n // " + Name + " 4x4 andor\n" +
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" assign " + y + " = " + v + ";\n" +
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" reg " + v + " = 0;\n" +
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" always @ (" + a11 + " or " + a12 + " or " + a13 + " or " + a14 + " or "
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+ a21 + " or " + a22 + " or " + a23 + " or " + a24 + " or "
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+ a31 + " or " + a32 + " or " + a33 + " or " + a34 + " or "
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+ a41 + " or " + a42 + " or " + a43 + " or " + a44 + ")\n " +
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" " + v + " <=" + td + " (" + a11 + " && " + a12 + " && " + a13 + " && " + a14 +")" + " || " +
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"(" + a21 + " && " + a22 + " && " + a23 + " && " + a24 +")" + " ||\n" +
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" (" + a31 + " && " + a32 + " && " + a33 + " && " + a34 +")" + " || " +
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"(" + a41 + " && " + a42 + " && " + a43 + " && " + a44 +");\n" ;
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return l;
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}
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