mirror of
https://github.com/ra3xdh/qucs_s
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909f02340d
-introduced new type spicecompat::SpiceDialect to distinguish SPICE, Xyce and CDL -adapt dependent components accordingly Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
200 lines
6.8 KiB
C++
200 lines
6.8 KiB
C++
/***************************************************************************
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dff_SR
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--------
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begin : December 2008
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copyright : (C) 2008 by Mike Brinson
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email : mbrin72043@yahoo.co.uk
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***************************************************************************/
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/*
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* dff_SR.cpp - device implementations for dff_SR module
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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*/
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#include "dff_SR.h"
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#include "node.h"
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#include "misc.h"
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#include "extsimkernels/spicecompat.h"
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dff_SR::dff_SR()
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{
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Type = isComponent; // Analogue and digital component.
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Description = QObject::tr ("D flip flop with set and reset verilog device");
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Props.append (new Property ("TR_H", "6", false,
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QObject::tr ("cross coupled gate transfer function high scaling factor")));
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Props.append (new Property ("TR_L", "5", false,
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QObject::tr ("cross coupled gate transfer function low scaling factor")));
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Props.append (new Property ("Delay", "1 ns", false,
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QObject::tr ("cross coupled gate delay")
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+" ("+QObject::tr ("s")+")"));
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createSymbol ();
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tx = x1 + 4;
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ty = y2 + 4;
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Model = "dff_SR";
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Name = "Y";
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SpiceModel = "A";
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}
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Component * dff_SR::newOne()
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{
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dff_SR * p = new dff_SR();
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p->Props.front()->Value = Props.front()->Value;
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p->recreate(0);
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return p;
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}
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Element * dff_SR::info(QString& Name, char * &BitmapFile, bool getNewOne)
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{
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Name = QObject::tr("D-FlipFlop w/ SR");
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BitmapFile = (char *) "dff_SR";
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if(getNewOne) return new dff_SR();
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return 0;
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}
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void dff_SR::createSymbol()
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{
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// put in here symbol drawing code and terminal definitions
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Rects.append(new qucs::Rect(-30, -40, 60, 80, QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::SquareCap, Qt::MiterJoin)));
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Lines.append(new qucs::Line(-50,-20,-30,-20,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line(-50, 20,-30, 20,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line( 30, 20, 50, 20,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line( 30,-20, 50,-20,QPen(Qt::darkBlue,2)));
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Polylines.append(new qucs::Polyline(
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std::vector<QPointF>{{-30, 10}, {-20, 20}, {-30, 30}}, QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::FlatCap, Qt::MiterJoin)
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));
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Lines.append(new qucs::Line( 0, -50, 0, -60,QPen(Qt::darkBlue,2)));
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Lines.append(new qucs::Line( 0, 50, 0, 60,QPen(Qt::darkBlue,2)));
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Ellipses.append(new qucs::Ellips( -5,-50, 10, 10, QPen(Qt::darkBlue,2)));
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Ellipses.append(new qucs::Ellips( -5, 40, 10, 10, QPen(Qt::darkBlue,2)));
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Texts.append(new Text(-25,-28, "D", Qt::darkBlue, 12.0));
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Texts.append(new Text( 15.5,-28, "Q", Qt::darkBlue, 12.0));
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Texts.append(new Text( -4,-39, "S", Qt::darkBlue, 12.0));
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Texts.append(new Text( 15.5, 12, "Q", Qt::darkBlue, 12.0));
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Texts.last()->over=true;
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Texts.append(new Text( -4, 24, "R", Qt::darkBlue, 12.0));
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Ports.append(new Port(0, -60)); // S
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Ports.append(new Port(-50,-20)); // D
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Ports.append(new Port(-50, 20)); // CLK
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Ports.append(new Port( 0, 60)); // R
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Ports.append(new Port( 50, 20)); // QB
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Ports.append(new Port( 50,-20)); // Q
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x1 = -50; y1 = -60;
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x2 = 50; y2 = 60;
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}
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QString dff_SR::vhdlCode( int )
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{
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QString s="";
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QString td = Props.at(2)->Value; // delay time
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if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
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td += ";\n";
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QString S = Ports.at(0)->Connection->Name;
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QString D = Ports.at(1)->Connection->Name;
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QString CLK = Ports.at(2)->Connection->Name;
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QString R = Ports.at(3)->Connection->Name;
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QString QB = Ports.at(4)->Connection->Name;
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QString Q = Ports.at(5)->Connection->Name;
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s = "\n "+Name+":process ("+S+", "+CLK+", "+R+") is\n"+
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" variable state : std_logic;\n"+
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" begin\n" +
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" if ("+S+" = '0') then\n"+
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" state := '1';\n"+
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" elsif ("+R+" = '0') then\n"+
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" state := '0';\n"+
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" elsif ("+CLK+" = '1' and "+CLK+"'event) then\n"+
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" state := "+D+";\n"+
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" end if;\n"+
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" "+Q+" <= state"+td+
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" "+QB+" <= not state"+td+
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" end process;\n";
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return s;
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}
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QString dff_SR::verilogCode( int )
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{
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QString td = Props.at(2)->Value; // delay time
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if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
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QString l = "";
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QString S = Ports.at(0)->Connection->Name;
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QString D = Ports.at(1)->Connection->Name;
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QString CLK = Ports.at(2)->Connection->Name;
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QString R = Ports.at(3)->Connection->Name;
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QString QB = Ports.at(4)->Connection->Name;
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QString Q = Ports.at(5)->Connection->Name;
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QString QR = "Q_reg" + Name + Q;
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QString QBR = "QB_reg" + Name + QB;
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QString ST = "Q_state" + Name;
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l = "\n // "+Name+" d flip-flop with set and reset\n"+
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" assign "+Q+" = "+QR+";\n"+
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" reg "+QR+" = 0;\n"+
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" assign "+QB+" = "+QBR+";\n"+
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" reg "+QBR+" = 1;\n"+
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" reg "+ST+" = 0;\n"+
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" always @ (posedge "+CLK+")\n"+
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" begin\n"+
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" if ("+R+" == 1 && "+S+" == 1)\n"+
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" begin\n"+
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" "+ST+" = "+D+";\n"+
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" "+QR+" <="+td+" "+ST+";\n"+
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" "+QBR+" <="+td+" ~"+ST+";\n"+
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" end\n"+
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" end\n"+
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" always @ ("+R+")\n"+
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" begin\n"+
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" if ("+R+" == 0) "+ST+" = 0;\n"+
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" "+QR+" <="+td+" "+ST+";\n"+
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" "+QBR+" <="+td+" ~"+ST+";\n"+
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" end\n"+
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" always @ ("+S+")\n"+
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" begin if ("+S+" == 0) "+ST+" = 1;\n"+
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" "+QR+" <="+td+" "+ST+";\n"+
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" "+QBR+" <="+td+" ~"+ST+";\n"+
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" end\n";
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return l;
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}
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QString dff_SR::spice_netlist(spicecompat::SpiceDialect dialect /* = spicecompat::SPICEDefault */)
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{
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if (dialect == spicecompat::SPICEXyce) return QString();
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QString s = SpiceModel + Name;
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QString tmp_model = "model_" + Name;
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QString td = spicecompat::normalize_value(getProperty("Delay")->Value);
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QString SET = spicecompat::normalize_node_name(Ports.at(0)->Connection->Name);
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QString D = spicecompat::normalize_node_name(Ports.at(1)->Connection->Name);
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QString CLK = spicecompat::normalize_node_name(Ports.at(2)->Connection->Name);
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QString RESET = spicecompat::normalize_node_name(Ports.at(3)->Connection->Name);
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QString QB = spicecompat::normalize_node_name(Ports.at(4)->Connection->Name);
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QString Q = spicecompat::normalize_node_name(Ports.at(5)->Connection->Name);
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s += " " + D + " " + CLK + " " + SET + " " + RESET + " " + Q + " " + QB;
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s += " " + tmp_model + "\n";
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s += QStringLiteral(".model %1 d_dff(clk_delay=%2 set_delay=%2 reset_delay=%2 rise_delay=%2 fall_delay=%2)\n")
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.arg(tmp_model).arg(td);
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return s;
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}
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