mirror of
https://github.com/ra3xdh/qucs_s
synced 2025-03-28 21:13:26 +00:00
b7a0e1be81
QList, std::vector etc. has front and back so this changes will reduce refactoring effort.
134 lines
4.2 KiB
C++
134 lines
4.2 KiB
C++
/***************************************************************************
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fa1b
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------
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begin : December 2008
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copyright : (C) 2008 by Mike Brinson
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email : mbrin72043@yahoo.co.uk
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***************************************************************************/
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/*
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* fa1b.cpp - device implementations for fa1b module
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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*/
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#include "fa1b.h"
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#include "node.h"
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#include "misc.h"
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fa1b::fa1b()
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{
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Type = isComponent; // Analogue and digital component.
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Description = QObject::tr ("1bit full adder verilog device");
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Props.append (new Property ("TR", "6", false,
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QObject::tr ("transfer function high scaling factor")));
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Props.append (new Property ("Delay", "1 ns", false,
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QObject::tr ("output delay")
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+" ("+QObject::tr ("s")+")"));
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createSymbol ();
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tx = x1 + 19;
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ty = y2 + 4;
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Model = "fa1b";
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Name = "Y";
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}
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Component * fa1b::newOne()
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{
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fa1b * p = new fa1b();
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p->Props.front()->Value = Props.front()->Value;
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p->recreate(0);
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return p;
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}
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Element * fa1b::info(QString& Name, char * &BitmapFile, bool getNewOne)
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{
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Name = QObject::tr("1Bit FullAdder");
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BitmapFile = (char *) "fa1b";
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if(getNewOne) return new fa1b();
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return 0;
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}
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void fa1b::createSymbol()
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{
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Rects.append(new qucs::Rect(-30, -40, 60, 90, QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::SquareCap, Qt::MiterJoin)));
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Lines.append(new qucs::Line(-50,-10,-30,-10,QPen(Qt::darkBlue,2))); // A
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Lines.append(new qucs::Line(-50, 10,-30, 10,QPen(Qt::darkBlue,2))); // B
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Lines.append(new qucs::Line(-50, 30,-30, 30,QPen(Qt::darkBlue,2))); // CI
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Lines.append(new qucs::Line( 30, 10, 50, 10,QPen(Qt::darkBlue,2))); // CO
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Lines.append(new qucs::Line( 30,-10, 50,-10,QPen(Qt::darkBlue,2))); // S
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Texts.append(new Text(-25, 22, "CI", Qt::darkBlue, 12.0));
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Texts.append(new Text( 7, 2, "CO", Qt::darkBlue, 12.0));
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Texts.append(new Text(-9.5, -40, "Σ", Qt::darkBlue, 29.0));
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Ports.append(new Port(-50,-10)); // A
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Ports.append(new Port(-50, 10)); // B
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Ports.append(new Port(-50, 30)); // CI
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Ports.append(new Port( 50, 10)); // CO
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Ports.append(new Port( 50,-10)); // S
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x1 = -50; y1 = -44;
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x2 = 50; y2 = 54;
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}
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QString fa1b::vhdlCode( int )
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{
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QString s="";
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QString td = Props.at(1)->Value; // delay time
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if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
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td += ";\n";
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QString A = Ports.at(0)->Connection->Name;
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QString B = Ports.at(1)->Connection->Name;
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QString CI = Ports.at(2)->Connection->Name;
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QString CO = Ports.at(3)->Connection->Name;
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QString S = Ports.at(4)->Connection->Name;
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s = "\n " + Name + ":process (" + A + ", " + B + ", " + CI + ")\n" +
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" begin\n" +
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" " + CO + " <= (" + A + " and " + B + ") or (" + CI + " and (" + A + " xor " + B + "))" + td +
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" " + S + " <= " + CI + " xor " + A + " xor " + B + td +
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" end process;\n";
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return s;
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}
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QString fa1b::verilogCode( int )
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{
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QString td = Props.at(1)->Value; // delay time
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if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
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QString l = "";
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QString A = Ports.at(0)->Connection->Name;
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QString B = Ports.at(1)->Connection->Name;
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QString CI = Ports.at(2)->Connection->Name;
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QString CO = Ports.at(3)->Connection->Name;
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QString S = Ports.at(4)->Connection->Name;
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QString COR = "CO_reg" + Name + CO;
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QString SR = "S_reg" + Name + S;
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l = "\n // " + Name + " 1bit fulladder\n" +
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" assign " + CO + " = " + COR + ";\n" +
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" reg " + COR + " = 0;\n" +
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" assign " + S + " = " + SR + ";\n" +
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" reg " + SR + " = 0;\n" +
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" always @ ("+ A + " or " + B + " or " + CI + ")\n" +
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" begin\n" +
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" " + COR + " <=" + td + " (" + A + " && " + B + ") || " + CI + " && " + "(" + A + " ^ " + B + ");\n" +
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" " + SR + " <=" + td + " (" + CI + " ^ " + A + " ^ " + B + ");\n" +
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" end\n";
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return l;
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}
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