mirror of
https://github.com/ra3xdh/qucs_s
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b7a0e1be81
QList, std::vector etc. has front and back so this changes will reduce refactoring effort.
139 lines
4.2 KiB
C++
139 lines
4.2 KiB
C++
/***************************************************************************
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gatedDlatch
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-------------
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begin : January 2009
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copyright : (C) 2008 by Mike Brinson
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email : mbrin72043@yahoo.co.uk
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***************************************************************************/
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/*
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* gatedDlatch.cpp - device implementations for gatedDlatch module
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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*/
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#include "gatedDlatch.h"
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#include "node.h"
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#include "misc.h"
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gatedDlatch::gatedDlatch()
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{
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Type = isComponent; // Analogue and digital component.
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Description = QObject::tr ("gated D latch verilog device");
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Props.append (new Property ("TR_H", "6", false,
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QObject::tr ("cross coupled gate transfer function high scaling factor")));
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Props.append (new Property ("TR_L", "5", false,
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QObject::tr ("cross coupled gate transfer function low scaling factor")));
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Props.append (new Property ("Delay", "1 ns", false,
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QObject::tr ("cross coupled gate delay")
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+" ("+QObject::tr ("s")+")"));
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createSymbol ();
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tx = x1 + 19;
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ty = y2 + 4;
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Model = "gatedDlatch";
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Name = "Y";
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}
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Component * gatedDlatch::newOne()
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{
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gatedDlatch * p = new gatedDlatch();
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p->Props.front()->Value = Props.front()->Value;
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p->recreate(0);
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return p;
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}
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Element * gatedDlatch::info(QString& Name, char * &BitmapFile, bool getNewOne)
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{
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Name = QObject::tr("Gated D-Latch");
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BitmapFile = (char *) "gatedDlatch";
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if(getNewOne) return new gatedDlatch();
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return 0;
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}
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void gatedDlatch::createSymbol()
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{
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Rects.append(new qucs::Rect(-30, -40, 60, 80,QPen(Qt::darkBlue,2, Qt::SolidLine, Qt::SquareCap, Qt::MiterJoin)));
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Lines.append(new qucs::Line(-50,-20,-30,-20,QPen(Qt::darkBlue,2))); // D
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Lines.append(new qucs::Line(-50, 20,-30, 20,QPen(Qt::darkBlue,2))); // C
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Lines.append(new qucs::Line( 40, 20, 50, 20,QPen(Qt::darkBlue,2))); // QB
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Lines.append(new qucs::Line( 30,-20, 50,-20,QPen(Qt::darkBlue,2))); // Q
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Arcs.append(new qucs::Arc( 30, 15, 10, 10, 0, 16*360, QPen(Qt::darkBlue,2)));
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Texts.append(new Text(-25,-28, "D", Qt::darkBlue, 12.0));
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Texts.append(new Text(-25, 12, "C", Qt::darkBlue, 12.0));
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Texts.append(new Text( 13,-28, "Q", Qt::darkBlue, 12.0));
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Texts.append(new Text( 13, 12, "Q", Qt::darkBlue, 12.0));
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Texts.last()->over=true;
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Ports.append(new Port(-50,-20)); // D
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Ports.append(new Port(-50, 20)); // C
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Ports.append(new Port( 50, 20)); // QB
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Ports.append(new Port( 50,-20)); // Q
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x1 = -50; y1 = -44;
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x2 = 50; y2 = 44;
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}
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QString gatedDlatch::vhdlCode( int )
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{
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QString s="";
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QString td = Props.at(2)->Value; // delay time
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if(!misc::VHDL_Delay(td, Name)) return td; // time has not VHDL format
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td += ";\n";
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QString D = Ports.at(0)->Connection->Name;
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QString C = Ports.at(1)->Connection->Name;
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QString QB = Ports.at(2)->Connection->Name;
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QString Q = Ports.at(3)->Connection->Name;
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s = "\n "+Name+":process ("+D+", "+C+")\n"+
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" begin\n" +
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" if ("+C+" = '1') then\n"+
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" "+Q+" <= "+D+td+
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" "+QB+" <= not "+D+td+
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" end if;\n"+
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" end process;\n";
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return s;
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}
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QString gatedDlatch::verilogCode( int )
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{
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QString td = Props.at(2)->Value; // delay time
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if(!misc::Verilog_Delay(td, Name)) return td; // time does not have VHDL format
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QString l = "";
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QString D = Ports.at(0)->Connection->Name;
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QString C = Ports.at(1)->Connection->Name;
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QString QB = Ports.at(2)->Connection->Name;
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QString Q = Ports.at(3)->Connection->Name;
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QString QR = "Q_reg" + Name + Q;
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QString QBR = "QB_reg" + Name + QB;
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l = "\n // "+Name+" gated d latch\n"+
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" assign "+Q+" = "+QR+";\n"+
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" reg "+QR+" = 0;\n"+
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" assign "+QB+" = "+QBR+";\n"+
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" reg "+QBR+" = 0;\n"+
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" always @ ("+D+" or "+C+")\n"+
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" begin\n"+
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" if ("+C+" == 1)\n"+
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" begin\n"+
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" " +QR+" <="+td+" "+D+";\n"+
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" " +QBR+" <="+td+" ~"+D+";\n" +
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" end\n"+
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" end\n";
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return l;
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}
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