mirror of
https://github.com/ra3xdh/qucs_s
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125 lines
3.8 KiB
C++
125 lines
3.8 KiB
C++
/***************************************************************************
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vafile.cpp
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------------
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begin : Sun Oct 26 2009
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copyright : (C) 2009 by Stefan Jahn
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email : stefa@lkcc.org
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***************************************************************************/
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/***************************************************************************
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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***************************************************************************/
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#include <QString>
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#include <QRegularExpression>
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#include <QFile>
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#include <QFileInfo>
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#include "vafile.h"
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// -------------------------------------------------------
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VerilogA_File_Info::VerilogA_File_Info () {
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ModuleName = "";
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PortNames = "";
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}
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// -------------------------------------------------------
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VerilogA_File_Info::VerilogA_File_Info (QString File, bool isfile)
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{
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if (isfile) {
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QFile f (File);
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if (!f.open (QIODevice::ReadOnly))
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File = "";
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else {
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QByteArray FileContent = f.readAll ();
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File = QString (FileContent);
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}
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f.close();
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}
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QString s;
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int i=0, j, k=0;
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while((i=File.indexOf("//", i)) >= 0) { // remove all Verilog-A comments
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j = File.indexOf('\n', i+2); // (This also finds "//" within a ...
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if(j < 0) // string, but as no strings are ...
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File = File.left(i); // allowed in module headers, it ...
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else // does not matter.)
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File.remove(i, j-i);
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}
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i=0;
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while((i=File.indexOf("/*", i)) >= 0) { // remove all Verilog-A comments
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j = File.indexOf("*/", i+2); // (This also finds "/*" within a ...
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if(j < 0) // string, but as no strings are ...
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File = File.left(i); // allowed in module headers, it ...
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else // does not matter.)
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File.remove(i, j-i+2);
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}
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QRegularExpression Expr;//,Expr1;
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//Expr.setPatternOptions(QRegularExpression::CaseInsensitiveOption);
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//Expr1.setPatternOptions(Qt::CaseSensitive);
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k--;
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Expr.setPattern("\\bmodule\\b"); // start of last module
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k = File.lastIndexOf(Expr, k);
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if(k < 0)
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return;
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Expr.setPattern("\\bendmodule\\b"); // end of last module
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i = File.indexOf(Expr, k+7);
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if(i < 0)
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return;
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s = File.mid(k+7, i-k-7); // cut out module declaration
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Expr.setPattern("\\b");
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i = s.indexOf(Expr);
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if(i < 0)
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return;
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j = s.indexOf(Expr, i+1);
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if(j < 0)
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return;
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ModuleName = s.mid(i, j-i); // save module name
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i = s.indexOf('(', j);
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if(i < 0)
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return;
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j = s.indexOf(')', i);
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if(j < 0)
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return;
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s = s.mid(i+1, j-i-1);
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// parse ports, i.e. network connections
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PortNames = parsePorts (s, 0);
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}
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// -------------------------------------------------------
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QString VerilogA_File_Info::parsePorts(QString s, int i)
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{
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QRegularExpression Expr,Expr1;
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//Expr.setCaseSensitivity(Qt::CaseSensitive);
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//Expr1.setCaseSensitivity(Qt::CaseSensitive);
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int j;
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i = 0; // remove all Verilog-A identifiers (e.g. "input")
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Expr.setPattern("(\\binput\\b|\\boutput\\b|\\binout\\b)");
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Expr1.setPattern("(\\b)");
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while((i=s.indexOf(Expr, i)) >= 0) {
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j = s.indexOf(Expr1, i+1);
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if(j < 0)
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s = s.left(i);
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else
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s.remove(i, j-i);
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}
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s.remove(' ');
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s.remove('\n');
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s.remove('\t');
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return s;
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}
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