mirror of
https://github.com/ra3xdh/qucs_s
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9d55075db8
Introduced very basic c++ coding style for the extsimkernels subsystem based on https://google.github.io/styleguide/cppguide.html: -Prefix class attributes with a_ (much more better readability!) -Class member initialization via constructor member initialization list -No public class attributes Signed-off-by: ThomasZecha <zecha@ihp-microelectronics.com>
58 lines
1.6 KiB
C++
58 lines
1.6 KiB
C++
/*
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* verilogawriter.h - Subcircuit to Verilog-A module converter declaration
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*
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* Copyright (C) 2015, Vadim Kuznetsov, ra3xdh@gmail.com
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*
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* This file is part of Qucs
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*
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* Qucs is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Qucs. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef VERILOGAWRITER_H
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#define VERILOGAWRITER_H
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#include <QString>
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#include <QStringList>
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#include <QTextStream>
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#include <schematic.h>
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#include <QRegularExpression>
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/*!
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\file verilogawriter.h
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\brief Declaration of the AbstractSpiceKernel class and vacompat namespace
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*/
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namespace vacompat {
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QString normalize_value(QString Value);
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void convert_functions(QStringList &tokens);
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QString normalize_voltage(QString &plus, QString &minus, bool left_side = false); // Exclude gnd nodes from
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QString normalize_current(QString &plus, QString &minus, bool left_side = false); // currents and voltages
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}
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class VerilogAwriter
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{
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public:
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VerilogAwriter();
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~VerilogAwriter();
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protected:
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bool prepareToVerilogA(Schematic *sch);
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public:
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bool createVA_module(QTextStream &stream, Schematic *sch);
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};
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#endif // VERILOGAWRITER_H
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