mirror of
https://github.com/ra3xdh/qucs_s
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7c3394ccd3
libcomp.cpp libcomp.h optimizedialog.h spicefile.h subcircuit.cpp verilogfile.cpp verilogfile.h vhdlfile.cpp vhdlfile.h except componentdialog and spicedialog
303 lines
8.2 KiB
C++
303 lines
8.2 KiB
C++
/***************************************************************************
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verilogfile.cpp
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---------------
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begin : Sat Mar 31 2007
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copyright : (C) 2007 by Stefan Jahn
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email : stefa@lkcc.org
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***************************************************************************/
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/***************************************************************************
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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***************************************************************************/
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#include <QtGui>
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#include "verilogfile.h"
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#include "qucs.h"
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#include "main.h"
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#include "schematic.h"
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#include <QTextStream>
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#include <QRegExp>
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#include <QFileInfo>
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Verilog_File::Verilog_File()
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{
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Type = isDigitalComponent;
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Description = QObject::tr("Verilog file");
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Props.append(new Property("File", "sub.v", false,
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QObject::tr("Name of Verilog file")));
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Model = "Verilog";
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Name = "X";
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// Do NOT call createSymbol() here. But create port to let it rotate.
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Ports.append(new Port(0, 0));
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}
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// -------------------------------------------------------
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Component* Verilog_File::newOne()
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{
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Verilog_File *p = new Verilog_File();
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p->Props.getFirst()->Value = Props.getFirst()->Value;
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p->recreate(0);
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return p;
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}
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// -------------------------------------------------------
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Element* Verilog_File::info(QString& Name, char* &BitmapFile, bool getNewOne)
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{
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Name = QObject::tr("Verilog file");
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BitmapFile = (char *) "vhdlfile";
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if(getNewOne) {
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Verilog_File *p = new Verilog_File();
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p->recreate(0); // createSymbol() is NOT called in constructor !!!
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return p;
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}
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return 0;
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}
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// -------------------------------------------------------
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QString Verilog_File::verilogCode(int)
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{
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QString s;
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QListIterator<Port *> iport(Ports);
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Port *pp = iport.next();
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if(pp) {
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s = " " + ModuleName + " " + Name + " (";
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// output all node names
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if(pp) s += pp->Connection->Name;
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while(iport.hasNext())
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{
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pp = iport.next();
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s += ", "+pp->Connection->Name; // node names
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}
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s += ");\n";
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}
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return s;
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}
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// -------------------------------------------------------
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// Returns a comma separated list of the port names of the last
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// entity in this file.
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QString Verilog_File::loadFile()
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{
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QString s, File(Props.getFirst()->Value);
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QFileInfo Info(File);
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if(Info.isRelative())
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File = QucsSettings.QucsWorkDir.filePath(File);
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QFile f(File);
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if(!f.open(QIODevice::ReadOnly))
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return QString("");
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QTextStream stream(&f);
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File = stream.read(); // QString is better for "find" function
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f.close();
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// parse ports, i.e. network connections
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Verilog_File_Info VInfo(File);
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ModuleName = VInfo.ModuleName;
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return VInfo.PortNames;
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}
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// -------------------------------------------------------
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void Verilog_File::createSymbol()
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{
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QFontMetrics metrics(QucsSettings.font); // get size of text
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int fHeight = metrics.lineSpacing();
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int No = 0;
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QString tmp, PortNames = loadFile();
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if(!PortNames.isEmpty())
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No = PortNames.count(',') + 1;
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#define HALFWIDTH 24
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int h = 30*((No-1)/2) + 15;
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Lines.append(new Line(-HALFWIDTH, -h, HALFWIDTH, -h,QPen(Qt::darkBlue,2)));
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Lines.append(new Line( HALFWIDTH, -h, HALFWIDTH, h,QPen(Qt::darkBlue,2)));
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Lines.append(new Line(-HALFWIDTH, h, HALFWIDTH, h,QPen(Qt::darkBlue,2)));
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Lines.append(new Line(-HALFWIDTH, -h,-HALFWIDTH, h,QPen(Qt::darkBlue,2)));
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tmp = QObject::tr("verilog");
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int w = metrics.width(tmp);
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Texts.append(new Text(w/-2, fHeight/-2, tmp));
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int y = 15-h, i = 0;
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while(i<No) {
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Lines.append(new Line(-30, y,-HALFWIDTH, y,QPen(Qt::darkBlue,2)));
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Ports.append(new Port(-30, y));
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tmp = PortNames.section(',', i, i);
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w = metrics.width(tmp);
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Texts.append(new Text(-26-w, y-fHeight-2, tmp));
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i++;
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if(i == No) break;
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Lines.append(new Line(HALFWIDTH, y, 30, y,QPen(Qt::darkBlue,2)));
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Ports.append(new Port( 30, y));
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tmp = PortNames.section(',', i, i);
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Texts.append(new Text( 27, y-fHeight-2, tmp));
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y += 60;
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i++;
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}
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x1 = -30; y1 = -h-2;
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x2 = 30; y2 = h+2;
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tx = x1+4;
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ty = y2+4;
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}
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// -------------------------------------------------------
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QString Verilog_File::getSubcircuitFile()
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{
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// construct full filename
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QString FileName = Props.getFirst()->Value;
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return properAbsFileName(FileName);
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}
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// -------------------------------------------------------
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bool Verilog_File::createSubNetlist(QTextStream *stream)
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{
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ErrText = "";
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// check filename
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QString FileName = Props.getFirst()->Value;
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if(FileName.isEmpty()) {
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ErrText += QObject::tr("ERROR: No file name in %1 component \"%2\".").
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arg(Model).arg(Name);
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return false;
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}
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// construct full filename
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FileName = getSubcircuitFile();
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// open file for reading
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QFile f(FileName);
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if(!f.open(QIODevice::ReadOnly)) {
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ErrText += QObject::tr("ERROR: Cannot open %1 file \"%2\".").
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arg(Model).arg(FileName);
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return false;
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}
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// write the whole Verilog file into the netlist output
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QByteArray FileContent = f.readAll();
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f.close();
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(*stream) << '\n';
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//?stream->writeRawBytes(FileContent.data(), FileContent.size());
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(*stream) << FileContent.data();
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(*stream) << '\n';
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return true;
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}
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// -------------------------------------------------------
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Verilog_File_Info::Verilog_File_Info()
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{
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ModuleName = "";
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PortNames = "";
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}
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// -------------------------------------------------------
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Verilog_File_Info::Verilog_File_Info(QString File, bool isfile)
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{
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if (isfile) {
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QFile f(File);
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if(!f.open(QIODevice::ReadOnly))
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File = "";
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else {
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QByteArray FileContent = f.readAll();
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File = QString(FileContent);
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}
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f.close();
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}
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QString s;
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int i=0, j, k=0;
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while((i=File.find("//", i)) >= 0) { // remove all Verilog comments
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j = File.find('\n', i+2); // (This also finds "//" within a ...
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if(j < 0) // string, but as no strings are ...
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File = File.left(i); // allowed in module headers, it ...
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else // does not matter.)
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File.remove(i, j-i);
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}
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i=0;
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while((i=File.find("/*", i)) >= 0) { // remove all Verilog comments
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j = File.find("*/", i+2); // (This also finds "/*" within a ...
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if(j < 0) // string, but as no strings are ...
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File = File.left(i); // allowed in module headers, it ...
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else // does not matter.)
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File.remove(i, j-i+2);
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}
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QRegExp Expr,Expr1;
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Expr.setCaseSensitive(true);
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Expr1.setCaseSensitive(true);
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k--;
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Expr.setPattern("\\bmodule\\b"); // start of last module
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k = File.findRev(Expr, k);
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if(k < 0)
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return;
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Expr.setPattern("\\bendmodule\\b"); // end of last module
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i = File.find(Expr, k+7);
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if(i < 0)
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return;
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s = File.mid(k+7, i-k-7); // cut out module declaration
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Expr.setPattern("\\b");
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i = s.find(Expr);
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if(i < 0)
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return;
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j = s.find(Expr, i+1);
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if(j < 0)
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return;
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ModuleName = s.mid(i, j-i); // save module name
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i = s.find('(', j);
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if(i < 0)
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return;
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j = s.find(')', i);
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if(j < 0)
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return;
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s = s.mid(i+1, j-i-1);
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// parse ports, i.e. network connections; and generics, i.e. parameters
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PortNames = parsePorts (s, 0);
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}
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// -------------------------------------------------------
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QString Verilog_File_Info::parsePorts(QString s, int i)
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{
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QRegExp Expr,Expr1;
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Expr.setCaseSensitive(true);
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Expr1.setCaseSensitive(true);
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int j;
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i = 0; // remove all Verilog identifiers (e.g. "input")
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Expr.setPattern("(\\binput\\b|\\boutput\\b|\\binout\\b)");
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Expr1.setPattern("(\\b)");
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while((i=s.find(Expr, i)) >= 0) {
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j = s.find(Expr1, i+1);
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if(j < 0)
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s = s.left(i);
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else
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s.remove(i, j-i);
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}
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s.remove(' ');
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s.remove('\n');
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s.remove('\t');
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return s;
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}
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